commit 2bfe26b209b018b4fcc7659facb1ee9a6f9304bd Author: Launchcore Date: Thu Nov 6 09:20:56 2025 +0800 Initial commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..cfb717c --- /dev/null +++ b/.gitignore @@ -0,0 +1,29 @@ +### OrCAD ### +### Cadence Design Systm's OrCAD ### +*.dat + +### Windows ### +# Windows thumbnail cache files +Thumbs.db +Thumbs.db:encryptable +ehthumbs.db +ehthumbs_vista.db + +# Dump file +*.stackdump + +# Folder config file +[Dd]esktop.ini + +# Recycle Bin used on file shares +$RECYCLE.BIN/ + +# Windows Installer files +*.cab +*.msi +*.msix +*.msm +*.msp + +# Windows shortcuts +*.lnk \ No newline at end of file diff --git a/AnalogCircuitExp1/1-1/ANALOGCIRCUITEXP1.DSN b/AnalogCircuitExp1/1-1/ANALOGCIRCUITEXP1.DSN new file mode 100644 index 0000000..7a5be4b Binary files /dev/null and b/AnalogCircuitExp1/1-1/ANALOGCIRCUITEXP1.DSN differ diff --git a/AnalogCircuitExp1/1-1/ANALOGCIRCUITEXP1_0.DBK b/AnalogCircuitExp1/1-1/ANALOGCIRCUITEXP1_0.DBK new file mode 100644 index 0000000..1657913 Binary files /dev/null and b/AnalogCircuitExp1/1-1/ANALOGCIRCUITEXP1_0.DBK differ diff --git a/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1.sim b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1.sim new file mode 100644 index 0000000..eadeff7 --- /dev/null +++ b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1.sim @@ -0,0 +1,137 @@ +@OrCAD Simulation Server Version: 1.0 + +@Settings: 0 1 +@General: +ProfileName= "ACExpSim1" +ProfileFile= "ACExpSim1.sim" +Connectivity= "SCHEMATIC1.net" +NetlistFile= "ACExpSim1.cir" +DataFile= "ACExpSim1.dat" +OutFile= "ACExpSim1.out" +Notes= +@#$BEGINNOTES +@#$ENDNOTES +@End General +@Analysis: 0 1 ++0 0 0 0 ++0 "3ms" ++1 "" ++2 "0" ++3 "0.00001" ++4 "" ++5 "" ++6 "" +@End Analysis +@Analysis: 1 0 ++2 0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 2 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 3 0 ++0 0 0 ++0 "" ++1 "" ++2 "" +@End Analysis +@Analysis: 4 0 ++0 0 1 0 0 0 0 0 0 0 1 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +LoadFile 0 "" +SaveFile 0 "" +@End Analysis +@Analysis: 5 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 6 0 ++1 ++0 "" +@End Analysis +@Analysis: 7 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 8 0 ++0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 9 0 ++0 "" +@End Analysis +@Analysis: 10 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 11 1 ++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 +@End Analysis +@Analysis: 12 0 ++2236960 0 +@End Analysis +@Analysis: 13 1 ++0 1 1 0 +@End Analysis +@Analysis: 14 1 ++1 1 1 "*" +@End Analysis +@Analysis: 15 0 +@End Analysis +@Analysis: 16 0 ++0 "0" ++1 "0" ++2 "chkpt_default, , ," +@End Analysis +@Analysis: 17 0 ++0 "-1" ++1 "" ++2 "-1" ++3 "-1" ++4 "1" +@End Analysis diff --git a/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.1OP b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.1OP new file mode 100644 index 0000000..3b3d19c Binary files /dev/null and b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.1OP differ diff --git a/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.cir b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.cir new file mode 100644 index 0000000..3ed915b --- /dev/null +++ b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.cir @@ -0,0 +1,18 @@ +** Profile: "SCHEMATIC1-ACExpSim1" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\AnalogCircuitExp1-PSpiceFiles\SCHEMATIC1\ACExpSim1.sim ] + +** Creating circuit file "ACExpSim1.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.TRAN 0 3ms 0 0.00001 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + +.END diff --git a/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.mif b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.mif new file mode 100644 index 0000000..16f630c --- /dev/null +++ b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.mif @@ -0,0 +1 @@ + lib=D:\OrCAD\OrCAD_16.5_Lite\tools\PSpice\Library\eval.lib, offset=27170, size=1127 diff --git a/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.mrk b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.mrk new file mode 100644 index 0000000..2c24960 Binary files /dev/null and b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.mrk differ diff --git a/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.out b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.out new file mode 100644 index 0000000..4bb0965 --- /dev/null +++ b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.out @@ -0,0 +1,168 @@ + +**** 11/29/24 11:25:46 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim1" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\AnalogCircuitExp1-PSpiceFiles\SCHEMATIC1\ACExpSi + + + **** CIRCUIT DESCRIPTION + + +****************************************************************************** + + + + +** Creating circuit file "ACExpSim1.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.TRAN 0 3ms 0 0.00001 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + + +**** INCLUDING SCHEMATIC1.net **** +* source ANALOGCIRCUITEXP1 +X_U1 N00295 N00302 N00281 N00277 OUT uA741 +V_-V 0 N00277 15Vdc +V_+V N00281 0 15Vdc +R_R1 IN N00302 10k TC=0,0 +R_R2 0 N00295 9.1k TC=0,0 +R_Rf N00302 OUT 100k TC=0,0 +R_RL 0 OUT 5k TC=0,0 +V_V1 IN 0 ++SIN 0 0.9V 1kHz 0 0 0 + +**** RESUMING ACExpSim1.cir **** +.END + +**** 11/29/24 11:25:46 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim1" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\AnalogCircuitExp1-PSpiceFiles\SCHEMATIC1\ACExpSi + + + **** Diode MODEL PARAMETERS + + +****************************************************************************** + + + + + X_U1.dx + IS 800.000000E-18 + RS 1 + + +**** 11/29/24 11:25:46 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim1" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\AnalogCircuitExp1-PSpiceFiles\SCHEMATIC1\ACExpSi + + + **** BJT MODEL PARAMETERS + + +****************************************************************************** + + + + + X_U1.qx + NPN + LEVEL 1 + IS 800.000000E-18 + BF 93.75 + NF 1 + BR 1 + NR 1 + ISS 0 + RE 0 + RC 0 + CJE 0 + VJE .75 + CJC 0 + VJC .75 + MJC .33 + XCJC 1 + CJS 0 + VJS .75 + KF 0 + AF 1 + CN 2.42 + D .87 + + +**** 11/29/24 11:25:46 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim1" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\AnalogCircuitExp1-PSpiceFiles\SCHEMATIC1\ACExpSi + + + **** INITIAL TRANSIENT SOLUTION TEMPERATURE = 27.000 DEG C + + +****************************************************************************** + + + + NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE + + +( IN) 0.0000 ( OUT) 207.9E-06 (N00277) -15.0000 (N00281) 15.0000 + +(N00295)-725.5E-06 (N00302)-706.2E-06 (X_U1.6)-20.66E-09 (X_U1.7) 210.4E-06 + +(X_U1.8) 210.4E-06 (X_U1.9) 0.0000 (X_U1.10) -.6084 + +(X_U1.11) 14.9600 (X_U1.12) 14.9600 + +(X_U1.13) -.5945 (X_U1.14) -.5945 + +(X_U1.53) 14.0000 (X_U1.54) -14.0000 + +(X_U1.90) 50.72E-06 (X_U1.91) 40.0000 + +(X_U1.92) -40.0000 (X_U1.99) 0.0000 + + + + + VOLTAGE SOURCE CURRENTS + NAME CURRENT + + V_-V -1.667E-03 + V_+V -1.667E-03 + V_V1 -7.062E-08 + X_U1.vb -2.066E-13 + X_U1.vc 1.400E-11 + X_U1.ve 1.400E-11 + X_U1.vlim 5.072E-08 + X_U1.vlp -4.000E-11 + X_U1.vln -4.000E-11 + + TOTAL POWER DISSIPATION 5.00E-02 WATTS + + + + JOB CONCLUDED + +**** 11/29/24 11:25:46 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim1" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\AnalogCircuitExp1-PSpiceFiles\SCHEMATIC1\ACExpSi + + + **** JOB STATISTICS SUMMARY + + +****************************************************************************** + + + + Total job time (using Solver 1) = .05 + \ No newline at end of file diff --git a/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.prb b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.prb new file mode 100644 index 0000000..2766284 --- /dev/null +++ b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/ACExpSim1/ACExpSim1.prb @@ -0,0 +1,97 @@ +[DISPLAYS] +BEGIN DISPLAY LAST SESSION +ANALYSIS TRANSIENT_ANALYSIS +SYMBOL ALWAYS +TRACECOLORSCHEME NORMAL +BEGIN ANAPLOT 1 +ACTIVE +XBASE +BEGIN XAXIS +XAXISUSERNAME 0 (null) +RANGEFLAG AUTO +TYPE LINEAR +UNIT s +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +END XAXIS +BEGIN YAXIS 1 +YAXISSIDE LEFT +ACTIVE +RANGEFLAG AUTO +TYPE LINEAR +UNIT V +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +BEGIN TRACE V(IN) +MARKERID 11 +END TRACE V(IN) +BEGIN TRACE V(OUT) +MARKERID 12 +END TRACE V(OUT) +BEGIN LABEL +TYPE TEXT +TEXT 物联网234_张顾皓 +LABELTEXTSIZE 10 +LABELTEXTTYPE 0 +LABELTEXTFONT Arial +LABELTEXTCOLOR 65280 +LABELTEXTSCRIPT 1 +STARTX 0.0013976833976834 +STARTY 5.75757575757576 +COLOR 7 +END LABEL +BEGIN LABEL +TYPE CURSPT +STARTX 0.000749305239878595 +STARTY 8.99805641174316 +ENDX 0.000818532818532819 +ENDY 8.08080808080808 +COLOR 7 +END LABEL +BEGIN LABEL +TYPE TEXT +TEXT (749.305u,8.9981) +LABELTEXTSIZE 10 +LABELTEXTTYPE 0 +LABELTEXTFONT Arial +LABELTEXTCOLOR 65280 +LABELTEXTSCRIPT 1 +STARTX 0.000818532818532819 +STARTY 7.77777777777778 +COLOR 7 +END LABEL +BEGIN LABEL +TYPE CURSPT +STARTX 0.000249274744419381 +STARTY 0.899990677833557 +ENDX 0.000318532818532819 +ENDY 1.81818181818182 +COLOR 7 +END LABEL +BEGIN LABEL +TYPE TEXT +TEXT (249.275u,899.991m) +LABELTEXTSIZE 10 +LABELTEXTTYPE 0 +LABELTEXTFONT Arial +LABELTEXTCOLOR 65280 +LABELTEXTSCRIPT 1 +STARTX 0.000318532818532819 +STARTY 2.12121212121212 +COLOR 7 +END LABEL +END YAXIS 1 +END ANAPLOT 1 +END DISPLAY LAST SESSION diff --git a/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS new file mode 100644 index 0000000..88776b4 --- /dev/null +++ b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS @@ -0,0 +1,13 @@ +.ALIASES +X_U1 U1(+=N00295 -=N00302 V+=N00281 V-=N00277 OUT=OUT ) CN ++@ANALOGCIRCUITEXP1.SCHEMATIC1(sch_1):INS36@EVAL.uA741.Normal(chips) +V_-V -V(+=0 -=N00277 ) CN @ANALOGCIRCUITEXP1.SCHEMATIC1(sch_1):INS95@SOURCE.VDC.Normal(chips) +V_+V +V(+=N00281 -=0 ) CN @ANALOGCIRCUITEXP1.SCHEMATIC1(sch_1):INS111@SOURCE.VDC.Normal(chips) +R_R1 R1(1=IN 2=N00302 ) CN @ANALOGCIRCUITEXP1.SCHEMATIC1(sch_1):INS145@ANALOG.R.Normal(chips) +R_R2 R2(1=0 2=N00295 ) CN @ANALOGCIRCUITEXP1.SCHEMATIC1(sch_1):INS161@ANALOG.R.Normal(chips) +R_Rf Rf(1=N00302 2=OUT ) CN @ANALOGCIRCUITEXP1.SCHEMATIC1(sch_1):INS186@ANALOG.R.Normal(chips) +R_RL RL(1=0 2=OUT ) CN @ANALOGCIRCUITEXP1.SCHEMATIC1(sch_1):INS202@ANALOG.R.Normal(chips) +V_V1 V1(+=IN -=0 ) CN @ANALOGCIRCUITEXP1.SCHEMATIC1(sch_1):INS662@SOURCE.VSIN.Normal(chips) +_ _(IN=IN) +_ _(OUT=OUT) +.ENDALIASES diff --git a/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net new file mode 100644 index 0000000..f2b4cd0 --- /dev/null +++ b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net @@ -0,0 +1,10 @@ +* source ANALOGCIRCUITEXP1 +X_U1 N00295 N00302 N00281 N00277 OUT uA741 +V_-V 0 N00277 15Vdc +V_+V N00281 0 15Vdc +R_R1 IN N00302 10k TC=0,0 +R_R2 0 N00295 9.1k TC=0,0 +R_Rf N00302 OUT 100k TC=0,0 +R_RL 0 OUT 5k TC=0,0 +V_V1 IN 0 ++SIN 0 0.9V 1kHz 0 0 0 diff --git a/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp new file mode 100644 index 0000000..1798d2f --- /dev/null +++ b/AnalogCircuitExp1/1-1/AnalogCircuitExp1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp @@ -0,0 +1,74 @@ +("FILE_TYPE" "PMAP File" + ("devices" + ("VDC") + ("R") + ) + ("instances" + ("-V" + ("device_name" "VDC") + ("pspice_path" "V_-V") + ("level" "0") + ("model_params" + ("DC" + ("value" "15Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("+V" + ("device_name" "VDC") + ("pspice_path" "V_+V") + ("level" "0") + ("model_params" + ("DC" + ("value" "15Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("R1" + ("device_name" "R") + ("pspice_path" "R_R1") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "10k") + ("pspice_param" "VALUE") + ) + ) + ) + ("R2" + ("device_name" "R") + ("pspice_path" "R_R2") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "9.1k") + ("pspice_param" "VALUE") + ) + ) + ) + ("Rf" + ("device_name" "R") + ("pspice_path" "R_Rf") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "100k") + ("pspice_param" "VALUE") + ) + ) + ) + ("RL" + ("device_name" "R") + ("pspice_path" "R_RL") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "5k") + ("pspice_param" "VALUE") + ) + ) + ) + ) +) diff --git a/AnalogCircuitExp1/1-1/AnalogCircuitExp1.opj b/AnalogCircuitExp1/1-1/AnalogCircuitExp1.opj new file mode 100644 index 0000000..978d0be --- /dev/null +++ b/AnalogCircuitExp1/1-1/AnalogCircuitExp1.opj @@ -0,0 +1,83 @@ +(ExpressProject "AnalogCircuitExp1" + (ProjectVersion "19981106") + (ProjectType "Analog or A/D Mixed Mode") + (Folder "Design Resources" + (Folder "Library") + (NoModify) + (File ".\analogcircuitexp1.dsn" + (Type "Schematic Design")) + (BuildFileAddedOrDeleted "x") + (CompileFileAddedOrDeleted "x") + (PSPICE_Regenerate_Netlist_Flag "FALSE")) + (Folder "Outputs" + (File ".\analogcircuitexp1-pspicefiles\schematic1\schematic1.net" + (Type "Report"))) + (Folder "PSpice Resources" + (Folder "Simulation Profiles" + (ActiveProfile ".\analogcircuitexp1-pspicefiles\schematic1\acexpsim1.sim") + (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91} + ".\analogcircuitexp1-pspicefiles\schematic1\acexpsim1.sim" + (DisplayName "SCHEMATIC1-ACExpSim1") + (Type "PSpice Profile"))) + (Folder "Model Libraries" + (Sort User)) + (Folder "Stimulus Files" + (Sort User)) + (Folder "Include Files" + (Sort User))) + (DefaultLibraryBrowseDirectory "library\PSpice") + (PartMRUSelector + (VSIN + (FullPartName "VSIN.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\SOURCE.OLB") + (DeviceIndex "0")) + (0 + (LibraryName "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB") + (DeviceIndex "0")) + (VDC + (FullPartName "VDC.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\SOURCE.OLB") + (DeviceIndex "0")) + (R + (FullPartName "R.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\ANALOG.OLB") + (DeviceIndex "0")) + (uA741 + (FullPartName "uA741.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\EVAL.OLB") + (DeviceIndex "0"))) + (LastUsedLibraryBrowseDirectory + "D:\OrCAD\OrCAD_16.5_Lite\tools\capture\library\pspice") + (GlobalState + (FileView + (Path "Design Resources") + (Path "Design Resources" + "F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\1-1\analogcircuitexp1.dsn") + (Path "Design Resources" + "F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\1-1\analogcircuitexp1.dsn" + "SCHEMATIC1") + (Path "Outputs") + (Select "Design Resources" + "F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\1-1\analogcircuitexp1.dsn" + "SCHEMATIC1" "PAGE1")) + (HierarchyView) + (Doc + (Type "COrCapturePMDoc") + (Frame + (Placement "44 0 1 -1 -1 -8 -31 0 200 0 430")) + (Tab 0)) + (Doc + (Type "COrSchematicDoc") + (Frame + (Placement "44 0 1 -1 -1 -8 -31 130 1257 130 599") + (Scroll "-54 0") + (Zoom "100") + (Occurrence "/")) + (Path + "F:\SCHOOLWORK\ANALOGCIRCUIT\ANALOGCIRCUITEXP1\1-1\ANALOGCIRCUITEXP1.DSN") + (Schematic "SCHEMATIC1") + (Page "PAGE1")))) diff --git a/AnalogCircuitExp1/1-1/Output1.pdf b/AnalogCircuitExp1/1-1/Output1.pdf new file mode 100644 index 0000000..4002cbe Binary files /dev/null and b/AnalogCircuitExp1/1-1/Output1.pdf differ diff --git a/AnalogCircuitExp1/1-1/Output2.pdf b/AnalogCircuitExp1/1-1/Output2.pdf new file mode 100644 index 0000000..c6124e7 Binary files /dev/null and b/AnalogCircuitExp1/1-1/Output2.pdf differ diff --git a/AnalogCircuitExp1/1-1/Output3.pdf b/AnalogCircuitExp1/1-1/Output3.pdf new file mode 100644 index 0000000..6fe014a Binary files /dev/null and b/AnalogCircuitExp1/1-1/Output3.pdf differ diff --git a/AnalogCircuitExp1/1-1/Output4.pdf b/AnalogCircuitExp1/1-1/Output4.pdf new file mode 100644 index 0000000..b218b6e Binary files /dev/null and b/AnalogCircuitExp1/1-1/Output4.pdf differ diff --git a/AnalogCircuitExp1/1-1/Output5.pdf b/AnalogCircuitExp1/1-1/Output5.pdf new file mode 100644 index 0000000..dfae89c Binary files /dev/null and b/AnalogCircuitExp1/1-1/Output5.pdf differ diff --git a/AnalogCircuitExp1/1-1/Output6.pdf b/AnalogCircuitExp1/1-1/Output6.pdf new file mode 100644 index 0000000..a39e279 Binary files /dev/null and b/AnalogCircuitExp1/1-1/Output6.pdf differ diff --git a/AnalogCircuitExp1/1-1/Output7.pdf b/AnalogCircuitExp1/1-1/Output7.pdf new file mode 100644 index 0000000..afe7af3 Binary files /dev/null and b/AnalogCircuitExp1/1-1/Output7.pdf differ diff --git a/AnalogCircuitExp1/1-1/Output8.pdf b/AnalogCircuitExp1/1-1/Output8.pdf new file mode 100644 index 0000000..f1c2b7e Binary files /dev/null and b/AnalogCircuitExp1/1-1/Output8.pdf differ diff --git a/AnalogCircuitExp1/1-2/ANALOGCIRCUITEXP1(2).DSN b/AnalogCircuitExp1/1-2/ANALOGCIRCUITEXP1(2).DSN new file mode 100644 index 0000000..063da40 Binary files /dev/null and b/AnalogCircuitExp1/1-2/ANALOGCIRCUITEXP1(2).DSN differ diff --git a/AnalogCircuitExp1/1-2/ANALOGCIRCUITEXP1(2)_0.DBK b/AnalogCircuitExp1/1-2/ANALOGCIRCUITEXP1(2)_0.DBK new file mode 100644 index 0000000..d1fd157 Binary files /dev/null and b/AnalogCircuitExp1/1-2/ANALOGCIRCUITEXP1(2)_0.DBK differ diff --git a/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2).sim b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2).sim new file mode 100644 index 0000000..585bf49 --- /dev/null +++ b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2).sim @@ -0,0 +1,137 @@ +@OrCAD Simulation Server Version: 1.0 + +@Settings: 0 1 +@General: +ProfileName= "ACExpSim1(2)" +ProfileFile= "ACExpSim1(2).sim" +Connectivity= "SCHEMATIC1.net" +NetlistFile= "ACExpSim1(2).cir" +DataFile= "ACExpSim1(2).dat" +OutFile= "ACExpSim1(2).out" +Notes= +@#$BEGINNOTES +@#$ENDNOTES +@End General +@Analysis: 0 1 ++0 0 0 0 ++0 "1000ns" ++1 "" ++2 "0" ++3 "" ++4 "" ++5 "" ++6 "" +@End Analysis +@Analysis: 1 0 ++2 0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 2 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 3 0 ++0 0 0 ++0 "" ++1 "" ++2 "" +@End Analysis +@Analysis: 4 0 ++0 0 1 0 0 0 0 0 0 0 1 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +LoadFile 0 "" +SaveFile 0 "" +@End Analysis +@Analysis: 5 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 6 0 ++1 ++0 "" +@End Analysis +@Analysis: 7 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 8 0 ++0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 9 0 ++0 "" +@End Analysis +@Analysis: 10 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 11 1 ++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 +@End Analysis +@Analysis: 12 0 ++2236960 0 +@End Analysis +@Analysis: 13 1 ++0 1 1 0 +@End Analysis +@Analysis: 14 1 ++1 1 1 "*" +@End Analysis +@Analysis: 15 0 +@End Analysis +@Analysis: 16 0 ++0 "0" ++1 "0" ++2 "chkpt_default, , ," +@End Analysis +@Analysis: 17 0 ++0 "-1" ++1 "" ++2 "-1" ++3 "-1" ++4 "1" +@End Analysis diff --git a/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2)/ACExpSim1(2).1OP b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2)/ACExpSim1(2).1OP new file mode 100644 index 0000000..79fdd1a Binary files /dev/null and b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2)/ACExpSim1(2).1OP differ diff --git a/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2)/ACExpSim1(2).cir b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2)/ACExpSim1(2).cir new file mode 100644 index 0000000..85faf88 --- /dev/null +++ b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2)/ACExpSim1(2).cir @@ -0,0 +1,18 @@ +** Profile: "SCHEMATIC1-ACExpSim1(2)" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\1-2\AnalogCircuitExp1(2)-PSpiceFiles\SCHEMATIC1\ACExpSim1(2).sim ] + +** Creating circuit file "ACExpSim1(2).cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.TRAN 0 1000ns 0 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + +.END diff --git a/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2)/ACExpSim1(2).mif b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2)/ACExpSim1(2).mif new file mode 100644 index 0000000..16f630c --- /dev/null +++ b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2)/ACExpSim1(2).mif @@ -0,0 +1 @@ + lib=D:\OrCAD\OrCAD_16.5_Lite\tools\PSpice\Library\eval.lib, offset=27170, size=1127 diff --git a/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2)/ACExpSim1(2).mrk b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2)/ACExpSim1(2).mrk new file mode 100644 index 0000000..a1c2448 Binary files /dev/null and b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2)/ACExpSim1(2).mrk differ diff --git a/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2)/ACExpSim1(2).out b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2)/ACExpSim1(2).out new file mode 100644 index 0000000..e690fd7 --- /dev/null +++ b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/ACExpSim1(2)/ACExpSim1(2).out @@ -0,0 +1,169 @@ + +**** 11/29/24 11:49:30 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim1(2)" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\1-2\AnalogCircuitExp1(2)-PSpiceFiles\SCHEMATI + + + **** CIRCUIT DESCRIPTION + + +****************************************************************************** + + + + +** Creating circuit file "ACExpSim1(2).cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.TRAN 0 1000ns 0 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + + +**** INCLUDING SCHEMATIC1.net **** +* source ANALOGCIRCUITEXP1(2) +R_Rf N00912 OUT 100k TC=0,0 +R_R1 VI1 N00912 10k TC=0,0 +X_U1 N00902 N00912 N00892 N00886 OUT uA741 +R_R3 0 N00902 100k TC=0,0 +V_+V N00892 0 15Vdc +V_-V 0 N00886 15Vdc +V_V1 VI1 0 -5Vdc +V_V2 VI2 0 -15Vdc +R_R2 VI2 N00902 10k TC=0,0 + +**** RESUMING ACExpSim1(2).cir **** +.END + +**** 11/29/24 11:49:30 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim1(2)" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\1-2\AnalogCircuitExp1(2)-PSpiceFiles\SCHEMATI + + + **** Diode MODEL PARAMETERS + + +****************************************************************************** + + + + + X_U1.dx + IS 800.000000E-18 + RS 1 + + +**** 11/29/24 11:49:30 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim1(2)" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\1-2\AnalogCircuitExp1(2)-PSpiceFiles\SCHEMATI + + + **** BJT MODEL PARAMETERS + + +****************************************************************************** + + + + + X_U1.qx + NPN + LEVEL 1 + IS 800.000000E-18 + BF 93.75 + NF 1 + BR 1 + NR 1 + ISS 0 + RE 0 + RC 0 + CJE 0 + VJE .75 + CJC 0 + VJC .75 + MJC .33 + XCJC 1 + CJS 0 + VJS .75 + KF 0 + AF 1 + CN 2.42 + D .87 + + +**** 11/29/24 11:49:30 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim1(2)" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\1-2\AnalogCircuitExp1(2)-PSpiceFiles\SCHEMATI + + + **** INITIAL TRANSIENT SOLUTION TEMPERATURE = 27.000 DEG C + + +****************************************************************************** + + + + NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE + + +( OUT) -14.6120 ( VI1) -5.0000 ( VI2) -15.0000 (N00886) -15.0000 + +(N00892) 15.0000 (N00902) -13.6360 (N00912) -5.8753 (X_U1.6) 1.4472 + +(X_U1.7) -14.6180 (X_U1.8) -14.6180 (X_U1.9) 0.0000 (X_U1.10) -6.5131 + +(X_U1.11) 14.9230 (X_U1.12) 15.0000 + +(X_U1.13) -6.4862 (X_U1.14) -6.5131 + +(X_U1.53) 14.0000 (X_U1.54) -14.0000 + +(X_U1.90) -.1027 (X_U1.91) 40.0000 + +(X_U1.92) -40.0000 (X_U1.99) 0.0000 + + + + + VOLTAGE SOURCE CURRENTS + NAME CURRENT + + V_+V -1.667E-03 + V_-V -1.652E-03 + V_V1 -8.753E-05 + V_V2 1.364E-04 + X_U1.vb 1.447E-05 + X_U1.vc 2.861E-11 + X_U1.ve -1.534E-05 + X_U1.vlim -1.027E-04 + X_U1.vlp -4.010E-11 + X_U1.vln -3.990E-11 + + TOTAL POWER DISSIPATION 5.14E-02 WATTS + + + + JOB CONCLUDED + +**** 11/29/24 11:49:30 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim1(2)" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\1-2\AnalogCircuitExp1(2)-PSpiceFiles\SCHEMATI + + + **** JOB STATISTICS SUMMARY + + +****************************************************************************** + + + + Total job time (using Solver 1) = .02 + \ No newline at end of file diff --git a/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS new file mode 100644 index 0000000..4324ca3 --- /dev/null +++ b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS @@ -0,0 +1,15 @@ +.ALIASES +R_Rf Rf(1=N00912 2=OUT ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS818@ANALOG.R.Normal(chips) +R_R1 R1(1=VI1 2=N00912 ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS776@ANALOG.R.Normal(chips) +X_U1 U1(+=N00902 -=N00912 V+=N00892 V-=N00886 OUT=OUT ) CN ++@ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS698@EVAL.uA741.Normal(chips) +R_R3 R3(1=0 2=N00902 ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS798@ANALOG.R.Normal(chips) +V_+V +V(+=N00892 -=0 ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS756@SOURCE.VDC.Normal(chips) +V_-V -V(+=0 -=N00886 ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS736@SOURCE.VDC.Normal(chips) +V_V1 V1(+=VI1 -=0 ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS1192@SOURCE.VDC.Normal(chips) +V_V2 V2(+=VI2 -=0 ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS1223@SOURCE.VDC.Normal(chips) +R_R2 R2(1=VI2 2=N00902 ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS1270@ANALOG.R.Normal(chips) +_ _(OUT=OUT) +_ _(vi1=VI1) +_ _(vi2=VI2) +.ENDALIASES diff --git a/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net new file mode 100644 index 0000000..b6ea9ae --- /dev/null +++ b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net @@ -0,0 +1,10 @@ +* source ANALOGCIRCUITEXP1(2) +R_Rf N00912 OUT 100k TC=0,0 +R_R1 VI1 N00912 10k TC=0,0 +X_U1 N00902 N00912 N00892 N00886 OUT uA741 +R_R3 0 N00902 100k TC=0,0 +V_+V N00892 0 15Vdc +V_-V 0 N00886 15Vdc +V_V1 VI1 0 -5Vdc +V_V2 VI2 0 -15Vdc +R_R2 VI2 N00902 10k TC=0,0 diff --git a/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp new file mode 100644 index 0000000..204bd9e --- /dev/null +++ b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2)-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp @@ -0,0 +1,96 @@ +("FILE_TYPE" "PMAP File" + ("devices" + ("R") + ("VDC") + ) + ("instances" + ("Rf" + ("device_name" "R") + ("pspice_path" "R_Rf") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "100k") + ("pspice_param" "VALUE") + ) + ) + ) + ("R1" + ("device_name" "R") + ("pspice_path" "R_R1") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "10k") + ("pspice_param" "VALUE") + ) + ) + ) + ("R3" + ("device_name" "R") + ("pspice_path" "R_R3") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "100k") + ("pspice_param" "VALUE") + ) + ) + ) + ("+V" + ("device_name" "VDC") + ("pspice_path" "V_+V") + ("level" "0") + ("model_params" + ("DC" + ("value" "15Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("-V" + ("device_name" "VDC") + ("pspice_path" "V_-V") + ("level" "0") + ("model_params" + ("DC" + ("value" "15Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("V1" + ("device_name" "VDC") + ("pspice_path" "V_V1") + ("level" "0") + ("model_params" + ("DC" + ("value" "-5Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("V2" + ("device_name" "VDC") + ("pspice_path" "V_V2") + ("level" "0") + ("model_params" + ("DC" + ("value" "-15Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("R2" + ("device_name" "R") + ("pspice_path" "R_R2") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "10k") + ("pspice_param" "VALUE") + ) + ) + ) + ) +) diff --git a/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2).opj b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2).opj new file mode 100644 index 0000000..61a39ac --- /dev/null +++ b/AnalogCircuitExp1/1-2/AnalogCircuitExp1(2).opj @@ -0,0 +1,61 @@ +(ExpressProject "AnalogCircuitExp1(2)" + (ProjectVersion "19981106") + (ProjectType "Analog or A/D Mixed Mode") + (Folder "Design Resources" + (Folder "Library") + (NoModify) + (File ".\analogcircuitexp1(2).dsn" + (Type "Schematic Design")) + (BuildFileAddedOrDeleted "x") + (CompileFileAddedOrDeleted "x") + (PSPICE_Regenerate_Netlist_Flag "FALSE")) + (Folder "Outputs" + (File ".\analogcircuitexp1(2)-pspicefiles\schematic1\schematic1.net" + (Type "Report"))) + (Folder "PSpice Resources" + (Folder "Simulation Profiles" + (ActiveProfile + ".\analogcircuitexp1(2)-pspicefiles\schematic1\acexpsim1(2).sim") + (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91} + ".\analogcircuitexp1(2)-pspicefiles\schematic1\acexpsim1(2).sim" + (DisplayName "SCHEMATIC1-ACExpSim1(2)") + (Type "PSpice Profile"))) + (Folder "Model Libraries" + (Sort User)) + (Folder "Stimulus Files" + (Sort User)) + (Folder "Include Files" + (Sort User))) + (DefaultLibraryBrowseDirectory "library\PSpice") + (PartMRUSelector + (VDC + (FullPartName "VDC.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\SOURCE.OLB") + (DeviceIndex "0")) + (uA741 + (FullPartName "uA741.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\EVAL.OLB") + (DeviceIndex "0"))) + (GlobalState + (FileView + (Path "Design Resources") + (Path "Outputs")) + (HierarchyView) + (Doc + (Type "COrCapturePMDoc") + (Frame + (Placement "44 0 1 -1 -1 -8 -31 0 200 0 430")) + (Tab 0)) + (Doc + (Type "COrSchematicDoc") + (Frame + (Placement "44 2 3 -1 -1 -8 -31 52 1471 52 521") + (Scroll "-200 0") + (Zoom "93") + (Occurrence "/")) + (Path + "F:\SCHOOLWORK\ANALOGCIRCUIT\ANALOGCIRCUITEXP1\1-2\ANALOGCIRCUITEXP1(2).DSN") + (Schematic "SCHEMATIC1") + (Page "PAGE1")))) diff --git a/AnalogCircuitExp1/1-2/Output1.pdf b/AnalogCircuitExp1/1-2/Output1.pdf new file mode 100644 index 0000000..ca02666 Binary files /dev/null and b/AnalogCircuitExp1/1-2/Output1.pdf differ diff --git a/AnalogCircuitExp1/1-2/Output2.pdf b/AnalogCircuitExp1/1-2/Output2.pdf new file mode 100644 index 0000000..6f7a5ac Binary files /dev/null and b/AnalogCircuitExp1/1-2/Output2.pdf differ diff --git a/AnalogCircuitExp1/1-2/Output3.pdf b/AnalogCircuitExp1/1-2/Output3.pdf new file mode 100644 index 0000000..6c04aef Binary files /dev/null and b/AnalogCircuitExp1/1-2/Output3.pdf differ diff --git a/AnalogCircuitExp1/1-2/Output4.pdf b/AnalogCircuitExp1/1-2/Output4.pdf new file mode 100644 index 0000000..6361b76 Binary files /dev/null and b/AnalogCircuitExp1/1-2/Output4.pdf differ diff --git a/AnalogCircuitExp1/1-2/Output5.pdf b/AnalogCircuitExp1/1-2/Output5.pdf new file mode 100644 index 0000000..134176f Binary files /dev/null and b/AnalogCircuitExp1/1-2/Output5.pdf differ diff --git a/AnalogCircuitExp1/1-2/Output6.pdf b/AnalogCircuitExp1/1-2/Output6.pdf new file mode 100644 index 0000000..c6b2fe0 Binary files /dev/null and b/AnalogCircuitExp1/1-2/Output6.pdf differ diff --git a/AnalogCircuitExp2/ACExpSim2.out.pdf b/AnalogCircuitExp2/ACExpSim2.out.pdf new file mode 100644 index 0000000..0556d89 Binary files /dev/null and b/AnalogCircuitExp2/ACExpSim2.out.pdf differ diff --git a/AnalogCircuitExp2/ANALOGCIRCUITEXP2.DSN b/AnalogCircuitExp2/ANALOGCIRCUITEXP2.DSN new file mode 100644 index 0000000..1c20491 Binary files /dev/null and b/AnalogCircuitExp2/ANALOGCIRCUITEXP2.DSN differ diff --git a/AnalogCircuitExp2/ANALOGCIRCUITEXP2.DSNlck b/AnalogCircuitExp2/ANALOGCIRCUITEXP2.DSNlck new file mode 100644 index 0000000..1d58a19 Binary files /dev/null and b/AnalogCircuitExp2/ANALOGCIRCUITEXP2.DSNlck differ diff --git a/AnalogCircuitExp2/ANALOGCIRCUITEXP2_0.DBK b/AnalogCircuitExp2/ANALOGCIRCUITEXP2_0.DBK new file mode 100644 index 0000000..74f2636 Binary files /dev/null and b/AnalogCircuitExp2/ANALOGCIRCUITEXP2_0.DBK differ diff --git a/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2.sim b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2.sim new file mode 100644 index 0000000..0e6ef6b --- /dev/null +++ b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2.sim @@ -0,0 +1,137 @@ +@OrCAD Simulation Server Version: 1.0 + +@Settings: 0 1 +@General: +ProfileName= "ACExpSim2" +ProfileFile= "ACExpSim2.sim" +Connectivity= "SCHEMATIC1.net" +NetlistFile= "ACExpSim2.cir" +DataFile= "ACExpSim2.dat" +OutFile= "ACExpSim2.out" +Notes= +@#$BEGINNOTES +@#$ENDNOTES +@End General +@Analysis: 0 1 ++0 0 0 0 ++0 "3ms" ++1 "" ++2 "0" ++3 "0.01m" ++4 "" ++5 "" ++6 "" +@End Analysis +@Analysis: 1 0 ++2 0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 2 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 3 0 ++1 0 0 ++0 "" ++1 "" ++2 "" +@End Analysis +@Analysis: 4 0 ++0 0 1 0 0 0 0 0 0 0 1 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +LoadFile 0 "" +SaveFile 0 "" +@End Analysis +@Analysis: 5 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 6 0 ++1 ++0 "" +@End Analysis +@Analysis: 7 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 8 0 ++0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 9 0 ++0 "" +@End Analysis +@Analysis: 10 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 11 1 ++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 +@End Analysis +@Analysis: 12 0 ++2236960 0 +@End Analysis +@Analysis: 13 1 ++0 1 1 0 +@End Analysis +@Analysis: 14 1 ++1 1 1 "*" +@End Analysis +@Analysis: 15 0 +@End Analysis +@Analysis: 16 0 ++0 "0" ++1 "0" ++2 "chkpt_default, , ," +@End Analysis +@Analysis: 17 0 ++0 "-1" ++1 "" ++2 "-1" ++3 "-1" ++4 "1" +@End Analysis diff --git a/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.1OP b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.1OP new file mode 100644 index 0000000..b0af487 Binary files /dev/null and b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.1OP differ diff --git a/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.cir b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.cir new file mode 100644 index 0000000..592a1d2 --- /dev/null +++ b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.cir @@ -0,0 +1,19 @@ +** Profile: "SCHEMATIC1-ACExpSim2" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp2\AnalogCircuitExp2-PSpiceFiles\SCHEMATIC1\ACExpSim2.sim ] + +** Creating circuit file "ACExpSim2.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +.LIB "../../../analogcircuitexp2-pspicefiles/analogcircuitexp2.lib" +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.TRAN 0 3ms 0 0.01m +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + +.END diff --git a/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.mif b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.mif new file mode 100644 index 0000000..404f645 --- /dev/null +++ b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.mif @@ -0,0 +1 @@ + lib=F:\Schoolwork\AnalogCircuit\AnalogCircuitExp2\analogcircuitexp2-pspicefiles\analogcircuitexp2.lib, offset=43, size=305 diff --git a/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.mrk b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.mrk new file mode 100644 index 0000000..13818b6 Binary files /dev/null and b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.mrk differ diff --git a/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.out b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.out new file mode 100644 index 0000000..d432d12 --- /dev/null +++ b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.out @@ -0,0 +1,148 @@ + +**** 12/11/24 11:54:31 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim2" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp2\AnalogCircuitExp2-PSpiceFiles\SCHEMATIC1\ACExpSi + + + **** CIRCUIT DESCRIPTION + + +****************************************************************************** + + + + +** Creating circuit file "ACExpSim2.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +.LIB "../../../analogcircuitexp2-pspicefiles/analogcircuitexp2.lib" +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.TRAN 0 3ms 0 0.01m +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + + +**** INCLUDING SCHEMATIC1.net **** +* source ANALOGCIRCUITEXP2 +V_Vs VS 0 ++SIN 0 10.5mV 1kHz 0 0 0 +R_Rs VS VI 1k TC=0,0 +C_C1 VI N00381 10uF TC=0,0 +R_Rb2 0 N00381 30k TC=0,0 +R_Rb1 N00381 N00522 73k TC=0,0 +Q_T N00410 N00381 N00414 Q2N3904 +R_Rc N00410 N00522 2k TC=0,0 +R_Re 0 N00414 1k TC=0,0 +C_Ce 0 N00414 47uF TC=0,0 +C_C2 N00410 VO 10uF TC=0,0 +V_Vcc N00522 0 12V +R_RL 0 VO 2k TC=0,0 + +**** RESUMING ACExpSim2.cir **** +.END + +**** 12/11/24 11:54:31 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim2" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp2\AnalogCircuitExp2-PSpiceFiles\SCHEMATIC1\ACExpSi + + + **** BJT MODEL PARAMETERS + + +****************************************************************************** + + + + + Q2N3904 + NPN + LEVEL 1 + IS 6.734000E-15 + BF 70 + NF 1 + VAF 74.03 + IKF .06678 + ISE 6.734000E-15 + NE 1.259 + BR .7371 + NR 1 + ISS 0 + RB 10 + RE 0 + RC 1 + CJE 4.493000E-12 + VJE .75 + MJE .2593 + CJC 3.638000E-12 + VJC .75 + MJC .3085 + XCJC 1 + CJS 0 + VJS .75 + TF 301.200000E-12 + XTF 2 + VTF 4 + ITF .4 + TR 239.500000E-09 + XTB 1.5 + KF 0 + AF 1 + CN 2.42 + D .87 + + +**** 12/11/24 11:54:31 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim2" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp2\AnalogCircuitExp2-PSpiceFiles\SCHEMATIC1\ACExpSi + + + **** INITIAL TRANSIENT SOLUTION TEMPERATURE = 27.000 DEG C + + +****************************************************************************** + + + + NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE + + +( VI) 0.0000 ( VO) 0.0000 ( VS) 0.0000 (N00381) 2.7287 + +(N00410) 7.9801 (N00414) 2.0460 (N00522) 12.0000 + + + + + VOLTAGE SOURCE CURRENTS + NAME CURRENT + + V_Vs 0.000E+00 + V_Vcc -2.137E-03 + + TOTAL POWER DISSIPATION 2.56E-02 WATTS + + + + JOB CONCLUDED + +**** 12/11/24 11:54:31 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim2" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp2\AnalogCircuitExp2-PSpiceFiles\SCHEMATIC1\ACExpSi + + + **** JOB STATISTICS SUMMARY + + +****************************************************************************** + + + + Total job time (using Solver 1) = .02 + \ No newline at end of file diff --git a/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.out.1 b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.out.1 new file mode 100644 index 0000000..bd9ef98 --- /dev/null +++ b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.out.1 @@ -0,0 +1,192 @@ + +**** 12/11/24 11:31:39 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim2" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp2\AnalogCircuitExp2-PSpiceFiles\SCHEMATIC1\ACExpSi + + + **** CIRCUIT DESCRIPTION + + +****************************************************************************** + + + + +** Creating circuit file "ACExpSim2.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +.LIB "../../../analogcircuitexp2-pspicefiles/analogcircuitexp2.lib" +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.OP +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + + +**** INCLUDING SCHEMATIC1.net **** +* source ANALOGCIRCUITEXP2 +V_Vs VS 0 ++SIN 0 5mV 1kHz 0 0 0 +R_Rs VS VI 1k TC=0,0 +C_C1 VI N00381 10uF TC=0,0 +R_Rb2 0 N00381 30k TC=0,0 +R_Rb1 N00381 N00522 57k TC=0,0 +Q_T N00410 N00381 N00414 Q2N3904 +R_Rc N00410 N00522 2k TC=0,0 +R_Re 0 N00414 1k TC=0,0 +C_Ce 0 N00414 47uF TC=0,0 +C_C2 N00410 VO 10uF TC=0,0 +V_Vcc N00522 0 12V +R_RL 0 VO 2k TC=0,0 + +**** RESUMING ACExpSim2.cir **** +.END + +INFO(ORPSIM-15423): Unable to find index file analogcircuitexp2.ind for library file analogcircuitexp2.lib. + +INFO(ORPSIM-15422): Making new index file analogcircuitexp2.ind for library file analogcircuitexp2.lib. + +Index has 1 entries from 1 file(s). + +**** 12/11/24 11:31:39 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim2" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp2\AnalogCircuitExp2-PSpiceFiles\SCHEMATIC1\ACExpSi + + + **** BJT MODEL PARAMETERS + + +****************************************************************************** + + + + + Q2N3904 + NPN + LEVEL 1 + IS 6.734000E-15 + BF 70 + NF 1 + VAF 74.03 + IKF .06678 + ISE 6.734000E-15 + NE 1.259 + BR .7371 + NR 1 + ISS 0 + RB 10 + RE 0 + RC 1 + CJE 4.493000E-12 + VJE .75 + MJE .2593 + CJC 3.638000E-12 + VJC .75 + MJC .3085 + XCJC 1 + CJS 0 + VJS .75 + TF 301.200000E-12 + XTF 2 + VTF 4 + ITF .4 + TR 239.500000E-09 + XTB 1.5 + KF 0 + AF 1 + CN 2.42 + D .87 + + +**** 12/11/24 11:31:39 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim2" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp2\AnalogCircuitExp2-PSpiceFiles\SCHEMATIC1\ACExpSi + + + **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C + + +****************************************************************************** + + + + NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE + + +( VI) 0.0000 ( VO) 0.0000 ( VS) 0.0000 (N00381) 3.2412 + +(N00410) 6.9872 (N00414) 2.5520 (N00522) 12.0000 + + + + + VOLTAGE SOURCE CURRENTS + NAME CURRENT + + V_Vs 0.000E+00 + V_Vcc -2.660E-03 + + TOTAL POWER DISSIPATION 3.19E-02 WATTS + + +**** 12/11/24 11:31:39 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim2" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp2\AnalogCircuitExp2-PSpiceFiles\SCHEMATIC1\ACExpSi + + + **** OPERATING POINT INFORMATION TEMPERATURE = 27.000 DEG C + + +****************************************************************************** + + + + + + +**** BIPOLAR JUNCTION TRANSISTORS + + +NAME Q_T +MODEL Q2N3904 +IB 4.56E-05 +IC 2.51E-03 +VBE 6.89E-01 +VBC -3.75E+00 +VCE 4.44E+00 +BETADC 5.49E+01 +GM 9.36E-02 +RPI 5.95E+02 +RX 1.00E+01 +RO 3.10E+04 +CBE 3.48E-11 +CBC 2.09E-12 +CJS 0.00E+00 +BETAAC 5.57E+01 +CBX/CBX2 0.00E+00 +FT/FT2 4.04E+08 + + + + JOB CONCLUDED + +**** 12/11/24 11:31:39 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ACExpSim2" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp2\AnalogCircuitExp2-PSpiceFiles\SCHEMATIC1\ACExpSi + + + **** JOB STATISTICS SUMMARY + + +****************************************************************************** + + + + Total job time (using Solver 1) = .11 + \ No newline at end of file diff --git a/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.prb b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.prb new file mode 100644 index 0000000..705d414 --- /dev/null +++ b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/ACExpSim2/ACExpSim2.prb @@ -0,0 +1,153 @@ +[DISPLAYS] +BEGIN DISPLAY LAST SESSION +ANALYSIS TRANSIENT_ANALYSIS +SYMBOL ALWAYS +TRACECOLORSCHEME NORMAL +BEGIN ANAPLOT 1 +XBASE +BEGIN XAXIS +XAXISUSERNAME 0 (null) +RANGEFLAG AUTO +TYPE LINEAR +UNIT s +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +END XAXIS +BEGIN YAXIS 1 +YAXISSIDE LEFT +ACTIVE +RANGEFLAG AUTO +TYPE LINEAR +UNIT V +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +BEGIN TRACE V(VS) +MARKERID 5 +TRACEADDEXT +END TRACE V(VS) +BEGIN TRACE V(VI) +MARKERID 6 +TRACEADDEXT +END TRACE V(VI) +BEGIN LABEL +TYPE CURSPT +STARTX 0.000272816454526037 +STARTY 0.00499793095514178 +ENDX 0.000342412451361867 +ENDY 0.0068013468013468 +COLOR 7 +END LABEL +BEGIN LABEL +TYPE TEXT +TEXT (272.817u,4.9979m) +LABELTEXTSIZE 10 +LABELTEXTTYPE 0 +LABELTEXTFONT Arial +LABELTEXTCOLOR 65280 +LABELTEXTSCRIPT 1 +STARTX 0.000342412451361867 +STARTY 0.0074074074074074 +COLOR 7 +END LABEL +BEGIN LABEL +TYPE CURSPT +STARTX 0.000252815225394443 +STARTY 0.0104983570054173 +ENDX 0.00032295719844358 +ENDY 0.0123232323232323 +COLOR 7 +END LABEL +BEGIN LABEL +TYPE TEXT +TEXT (252.815u,10.498m) +LABELTEXTSIZE 10 +LABELTEXTTYPE 0 +LABELTEXTFONT Arial +LABELTEXTCOLOR 65280 +LABELTEXTSCRIPT 1 +STARTX 0.00032295719844358 +STARTY 0.0129292929292929 +COLOR 7 +END LABEL +END YAXIS 1 +END ANAPLOT 1 +BEGIN ANAPLOT 2 +ACTIVE +BEGIN XAXIS +XAXISUSERNAME 0 (null) +RANGEFLAG AUTO +TYPE LINEAR +UNIT s +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +END XAXIS +BEGIN YAXIS 1 +YAXISSIDE LEFT +ACTIVE +RANGEFLAG AUTO +TYPE LINEAR +UNIT V +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +BEGIN TRACE V(Vo) +MARKERID 7 +END TRACE V(Vo) +BEGIN LABEL +TYPE TEXT +TEXT 物联网234 张顾皓 Ic=2mA时的Vi、Vs、Vo波形 +LABELTEXTSIZE 10 +LABELTEXTTYPE 0 +LABELTEXTFONT Arial +LABELTEXTCOLOR 65280 +LABELTEXTSCRIPT 1 +STARTX 0.002099609375 +STARTY -0.155395683453237 +COLOR 7 +END LABEL +BEGIN LABEL +TYPE CURSPT +STARTX 0.000732844520825893 +STARTY 0.334606140851974 +ENDX 0.000802734375 +ENDY 0.256115107913669 +COLOR 7 +END LABEL +BEGIN LABEL +TYPE TEXT +TEXT (732.845u,334.606m) +LABELTEXTSIZE 10 +LABELTEXTTYPE 0 +LABELTEXTFONT Arial +LABELTEXTCOLOR 65280 +LABELTEXTSCRIPT 1 +STARTX 0.000802734375 +STARTY 0.230215827338129 +COLOR 7 +END LABEL +END YAXIS 1 +END ANAPLOT 2 +END DISPLAY LAST SESSION diff --git a/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS new file mode 100644 index 0000000..7227e3f --- /dev/null +++ b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS @@ -0,0 +1,17 @@ +.ALIASES +V_Vs Vs(+=VS -=0 ) CN @ANALOGCIRCUITEXP2.SCHEMATIC1(sch_1):INS46@SOURCE.VSIN.Normal(chips) +R_Rs Rs(1=VS 2=VI ) CN @ANALOGCIRCUITEXP2.SCHEMATIC1(sch_1):INS83@ANALOG.R.Normal(chips) +C_C1 C1(1=VI 2=N00381 ) CN @ANALOGCIRCUITEXP2.SCHEMATIC1(sch_1):INS108@ANALOG.C.Normal(chips) +R_Rb2 Rb2(1=0 2=N00381 ) CN @ANALOGCIRCUITEXP2.SCHEMATIC1(sch_1):INS133@ANALOG.R.Normal(chips) +R_Rb1 Rb1(1=N00381 2=N00522 ) CN @ANALOGCIRCUITEXP2.SCHEMATIC1(sch_1):INS159@ANALOG.R.Normal(chips) +Q_T T(c=N00410 b=N00381 e=N00414 ) CN @ANALOGCIRCUITEXP2.SCHEMATIC1(sch_1):INS197@EVAL.Q2N3904.Normal(chips) +R_Rc Rc(1=N00410 2=N00522 ) CN @ANALOGCIRCUITEXP2.SCHEMATIC1(sch_1):INS225@ANALOG.R.Normal(chips) +R_Re Re(1=0 2=N00414 ) CN @ANALOGCIRCUITEXP2.SCHEMATIC1(sch_1):INS251@ANALOG.R.Normal(chips) +C_Ce Ce(1=0 2=N00414 ) CN @ANALOGCIRCUITEXP2.SCHEMATIC1(sch_1):INS276@ANALOG.C.Normal(chips) +C_C2 C2(1=N00410 2=VO ) CN @ANALOGCIRCUITEXP2.SCHEMATIC1(sch_1):INS301@ANALOG.C.Normal(chips) +V_Vcc Vcc(+=N00522 -=0 ) CN @ANALOGCIRCUITEXP2.SCHEMATIC1(sch_1):INS326@SOURCE.VDC.Normal(chips) +R_RL RL(1=0 2=VO ) CN @ANALOGCIRCUITEXP2.SCHEMATIC1(sch_1):INS352@ANALOG.R.Normal(chips) +_ _(Vi=VI) +_ _(Vo=VO) +_ _(Vs=VS) +.ENDALIASES diff --git a/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net new file mode 100644 index 0000000..629e0d7 --- /dev/null +++ b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net @@ -0,0 +1,14 @@ +* source ANALOGCIRCUITEXP2 +V_Vs VS 0 ++SIN 0 10.5mV 1kHz 0 0 0 +R_Rs VS VI 1k TC=0,0 +C_C1 VI N00381 10uF TC=0,0 +R_Rb2 0 N00381 30k TC=0,0 +R_Rb1 N00381 N00522 73k TC=0,0 +Q_T N00410 N00381 N00414 Q2N3904 +R_Rc N00410 N00522 2k TC=0,0 +R_Re 0 N00414 1k TC=0,0 +C_Ce 0 N00414 47uF TC=0,0 +C_C2 N00410 VO 10uF TC=0,0 +V_Vcc N00522 0 12V +R_RL 0 VO 2k TC=0,0 diff --git a/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp new file mode 100644 index 0000000..b704e0a --- /dev/null +++ b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp @@ -0,0 +1,119 @@ +("FILE_TYPE" "PMAP File" + ("devices" + ("R") + ("C") + ("VDC") + ) + ("instances" + ("Rs" + ("device_name" "R") + ("pspice_path" "R_Rs") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "1k") + ("pspice_param" "VALUE") + ) + ) + ) + ("C1" + ("device_name" "C") + ("pspice_path" "C_C1") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "10uF") + ("pspice_param" "VALUE") + ) + ) + ) + ("Rb2" + ("device_name" "R") + ("pspice_path" "R_Rb2") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "30k") + ("pspice_param" "VALUE") + ) + ) + ) + ("Rb1" + ("device_name" "R") + ("pspice_path" "R_Rb1") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "73k") + ("pspice_param" "VALUE") + ) + ) + ) + ("Rc" + ("device_name" "R") + ("pspice_path" "R_Rc") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "2k") + ("pspice_param" "VALUE") + ) + ) + ) + ("Re" + ("device_name" "R") + ("pspice_path" "R_Re") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "1k") + ("pspice_param" "VALUE") + ) + ) + ) + ("Ce" + ("device_name" "C") + ("pspice_path" "C_Ce") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "47uF") + ("pspice_param" "VALUE") + ) + ) + ) + ("C2" + ("device_name" "C") + ("pspice_path" "C_C2") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "10uF") + ("pspice_param" "VALUE") + ) + ) + ) + ("Vcc" + ("device_name" "VDC") + ("pspice_path" "V_Vcc") + ("level" "0") + ("model_params" + ("DC" + ("value" "12V") + ("pspice_param" "DC") + ) + ) + ) + ("RL" + ("device_name" "R") + ("pspice_path" "R_RL") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "2k") + ("pspice_param" "VALUE") + ) + ) + ) + ) +) diff --git a/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/analogcircuitexp2.ind b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/analogcircuitexp2.ind new file mode 100644 index 0000000..2454ba2 Binary files /dev/null and b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/analogcircuitexp2.ind differ diff --git a/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/analogcircuitexp2.lib b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/analogcircuitexp2.lib new file mode 100644 index 0000000..ceb3252 --- /dev/null +++ b/AnalogCircuitExp2/AnalogCircuitExp2-PSpiceFiles/analogcircuitexp2.lib @@ -0,0 +1,10 @@ +* PSpice Model Editor - Version 16.5.0 + +*$ +.model Q2N3904 NPN(Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=70 Ne=1.259 ++ Ise=6.734f Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 Rc=1 ++ Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75 ++ Tr=239.5n Tf=301.2p Itf=.4 Vtf=4 Xtf=2 Rb=10) +* National pid=23 case=TO92 +* 88-09-08 bam creation +*$ diff --git a/AnalogCircuitExp2/AnalogCircuitExp2.opj b/AnalogCircuitExp2/AnalogCircuitExp2.opj new file mode 100644 index 0000000..84e986c --- /dev/null +++ b/AnalogCircuitExp2/AnalogCircuitExp2.opj @@ -0,0 +1,44 @@ +(ExpressProject "AnalogCircuitExp2" + (ProjectVersion "19981106") + (ProjectType "Analog or A/D Mixed Mode") + (Folder "Design Resources" + (Folder "Library") + (NoModify) + (File ".\analogcircuitexp2.dsn" + (Type "Schematic Design")) + (BuildFileAddedOrDeleted "x") + (CompileFileAddedOrDeleted "x")) + (Folder "Outputs") + (Folder "PSpice Resources" + (Folder "Simulation Profiles") + (Folder "Stimulus Files" + (Sort User)) + (Folder "Include Files" + (Sort User)) + (Folder "Model Libraries" + (File ".\analogcircuitexp2-pspicefiles\analogcircuitexp2.lib" + (DisplayName ".\analogcircuitexp2-pspicefiles\analogcircuitexp2.lib") + (Type "PSpiceLibrary")) + (Sort User))) + (DefaultLibraryBrowseDirectory "library\PSpice") + (GlobalState + (FileView + (Path "Design Resources")) + (HierarchyView) + (Doc + (Type "COrCapturePMDoc") + (Frame + (Placement "44 0 1 -1 -1 -8 -31 0 200 0 430")) + (Tab 0)) + (Doc + (Type "COrSchematicDoc") + (Frame + (Placement "44 2 3 -1 -1 -8 -31 52 1471 52 521") + (Scroll "-312 0") + (Zoom "100") + (Occurrence "/")) + (Path + "F:\SCHOOLWORK\ANALOGCIRCUIT\ANALOGCIRCUITEXP2\ANALOGCIRCUITEXP2.DSN") + (Schematic "SCHEMATIC1") + (Page "PAGE1"))) + (PartMRUSelector)) diff --git a/AnalogCircuitExp2/Output1-1.pdf b/AnalogCircuitExp2/Output1-1.pdf new file mode 100644 index 0000000..f765353 Binary files /dev/null and b/AnalogCircuitExp2/Output1-1.pdf differ diff --git a/AnalogCircuitExp2/Output1-2.pdf b/AnalogCircuitExp2/Output1-2.pdf new file mode 100644 index 0000000..ed50b50 Binary files /dev/null and b/AnalogCircuitExp2/Output1-2.pdf differ diff --git a/AnalogCircuitExp2/Output1-3.pdf b/AnalogCircuitExp2/Output1-3.pdf new file mode 100644 index 0000000..0537953 Binary files /dev/null and b/AnalogCircuitExp2/Output1-3.pdf differ diff --git a/AnalogCircuitExp2/Output1-4.pdf b/AnalogCircuitExp2/Output1-4.pdf new file mode 100644 index 0000000..bb586d8 Binary files /dev/null and b/AnalogCircuitExp2/Output1-4.pdf differ diff --git a/AnalogCircuitExp2/Output2-1.pdf b/AnalogCircuitExp2/Output2-1.pdf new file mode 100644 index 0000000..b74257c Binary files /dev/null and b/AnalogCircuitExp2/Output2-1.pdf differ diff --git a/AnalogCircuitExp2/Output2-2.pdf b/AnalogCircuitExp2/Output2-2.pdf new file mode 100644 index 0000000..cd58bf6 Binary files /dev/null and b/AnalogCircuitExp2/Output2-2.pdf differ diff --git a/AnalogCircuitExp2/SCHEMATIC1 _ PAGE1.pdf b/AnalogCircuitExp2/SCHEMATIC1 _ PAGE1.pdf new file mode 100644 index 0000000..299670f Binary files /dev/null and b/AnalogCircuitExp2/SCHEMATIC1 _ PAGE1.pdf differ diff --git a/CircuitExp1/1-1/CIRCUITEXP1-1.DSN b/CircuitExp1/1-1/CIRCUITEXP1-1.DSN new file mode 100644 index 0000000..97f368c Binary files /dev/null and b/CircuitExp1/1-1/CIRCUITEXP1-1.DSN differ diff --git a/CircuitExp1/1-1/CIRCUITEXP1-1_0.DBK b/CircuitExp1/1-1/CIRCUITEXP1-1_0.DBK new file mode 100644 index 0000000..39adee6 Binary files /dev/null and b/CircuitExp1/1-1/CIRCUITEXP1-1_0.DBK differ diff --git a/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/ExpSim1-1.sim b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/ExpSim1-1.sim new file mode 100644 index 0000000..d5072ea --- /dev/null +++ b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/ExpSim1-1.sim @@ -0,0 +1,137 @@ +@OrCAD Simulation Server Version: 1.0 + +@Settings: 1 1 +@General: +ProfileName= "ExpSim1-1" +ProfileFile= "ExpSim1-1.sim" +Connectivity= "SCHEMATIC1.net" +NetlistFile= "ExpSim1-1.cir" +DataFile= "ExpSim1-1.dat" +OutFile= "ExpSim1-1.out" +Notes= +@#$BEGINNOTES +@#$ENDNOTES +@End General +@Analysis: 0 0 ++0 0 0 0 ++0 "1000ns" ++1 "" ++2 "0" ++3 "" ++4 "" ++5 "" ++6 "" +@End Analysis +@Analysis: 1 0 ++2 0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 2 1 ++0 0 ++0 "V1" ++1 "" ++2 "" ++3 "" ++4 "0" ++5 "20" ++6 "2" ++7 "" +@End Analysis +@Analysis: 3 0 ++0 0 0 ++0 "" ++1 "" ++2 "" +@End Analysis +@Analysis: 4 0 ++0 0 1 0 0 0 1 0 0 0 1 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +LoadFile 0 "" +SaveFile 0 "" +@End Analysis +@Analysis: 5 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 6 0 ++1 ++0 "" +@End Analysis +@Analysis: 7 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 8 0 ++0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 9 0 ++0 "" +@End Analysis +@Analysis: 10 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 11 1 ++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 +@End Analysis +@Analysis: 12 0 ++2236960 0 +@End Analysis +@Analysis: 13 1 ++0 1 1 0 +@End Analysis +@Analysis: 14 1 ++1 1 1 "*" +@End Analysis +@Analysis: 15 0 +@End Analysis +@Analysis: 16 0 ++0 "0" ++1 "0" ++2 "chkpt_default, , ," +@End Analysis +@Analysis: 17 0 ++0 "-1" ++1 "" ++2 "-1" ++3 "-1" ++4 "1" +@End Analysis diff --git a/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/ExpSim1-1/ExpSim1-1.cir b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/ExpSim1-1/ExpSim1-1.cir new file mode 100644 index 0000000..461fbee --- /dev/null +++ b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/ExpSim1-1/ExpSim1-1.cir @@ -0,0 +1,18 @@ +** Profile: "SCHEMATIC1-ExpSim1-1" [ F:\Projects\AnalogCircuit\CircuitExp1\1-1\CircuitExp1-1-PSpiceFiles\SCHEMATIC1\ExpSim1-1.sim ] + +** Creating circuit file "ExpSim1-1.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.DC LIN V_V1 0 20 2 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + +.END diff --git a/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/ExpSim1-1/ExpSim1-1.mrk b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/ExpSim1-1/ExpSim1-1.mrk new file mode 100644 index 0000000..31cac55 Binary files /dev/null and b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/ExpSim1-1/ExpSim1-1.mrk differ diff --git a/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/ExpSim1-1/ExpSim1-1.out b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/ExpSim1-1/ExpSim1-1.out new file mode 100644 index 0000000..cca2688 --- /dev/null +++ b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/ExpSim1-1/ExpSim1-1.out @@ -0,0 +1,56 @@ + +**** 09/13/24 11:42:54 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim1-1" [ F:\Projects\AnalogCircuit\CircuitExp1\1-1\CircuitExp1-1-PSpiceFiles\SCHEMATIC1\ExpSim1-1.sim ] + + + **** CIRCUIT DESCRIPTION + + +****************************************************************************** + + + + +** Creating circuit file "ExpSim1-1.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.DC LIN V_V1 0 20 2 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + + +**** INCLUDING SCHEMATIC1.net **** +* source CIRCUITEXP1-1 +V_V1 N1 0 10Vdc +R_R2 N1 N2 3k TC=0,0 +R_R1 0 N2 1k TC=0,0 + +**** RESUMING ExpSim1-1.cir **** +.END + + + JOB CONCLUDED + +**** 09/13/24 11:42:54 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim1-1" [ F:\Projects\AnalogCircuit\CircuitExp1\1-1\CircuitExp1-1-PSpiceFiles\SCHEMATIC1\ExpSim1-1.sim ] + + + **** JOB STATISTICS SUMMARY + + +****************************************************************************** + + + + Total job time (using Solver 1) = 0.00 + \ No newline at end of file diff --git a/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/ExpSim1-1/ExpSim1-1.prb b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/ExpSim1-1/ExpSim1-1.prb new file mode 100644 index 0000000..6311e9b --- /dev/null +++ b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/ExpSim1-1/ExpSim1-1.prb @@ -0,0 +1,90 @@ +[DISPLAYS] +BEGIN DISPLAY LAST SESSION +ANALYSIS DC_SWEEP +SYMBOL ALWAYS +TRACECOLORSCHEME NORMAL +BEGIN ANAPLOT 1 +ACTIVE +XBASE +BEGIN XAXIS +XAXISUSERNAME 0 (null) +RANGEFLAG AUTO +TYPE LINEAR +UNIT V +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +END XAXIS +BEGIN YAXIS 1 +YAXISSIDE LEFT +ACTIVE +RANGEFLAG AUTO +TYPE LINEAR +UNIT V +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +BEGIN TRACE V(N1)- V(N2) +MARKERID 7 +INSTANCE 1 TRACECOLOR 3 +INSTANCE 1 TRACEWIDTH 2 +INSTANCE 1 TRACESYMBOL 0 +INSTANCE 1 TRACEUSERMODIFIED +END TRACE V(N1)- V(N2) +BEGIN TRACE V(N2) +MARKERID 8 +INSTANCE 1 TRACECOLOR 4 +INSTANCE 1 TRACEPATTERN DASH +INSTANCE 1 TRACEWIDTH 2 +INSTANCE 1 TRACESYMBOL 1 +INSTANCE 1 TRACEUSERMODIFIED +END TRACE V(N2) +BEGIN LABEL +TYPE TEXT +TEXT 鐗╄仈缃234_2330110900_寮犻【鐨 +LABELTEXTSIZE 12 +LABELTEXTTYPE 0 +LABELTEXTFONT Arial +LABELTEXTCOLOR 0 +LABELTEXTSCRIPT 0 +STARTX 4.5 +STARTY 11.6161616161616 +COLOR 7 +END LABEL +BEGIN LABEL +TYPE TEXT +TEXT U(R2) +LABELTEXTSIZE 12 +LABELTEXTTYPE 0 +LABELTEXTFONT Arial +LABELTEXTCOLOR 0 +LABELTEXTSCRIPT 0 +STARTX 8.20512820512821 +STARTY 7.12121212121212 +COLOR 7 +END LABEL +BEGIN LABEL +TYPE TEXT +TEXT U(R1) +LABELTEXTSIZE 12 +LABELTEXTTYPE 0 +LABELTEXTFONT Arial +LABELTEXTCOLOR 0 +LABELTEXTSCRIPT 0 +STARTX 11.8589743589744 +STARTY 3.78787878787879 +COLOR 7 +END LABEL +END YAXIS 1 +END ANAPLOT 1 +END DISPLAY LAST SESSION diff --git a/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS new file mode 100644 index 0000000..0b03f49 --- /dev/null +++ b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS @@ -0,0 +1,7 @@ +.ALIASES +V_V1 V1(+=N1 -=0 ) CN @CIRCUITEXP1-1.SCHEMATIC1(sch_1):INS35@SOURCE.VDC.Normal(chips) +R_R2 R2(1=N1 2=N2 ) CN @CIRCUITEXP1-1.SCHEMATIC1(sch_1):INS60@ANALOG.R.Normal(chips) +R_R1 R1(1=0 2=N2 ) CN @CIRCUITEXP1-1.SCHEMATIC1(sch_1):INS85@ANALOG.R.Normal(chips) +_ _(N1=N1) +_ _(N2=N2) +.ENDALIASES diff --git a/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net new file mode 100644 index 0000000..a659917 --- /dev/null +++ b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net @@ -0,0 +1,4 @@ +* source CIRCUITEXP1-1 +V_V1 N1 0 10Vdc +R_R2 N1 N2 3k TC=0,0 +R_R1 0 N2 1k TC=0,0 diff --git a/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp new file mode 100644 index 0000000..bf37e48 --- /dev/null +++ b/CircuitExp1/1-1/CircuitExp1-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp @@ -0,0 +1,41 @@ +("FILE_TYPE" "PMAP File" + ("devices" + ("VDC") + ("R") + ) + ("instances" + ("V1" + ("device_name" "VDC") + ("pspice_path" "V_V1") + ("level" "0") + ("model_params" + ("DC" + ("value" "10Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("R2" + ("device_name" "R") + ("pspice_path" "R_R2") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "3k") + ("pspice_param" "VALUE") + ) + ) + ) + ("R1" + ("device_name" "R") + ("pspice_path" "R_R1") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "1k") + ("pspice_param" "VALUE") + ) + ) + ) + ) +) diff --git a/CircuitExp1/1-1/CircuitExp1-1.opj b/CircuitExp1/1-1/CircuitExp1-1.opj new file mode 100644 index 0000000..b95623f --- /dev/null +++ b/CircuitExp1/1-1/CircuitExp1-1.opj @@ -0,0 +1,51 @@ +(ExpressProject "CircuitExp1-1" + (ProjectVersion "19981106") + (ProjectType "Analog or A/D Mixed Mode") + (Folder "Design Resources" + (Folder "Library") + (NoModify) + (File ".\circuitexp1-1.dsn" + (Type "Schematic Design")) + (BuildFileAddedOrDeleted "x") + (CompileFileAddedOrDeleted "x") + (PSPICE_Regenerate_Netlist_Flag "FALSE")) + (Folder "Outputs" + (File ".\circuitexp1-1-pspicefiles\schematic1\schematic1.net" + (Type "Report"))) + (Folder "PSpice Resources" + (Folder "Simulation Profiles" + (ActiveProfile ".\circuitexp1-1-pspicefiles\schematic1\expsim1-1.sim") + (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91} + ".\circuitexp1-1-pspicefiles\schematic1\expsim1-1.sim" + (DisplayName "SCHEMATIC1-ExpSim1-1") + (Type "PSpice Profile"))) + (Folder "Model Libraries" + (Sort User)) + (Folder "Stimulus Files" + (Sort User)) + (Folder "Include Files" + (Sort User))) + (DefaultLibraryBrowseDirectory "library\PSpice") + (GlobalState + (FileView + (Path "Design Resources") + (Path "Outputs") + (Path "PSpice Resources") + (Path "PSpice Resources" "Simulation Profiles")) + (HierarchyView) + (Doc + (Type "COrCapturePMDoc") + (Frame + (Placement "44 2 3 -1 -1 -8 -31 0 380 0 517")) + (Tab 0)) + (Doc + (Type "COrSchematicDoc") + (Frame + (Placement "44 0 1 -1 -1 -8 -31 76 1581 22 620") + (Scroll "-151 50") + (Zoom "119") + (Occurrence "/")) + (Path "F:\PROJECTS\ANALOGCIRCUIT\CIRCUITEXP1\1-1\CIRCUITEXP1-1.DSN") + (Schematic "SCHEMATIC1") + (Page "PAGE1"))) + (PartMRUSelector)) diff --git a/CircuitExp1/1-1/SCHEMATIC1 _ PAGE1.pdf b/CircuitExp1/1-1/SCHEMATIC1 _ PAGE1.pdf new file mode 100644 index 0000000..db7fc7e Binary files /dev/null and b/CircuitExp1/1-1/SCHEMATIC1 _ PAGE1.pdf differ diff --git a/CircuitExp1/1-1/output_1.pdf b/CircuitExp1/1-1/output_1.pdf new file mode 100644 index 0000000..dfb22e0 Binary files /dev/null and b/CircuitExp1/1-1/output_1.pdf differ diff --git a/CircuitExp1/1-1/output_2.pdf b/CircuitExp1/1-1/output_2.pdf new file mode 100644 index 0000000..c3e53bd Binary files /dev/null and b/CircuitExp1/1-1/output_2.pdf differ diff --git a/CircuitExp1/1-2/CIRCUITEXP1-2.DSN b/CircuitExp1/1-2/CIRCUITEXP1-2.DSN new file mode 100644 index 0000000..06ab8f6 Binary files /dev/null and b/CircuitExp1/1-2/CIRCUITEXP1-2.DSN differ diff --git a/CircuitExp1/1-2/CIRCUITEXP1-2_0.DBK b/CircuitExp1/1-2/CIRCUITEXP1-2_0.DBK new file mode 100644 index 0000000..4e25f17 Binary files /dev/null and b/CircuitExp1/1-2/CIRCUITEXP1-2_0.DBK differ diff --git a/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2.sim b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2.sim new file mode 100644 index 0000000..d13e659 --- /dev/null +++ b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2.sim @@ -0,0 +1,137 @@ +@OrCAD Simulation Server Version: 1.0 + +@Settings: 1 1 +@General: +ProfileName= "ExpSim1-2" +ProfileFile= "ExpSim1-2.sim" +Connectivity= "SCHEMATIC1.net" +NetlistFile= "ExpSim1-2.cir" +DataFile= "ExpSim1-2.dat" +OutFile= "ExpSim1-2.out" +Notes= +@#$BEGINNOTES +@#$ENDNOTES +@End General +@Analysis: 0 0 ++0 0 0 0 ++0 "1000ns" ++1 "" ++2 "0" ++3 "" ++4 "" ++5 "" ++6 "" +@End Analysis +@Analysis: 1 0 ++2 0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 2 1 ++0 0 ++0 "V2" ++1 "" ++2 "" ++3 "" ++4 "0" ++5 "5" ++6 "0.1" ++7 "" +@End Analysis +@Analysis: 3 0 ++0 0 0 ++0 "" ++1 "" ++2 "" +@End Analysis +@Analysis: 4 0 ++0 0 1 0 0 0 1 0 0 0 1 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +LoadFile 0 "" +SaveFile 0 "" +@End Analysis +@Analysis: 5 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 6 0 ++1 ++0 "" +@End Analysis +@Analysis: 7 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 8 0 ++0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 9 0 ++0 "" +@End Analysis +@Analysis: 10 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 11 1 ++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 +@End Analysis +@Analysis: 12 0 ++2236960 0 +@End Analysis +@Analysis: 13 1 ++0 1 1 0 +@End Analysis +@Analysis: 14 1 ++1 1 1 "*" +@End Analysis +@Analysis: 15 0 +@End Analysis +@Analysis: 16 0 ++0 "0" ++1 "0" ++2 "chkpt_default, , ," +@End Analysis +@Analysis: 17 0 ++0 "-1" ++1 "" ++2 "-1" ++3 "-1" ++4 "1" +@End Analysis diff --git a/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2/ExpSim1-2.cir b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2/ExpSim1-2.cir new file mode 100644 index 0000000..e2529b3 --- /dev/null +++ b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2/ExpSim1-2.cir @@ -0,0 +1,18 @@ +** Profile: "SCHEMATIC1-ExpSim1-2" [ F:\Projects\AnalogCircuit\CircuitExp1\1-2\CircuitExp1-2-PSpiceFiles\SCHEMATIC1\ExpSim1-2.sim ] + +** Creating circuit file "ExpSim1-2.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.DC LIN V_V2 0 5 0.1 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + +.END diff --git a/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2/ExpSim1-2.mif b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2/ExpSim1-2.mif new file mode 100644 index 0000000..1e7d074 --- /dev/null +++ b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2/ExpSim1-2.mif @@ -0,0 +1 @@ + lib=D:\OrCAD\OrCAD_16.5_Lite\tools\PSpice\Library\eval.lib, offset=22016, size=222 diff --git a/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2/ExpSim1-2.mrk b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2/ExpSim1-2.mrk new file mode 100644 index 0000000..3aeb278 Binary files /dev/null and b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2/ExpSim1-2.mrk differ diff --git a/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2/ExpSim1-2.out b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2/ExpSim1-2.out new file mode 100644 index 0000000..a8edc6a --- /dev/null +++ b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2/ExpSim1-2.out @@ -0,0 +1,83 @@ + +**** 09/20/24 10:40:11 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim1-2" [ F:\Projects\AnalogCircuit\CircuitExp1\1-2\CircuitExp1-2-PSpiceFiles\SCHEMATIC1\ExpSim1-2.sim ] + + + **** CIRCUIT DESCRIPTION + + +****************************************************************************** + + + + +** Creating circuit file "ExpSim1-2.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.DC LIN V_V2 0 5 0.1 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + + +**** INCLUDING SCHEMATIC1.net **** +* source CIRCUITEXP1-2 +R_R4 N3 N4 200 TC=0,0 +D_D1 N4 0 D1N4002 +V_V2 N3 0 5Vdc + +**** RESUMING ExpSim1-2.cir **** +.END + +**** 09/20/24 10:40:11 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim1-2" [ F:\Projects\AnalogCircuit\CircuitExp1\1-2\CircuitExp1-2-PSpiceFiles\SCHEMATIC1\ExpSim1-2.sim ] + + + **** Diode MODEL PARAMETERS + + +****************************************************************************** + + + + + D1N4002 + IS 14.110000E-09 + N 1.984 + ISR 100.000000E-12 + IKF 94.81 + BV 100.1 + IBV 10 + RS .03389 + TT 4.761000E-06 + CJO 51.170000E-12 + VJ .3905 + M .2762 + + + + JOB CONCLUDED + +**** 09/20/24 10:40:11 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim1-2" [ F:\Projects\AnalogCircuit\CircuitExp1\1-2\CircuitExp1-2-PSpiceFiles\SCHEMATIC1\ExpSim1-2.sim ] + + + **** JOB STATISTICS SUMMARY + + +****************************************************************************** + + + + Total job time (using Solver 1) = 0.00 + \ No newline at end of file diff --git a/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2/ExpSim1-2.prb b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2/ExpSim1-2.prb new file mode 100644 index 0000000..81363d3 --- /dev/null +++ b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/ExpSim1-2/ExpSim1-2.prb @@ -0,0 +1,80 @@ +[DISPLAYS] +BEGIN DISPLAY LAST SESSION +ANALYSIS DC_SWEEP +SYMBOL ALWAYS +TRACECOLORSCHEME NORMAL +BEGIN ANAPLOT 1 +ACTIVE +XBASE +BEGIN XAXIS +XAXISUSERNAME 0 (null) +RANGEFLAG AUTO +TYPE LINEAR +UNIT V +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +END XAXIS +BEGIN YAXIS 1 +YAXISSIDE LEFT +RANGEFLAG AUTO +TYPE LINEAR +UNIT V +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +BEGIN TRACE V(N4) +MARKERID 4 +INSTANCE 1 TRACECOLOR 3 +INSTANCE 1 TRACEPATTERN DASH +INSTANCE 1 TRACEWIDTH 2 +INSTANCE 1 TRACESYMBOL 0 +INSTANCE 1 TRACEUSERMODIFIED +END TRACE V(N4) +END YAXIS 1 +BEGIN YAXIS 2 +YAXISSIDE LEFT +ACTIVE +RANGEFLAG AUTO +TYPE LINEAR +UNIT A +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +BEGIN TRACE I(D1) +MARKERID 5 +INSTANCE 1 TRACECOLOR 4 +INSTANCE 1 TRACEWIDTH 2 +INSTANCE 1 TRACESYMBOL 1 +INSTANCE 1 TRACEUSERMODIFIED +END TRACE I(D1) +BEGIN LABEL +TYPE TEXT +TEXT 鐗╄仈缃234_2330110900_寮犻【鐨撱 +LABELTEXTSIZE 12 +LABELTEXTTYPE 0 +LABELTEXTFONT Arial +LABELTEXTCOLOR 0 +LABELTEXTSCRIPT 0 +STARTX 3.04109589041096 +STARTY 0.00368686868686868 +COLOR 7 +END LABEL +END YAXIS 2 +END ANAPLOT 1 +END DISPLAY LAST SESSION diff --git a/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS new file mode 100644 index 0000000..349e33d --- /dev/null +++ b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS @@ -0,0 +1,7 @@ +.ALIASES +R_R4 R4(1=N3 2=N4 ) CN @CIRCUITEXP1-2.SCHEMATIC1(sch_1):INS40@ANALOG.R.Normal(chips) +D_D1 D1(1=N4 2=0 ) CN @CIRCUITEXP1-2.SCHEMATIC1(sch_1):INS65@EVAL.D1N4002.Normal(chips) +V_V2 V2(+=N3 -=0 ) CN @CIRCUITEXP1-2.SCHEMATIC1(sch_1):INS90@SOURCE.VDC.Normal(chips) +_ _(N3=N3) +_ _(N4=N4) +.ENDALIASES diff --git a/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net new file mode 100644 index 0000000..1f47079 --- /dev/null +++ b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net @@ -0,0 +1,4 @@ +* source CIRCUITEXP1-2 +R_R4 N3 N4 200 TC=0,0 +D_D1 N4 0 D1N4002 +V_V2 N3 0 5Vdc diff --git a/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp new file mode 100644 index 0000000..193f716 --- /dev/null +++ b/CircuitExp1/1-2/CircuitExp1-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp @@ -0,0 +1,30 @@ +("FILE_TYPE" "PMAP File" + ("devices" + ("R") + ("VDC") + ) + ("instances" + ("R4" + ("device_name" "R") + ("pspice_path" "R_R4") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "200") + ("pspice_param" "VALUE") + ) + ) + ) + ("V2" + ("device_name" "VDC") + ("pspice_path" "V_V2") + ("level" "0") + ("model_params" + ("DC" + ("value" "5Vdc") + ("pspice_param" "DC") + ) + ) + ) + ) +) diff --git a/CircuitExp1/1-2/CircuitExp1-2.opj b/CircuitExp1/1-2/CircuitExp1-2.opj new file mode 100644 index 0000000..a3f8b2c --- /dev/null +++ b/CircuitExp1/1-2/CircuitExp1-2.opj @@ -0,0 +1,69 @@ +(ExpressProject "CircuitExp1-2" + (ProjectVersion "19981106") + (ProjectType "Analog or A/D Mixed Mode") + (Folder "Design Resources" + (Folder "Library") + (NoModify) + (File ".\circuitexp1-2.dsn" + (Type "Schematic Design")) + (BuildFileAddedOrDeleted "x") + (CompileFileAddedOrDeleted "x") + (PSPICE_Regenerate_Netlist_Flag "FALSE")) + (Folder "Outputs" + (File ".\circuitexp1-2-pspicefiles\schematic1\schematic1.net" + (Type "Report"))) + (Folder "PSpice Resources" + (Folder "Simulation Profiles" + (ActiveProfile ".\circuitexp1-2-pspicefiles\schematic1\expsim1-2.sim") + (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91} + ".\circuitexp1-2-pspicefiles\schematic1\expsim1-2.sim" + (DisplayName "SCHEMATIC1-ExpSim1-2") + (Type "PSpice Profile"))) + (Folder "Model Libraries" + (Sort User)) + (Folder "Stimulus Files" + (Sort User)) + (Folder "Include Files" + (Sort User))) + (DefaultLibraryBrowseDirectory "library\PSpice") + (PartMRUSelector + (0 + (LibraryName "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB") + (DeviceIndex "0")) + (VDC + (FullPartName "VDC.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\SOURCE.OLB") + (DeviceIndex "0")) + (D1N4002 + (FullPartName "D1N4002.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\EVAL.OLB") + (DeviceIndex "0")) + (R + (FullPartName "R.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\ANALOG.OLB") + (DeviceIndex "0"))) + (GlobalState + (FileView + (Path "Design Resources") + (Path "Outputs")) + (HierarchyView) + (Doc + (Type "COrCapturePMDoc") + (Frame + (Placement "44 2 3 -1 -1 -8 -31 0 200 0 426")) + (Tab 0)) + (Doc + (Type "COrSchematicDoc") + (Frame + (Placement "44 0 1 -1 -1 -8 -31 25 1508 63 528") + (Scroll "441 685") + (Zoom "255") + (Occurrence "/")) + (Path "F:\PROJECTS\ANALOGCIRCUIT\CIRCUITEXP1\1-2\CIRCUITEXP1-2.DSN") + (Schematic "SCHEMATIC1") + (Page "PAGE1"))) + (LastUsedLibraryBrowseDirectory + "D:\OrCAD\OrCAD_16.5_Lite\tools\capture\library\pspice")) diff --git a/CircuitExp1/1-2/SCHEMATIC1 _ PAGE1.pdf b/CircuitExp1/1-2/SCHEMATIC1 _ PAGE1.pdf new file mode 100644 index 0000000..8d080ab Binary files /dev/null and b/CircuitExp1/1-2/SCHEMATIC1 _ PAGE1.pdf differ diff --git a/CircuitExp1/1-2/output.pdf b/CircuitExp1/1-2/output.pdf new file mode 100644 index 0000000..c5efa37 Binary files /dev/null and b/CircuitExp1/1-2/output.pdf differ diff --git a/CircuitExp1/1.docx b/CircuitExp1/1.docx new file mode 100644 index 0000000..4cb9bb7 Binary files /dev/null and b/CircuitExp1/1.docx differ diff --git a/CircuitExp1/1.pdf b/CircuitExp1/1.pdf new file mode 100644 index 0000000..f3e6f24 Binary files /dev/null and b/CircuitExp1/1.pdf differ diff --git a/CircuitExp2/2-1/CIRCUITEXP2-1.DSN b/CircuitExp2/2-1/CIRCUITEXP2-1.DSN new file mode 100644 index 0000000..59669d4 Binary files /dev/null and b/CircuitExp2/2-1/CIRCUITEXP2-1.DSN differ diff --git a/CircuitExp2/2-1/CIRCUITEXP2-1_0.DBK b/CircuitExp2/2-1/CIRCUITEXP2-1_0.DBK new file mode 100644 index 0000000..c41078c Binary files /dev/null and b/CircuitExp2/2-1/CIRCUITEXP2-1_0.DBK differ diff --git a/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1-summary.sim b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1-summary.sim new file mode 100644 index 0000000..6fbc711 --- /dev/null +++ b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1-summary.sim @@ -0,0 +1,137 @@ +@OrCAD Simulation Server Version: 1.0 + +@Settings: 1 1 +@General: +ProfileName= "ExpSim2-1-summary" +ProfileFile= "ExpSim2-1-summary.sim" +Connectivity= "SCHEMATIC1.net" +NetlistFile= "ExpSim2-1-summary.cir" +DataFile= "ExpSim2-1-summary.dat" +OutFile= "ExpSim2-1-summary.out" +Notes= +@#$BEGINNOTES +@#$ENDNOTES +@End General +@Analysis: 0 0 ++0 0 0 0 ++0 "1000ns" ++1 "" ++2 "0" ++3 "" ++4 "" ++5 "" ++6 "" +@End Analysis +@Analysis: 1 0 ++2 0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 2 1 ++0 0 ++0 "V1" ++1 "" ++2 "" ++3 "" ++4 "0" ++5 "4" ++6 "0.5" ++7 "" +@End Analysis +@Analysis: 3 0 ++0 0 0 ++0 "" ++1 "" ++2 "" +@End Analysis +@Analysis: 4 0 ++0 0 1 0 0 0 1 0 0 0 1 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +LoadFile 0 "" +SaveFile 0 "" +@End Analysis +@Analysis: 5 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 6 0 ++1 ++0 "" +@End Analysis +@Analysis: 7 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 8 0 ++0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 9 0 ++0 "" +@End Analysis +@Analysis: 10 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 11 1 ++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 +@End Analysis +@Analysis: 12 0 ++2236960 0 +@End Analysis +@Analysis: 13 1 ++0 1 1 0 +@End Analysis +@Analysis: 14 1 ++1 1 1 "*" +@End Analysis +@Analysis: 15 0 +@End Analysis +@Analysis: 16 0 ++0 "0" ++1 "0" ++2 "chkpt_default, , ," +@End Analysis +@Analysis: 17 0 ++0 "-1" ++1 "" ++2 "-1" ++3 "-1" ++4 "1" +@End Analysis diff --git a/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1-summary/ExpSim2-1-summary.cir b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1-summary/ExpSim2-1-summary.cir new file mode 100644 index 0000000..8ff0ac7 --- /dev/null +++ b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1-summary/ExpSim2-1-summary.cir @@ -0,0 +1,18 @@ +** Profile: "SCHEMATIC1-ExpSim2-1-summary" [ F:\Projects\AnalogCircuit\CircuitExp2\2-1\CircuitExp2-1-PSpiceFiles\SCHEMATIC1\ExpSim2-1-summary.sim ] + +** Creating circuit file "ExpSim2-1-summary.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.DC LIN V_V1 0 4 0.5 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + +.END diff --git a/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1-summary/ExpSim2-1-summary.mrk b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1-summary/ExpSim2-1-summary.mrk new file mode 100644 index 0000000..f721458 Binary files /dev/null and b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1-summary/ExpSim2-1-summary.mrk differ diff --git a/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1-summary/ExpSim2-1-summary.out b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1-summary/ExpSim2-1-summary.out new file mode 100644 index 0000000..b87388d --- /dev/null +++ b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1-summary/ExpSim2-1-summary.out @@ -0,0 +1,56 @@ + +**** 09/20/24 11:10:38 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim2-1-summary" [ F:\Projects\AnalogCircuit\CircuitExp2\2-1\CircuitExp2-1-PSpiceFiles\SCHEMATIC1\ExpSim2 + + + **** CIRCUIT DESCRIPTION + + +****************************************************************************** + + + + +** Creating circuit file "ExpSim2-1-summary.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.DC LIN V_V1 0 4 0.5 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + + +**** INCLUDING SCHEMATIC1.net **** +* source CIRCUITEXP2-1 +V_V1 N00144 0 3Vdc +G_G1 N00169 0 N00144 0 0.01 +R_R1 0 N00169 1k TC=0,0 + +**** RESUMING ExpSim2-1-summary.cir **** +.END + + + JOB CONCLUDED + +**** 09/20/24 11:10:38 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim2-1-summary" [ F:\Projects\AnalogCircuit\CircuitExp2\2-1\CircuitExp2-1-PSpiceFiles\SCHEMATIC1\ExpSim2 + + + **** JOB STATISTICS SUMMARY + + +****************************************************************************** + + + + Total job time (using Solver 1) = 0.00 + \ No newline at end of file diff --git a/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1-summary/ExpSim2-1-summary.prb b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1-summary/ExpSim2-1-summary.prb new file mode 100644 index 0000000..5df55d4 --- /dev/null +++ b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1-summary/ExpSim2-1-summary.prb @@ -0,0 +1,58 @@ +[DISPLAYS] +BEGIN DISPLAY LAST SESSION +ANALYSIS DC_SWEEP +SYMBOL ALWAYS +TRACECOLORSCHEME NORMAL +BEGIN ANAPLOT 1 +ACTIVE +XBASE +BEGIN XAXIS +XAXISUSERNAME 0 (null) +RANGEFLAG AUTO +TYPE LINEAR +UNIT V +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +END XAXIS +BEGIN YAXIS 1 +YAXISSIDE LEFT +ACTIVE +RANGEFLAG AUTO +TYPE LINEAR +UNIT A +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +BEGIN TRACE I(R1) +MARKERID 1 +INSTANCE 1 TRACECOLOR 3 +INSTANCE 1 TRACEWIDTH 2 +INSTANCE 1 TRACESYMBOL 0 +INSTANCE 1 TRACEUSERMODIFIED +END TRACE I(R1) +BEGIN LABEL +TYPE TEXT +TEXT 鐗╄仈缃234_2330110900_寮犻【鐨 +LABELTEXTSIZE 12 +LABELTEXTTYPE 0 +LABELTEXTFONT Arial +LABELTEXTCOLOR 0 +LABELTEXTSCRIPT 0 +STARTX 1.67010309278351 +STARTY 0.0292255892255892 +COLOR 7 +END LABEL +END YAXIS 1 +END ANAPLOT 1 +END DISPLAY LAST SESSION diff --git a/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1.sim b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1.sim new file mode 100644 index 0000000..5e5bb77 --- /dev/null +++ b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1.sim @@ -0,0 +1,137 @@ +@OrCAD Simulation Server Version: 1.0 + +@Settings: 0 1 +@General: +ProfileName= "ExpSim2-1" +ProfileFile= "ExpSim2-1.sim" +Connectivity= "SCHEMATIC1.net" +NetlistFile= "ExpSim2-1.cir" +DataFile= "ExpSim2-1.dat" +OutFile= "ExpSim2-1.out" +Notes= +@#$BEGINNOTES +@#$ENDNOTES +@End General +@Analysis: 0 1 ++0 0 0 0 ++0 "10ms" ++1 "" ++2 "0" ++3 "" ++4 "" ++5 "" ++6 "" +@End Analysis +@Analysis: 1 0 ++2 0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 2 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 3 0 ++0 0 0 ++0 "" ++1 "" ++2 "" +@End Analysis +@Analysis: 4 0 ++0 0 1 0 0 0 0 0 0 0 1 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +LoadFile 0 "" +SaveFile 0 "" +@End Analysis +@Analysis: 5 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 6 0 ++1 ++0 "" +@End Analysis +@Analysis: 7 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 8 0 ++0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 9 0 ++0 "" +@End Analysis +@Analysis: 10 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 11 1 ++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 +@End Analysis +@Analysis: 12 0 ++2236960 0 +@End Analysis +@Analysis: 13 1 ++0 1 1 0 +@End Analysis +@Analysis: 14 1 ++1 1 1 "*" +@End Analysis +@Analysis: 15 0 +@End Analysis +@Analysis: 16 0 ++0 "0" ++1 "0" ++2 "chkpt_default, , ," +@End Analysis +@Analysis: 17 0 ++0 "-1" ++1 "" ++2 "-1" ++3 "-1" ++4 "1" +@End Analysis diff --git a/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1/ExpSim2-1.1OP b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1/ExpSim2-1.1OP new file mode 100644 index 0000000..4edf242 Binary files /dev/null and b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1/ExpSim2-1.1OP differ diff --git a/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1/ExpSim2-1.cir b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1/ExpSim2-1.cir new file mode 100644 index 0000000..4ca13a7 --- /dev/null +++ b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1/ExpSim2-1.cir @@ -0,0 +1,18 @@ +** Profile: "SCHEMATIC1-ExpSim2-1" [ F:\Projects\AnalogCircuit\CircuitExp2\2-1\circuitexp2-1-pspicefiles\schematic1\expsim2-1.sim ] + +** Creating circuit file "ExpSim2-1.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.TRAN 0 10ms 0 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + +.END diff --git a/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1/ExpSim2-1.mrk b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1/ExpSim2-1.mrk new file mode 100644 index 0000000..a1c2448 Binary files /dev/null and b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1/ExpSim2-1.mrk differ diff --git a/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1/ExpSim2-1.out b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1/ExpSim2-1.out new file mode 100644 index 0000000..a1e5217 --- /dev/null +++ b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/ExpSim2-1/ExpSim2-1.out @@ -0,0 +1,84 @@ + +**** 09/20/24 11:39:47 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim2-1" [ F:\Projects\AnalogCircuit\CircuitExp2\2-1\circuitexp2-1-pspicefiles\schematic1\expsim2-1.sim ] + + + **** CIRCUIT DESCRIPTION + + +****************************************************************************** + + + + +** Creating circuit file "ExpSim2-1.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.TRAN 0 10ms 0 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + + +**** INCLUDING SCHEMATIC1.net **** +* source CIRCUITEXP2-1 +V_V1 N00144 0 3Vdc +G_G1 N00169 0 N00144 0 0.01 +R_R1 0 N00169 9k TC=0,0 + +**** RESUMING ExpSim2-1.cir **** +.END + +**** 09/20/24 11:39:47 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim2-1" [ F:\Projects\AnalogCircuit\CircuitExp2\2-1\circuitexp2-1-pspicefiles\schematic1\expsim2-1.sim ] + + + **** INITIAL TRANSIENT SOLUTION TEMPERATURE = 27.000 DEG C + + +****************************************************************************** + + + + NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE + + +(N00144) 3.0000 (N00169) -270.0000 + + + + + VOLTAGE SOURCE CURRENTS + NAME CURRENT + + V_V1 0.000E+00 + + TOTAL POWER DISSIPATION 0.00E+00 WATTS + + + + JOB CONCLUDED + +**** 09/20/24 11:39:47 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim2-1" [ F:\Projects\AnalogCircuit\CircuitExp2\2-1\circuitexp2-1-pspicefiles\schematic1\expsim2-1.sim ] + + + **** JOB STATISTICS SUMMARY + + +****************************************************************************** + + + + Total job time (using Solver 1) = 0.00 + \ No newline at end of file diff --git a/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS new file mode 100644 index 0000000..4744c78 --- /dev/null +++ b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS @@ -0,0 +1,5 @@ +.ALIASES +V_V1 V1(+=N00144 -=0 ) CN @CIRCUITEXP2-1.SCHEMATIC1(sch_1):INS40@SOURCE.VDC.Normal(chips) +G_G1 G1(3=N00169 4=0 1=N00144 2=0 ) CN @CIRCUITEXP2-1.SCHEMATIC1(sch_1):INS71@ANALOG.G.Normal(chips) +R_R1 R1(1=0 2=N00169 ) CN @CIRCUITEXP2-1.SCHEMATIC1(sch_1):INS104@ANALOG.R.Normal(chips) +.ENDALIASES diff --git a/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net new file mode 100644 index 0000000..92c143d --- /dev/null +++ b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net @@ -0,0 +1,4 @@ +* source CIRCUITEXP2-1 +V_V1 N00144 0 3Vdc +G_G1 N00169 0 N00144 0 0.01 +R_R1 0 N00169 9k TC=0,0 diff --git a/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp new file mode 100644 index 0000000..5aff42c --- /dev/null +++ b/CircuitExp2/2-1/CircuitExp2-1-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp @@ -0,0 +1,30 @@ +("FILE_TYPE" "PMAP File" + ("devices" + ("VDC") + ("R") + ) + ("instances" + ("V1" + ("device_name" "VDC") + ("pspice_path" "V_V1") + ("level" "0") + ("model_params" + ("DC" + ("value" "3Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("R1" + ("device_name" "R") + ("pspice_path" "R_R1") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "9k") + ("pspice_param" "VALUE") + ) + ) + ) + ) +) diff --git a/CircuitExp2/2-1/CircuitExp2-1.opj b/CircuitExp2/2-1/CircuitExp2-1.opj new file mode 100644 index 0000000..dd95ad1 --- /dev/null +++ b/CircuitExp2/2-1/CircuitExp2-1.opj @@ -0,0 +1,75 @@ +(ExpressProject "CircuitExp2-1" + (ProjectVersion "19981106") + (ProjectType "Analog or A/D Mixed Mode") + (Folder "Design Resources" + (Folder "Library") + (NoModify) + (File ".\circuitexp2-1.dsn" + (Type "Schematic Design")) + (BuildFileAddedOrDeleted "x") + (CompileFileAddedOrDeleted "x") + (PSPICE_Regenerate_Netlist_Flag "FALSE")) + (Folder "Outputs" + (File ".\circuitexp2-1-pspicefiles\schematic1\schematic1.net" + (Type "Report"))) + (Folder "PSpice Resources" + (Folder "Simulation Profiles" + (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91} + ".\circuitexp2-1-pspicefiles\schematic1\expsim2-1.sim" + (DisplayName "SCHEMATIC1-ExpSim2-1") + (Type "PSpice Profile")) + (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91} + ".\circuitexp2-1-pspicefiles\schematic1\expsim2-1-summary.sim" + (DisplayName "SCHEMATIC1-ExpSim2-1-summary") + (Type "PSpice Profile")) + (ActiveProfile ".\circuitexp2-1-pspicefiles\schematic1\expsim2-1.sim")) + (Folder "Model Libraries" + (Sort User)) + (Folder "Stimulus Files" + (Sort User)) + (Folder "Include Files" + (Sort User))) + (DefaultLibraryBrowseDirectory "library\PSpice") + (GlobalState + (FileView + (Path "Design Resources") + (Path "Outputs") + (Path "PSpice Resources") + (Path "PSpice Resources" "Simulation Profiles") + (Select "PSpice Resources" "Simulation Profiles" + ".\circuitexp2-1-pspicefiles\schematic1\expsim2-1.sim")) + (HierarchyView) + (Doc + (Type "COrCapturePMDoc") + (Frame + (Placement "44 2 3 -1 -1 -8 -31 0 200 0 426")) + (Tab 0)) + (Doc + (Type "COrSchematicDoc") + (Frame + (Placement "44 0 1 -1 -1 -8 -31 26 1441 26 491") + (Scroll "1156 896") + (Zoom "400") + (Occurrence "/")) + (Path "F:\PROJECTS\ANALOGCIRCUIT\CIRCUITEXP2\2-1\CIRCUITEXP2-1.DSN") + (Schematic "SCHEMATIC1") + (Page "PAGE1"))) + (PartMRUSelector + (0 + (LibraryName "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB") + (DeviceIndex "0")) + (R + (FullPartName "R.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\ANALOG.OLB") + (DeviceIndex "0")) + (G + (FullPartName "G.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\ANALOG.OLB") + (DeviceIndex "0")) + (VDC + (FullPartName "VDC.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\SOURCE.OLB") + (DeviceIndex "0")))) diff --git a/CircuitExp2/2-1/ExpSim2-1-summary.pdf b/CircuitExp2/2-1/ExpSim2-1-summary.pdf new file mode 100644 index 0000000..abc5520 Binary files /dev/null and b/CircuitExp2/2-1/ExpSim2-1-summary.pdf differ diff --git a/CircuitExp2/2-1/SCHEMATIC1 _ PAGE1.pdf b/CircuitExp2/2-1/SCHEMATIC1 _ PAGE1.pdf new file mode 100644 index 0000000..b94419b Binary files /dev/null and b/CircuitExp2/2-1/SCHEMATIC1 _ PAGE1.pdf differ diff --git a/CircuitExp2/2-1/output2_1.pdf b/CircuitExp2/2-1/output2_1.pdf new file mode 100644 index 0000000..30fa47e Binary files /dev/null and b/CircuitExp2/2-1/output2_1.pdf differ diff --git a/CircuitExp2/2-1/output2_2.pdf b/CircuitExp2/2-1/output2_2.pdf new file mode 100644 index 0000000..f07a173 Binary files /dev/null and b/CircuitExp2/2-1/output2_2.pdf differ diff --git a/CircuitExp2/2-1/output2_3.pdf b/CircuitExp2/2-1/output2_3.pdf new file mode 100644 index 0000000..1dd8cbe Binary files /dev/null and b/CircuitExp2/2-1/output2_3.pdf differ diff --git a/CircuitExp2/2-1/output2_4.pdf b/CircuitExp2/2-1/output2_4.pdf new file mode 100644 index 0000000..f0243ec Binary files /dev/null and b/CircuitExp2/2-1/output2_4.pdf differ diff --git a/CircuitExp2/2-1/output2_5.pdf b/CircuitExp2/2-1/output2_5.pdf new file mode 100644 index 0000000..3e1a65e Binary files /dev/null and b/CircuitExp2/2-1/output2_5.pdf differ diff --git a/CircuitExp2/2-1/output2_6.pdf b/CircuitExp2/2-1/output2_6.pdf new file mode 100644 index 0000000..dc8e039 Binary files /dev/null and b/CircuitExp2/2-1/output2_6.pdf differ diff --git a/CircuitExp2/2-1/output2_7.pdf b/CircuitExp2/2-1/output2_7.pdf new file mode 100644 index 0000000..f236879 Binary files /dev/null and b/CircuitExp2/2-1/output2_7.pdf differ diff --git a/CircuitExp2/2-1/output2_8.pdf b/CircuitExp2/2-1/output2_8.pdf new file mode 100644 index 0000000..5f64f58 Binary files /dev/null and b/CircuitExp2/2-1/output2_8.pdf differ diff --git a/CircuitExp2/2-1/output2_9.pdf b/CircuitExp2/2-1/output2_9.pdf new file mode 100644 index 0000000..63ab1e1 Binary files /dev/null and b/CircuitExp2/2-1/output2_9.pdf differ diff --git a/CircuitExp2/2-1/output_1.pdf b/CircuitExp2/2-1/output_1.pdf new file mode 100644 index 0000000..b1e8d86 Binary files /dev/null and b/CircuitExp2/2-1/output_1.pdf differ diff --git a/CircuitExp2/2-1/output_2.pdf b/CircuitExp2/2-1/output_2.pdf new file mode 100644 index 0000000..5d1e9c5 Binary files /dev/null and b/CircuitExp2/2-1/output_2.pdf differ diff --git a/CircuitExp2/2-1/output_3.pdf b/CircuitExp2/2-1/output_3.pdf new file mode 100644 index 0000000..4b72a10 Binary files /dev/null and b/CircuitExp2/2-1/output_3.pdf differ diff --git a/CircuitExp2/2-1/output_4.pdf b/CircuitExp2/2-1/output_4.pdf new file mode 100644 index 0000000..eb8ba6f Binary files /dev/null and b/CircuitExp2/2-1/output_4.pdf differ diff --git a/CircuitExp2/2-1/output_5.pdf b/CircuitExp2/2-1/output_5.pdf new file mode 100644 index 0000000..9cab513 Binary files /dev/null and b/CircuitExp2/2-1/output_5.pdf differ diff --git a/CircuitExp2/2-1/output_6.pdf b/CircuitExp2/2-1/output_6.pdf new file mode 100644 index 0000000..80bc2f2 Binary files /dev/null and b/CircuitExp2/2-1/output_6.pdf differ diff --git a/CircuitExp2/2-1/output_7.pdf b/CircuitExp2/2-1/output_7.pdf new file mode 100644 index 0000000..2a7b953 Binary files /dev/null and b/CircuitExp2/2-1/output_7.pdf differ diff --git a/CircuitExp2/2-1/output_8.pdf b/CircuitExp2/2-1/output_8.pdf new file mode 100644 index 0000000..e771e4b Binary files /dev/null and b/CircuitExp2/2-1/output_8.pdf differ diff --git a/CircuitExp2/2-1/output_9.pdf b/CircuitExp2/2-1/output_9.pdf new file mode 100644 index 0000000..f8dd638 Binary files /dev/null and b/CircuitExp2/2-1/output_9.pdf differ diff --git a/CircuitExp2/2-2/CIRCUITEXP2-2.DSN b/CircuitExp2/2-2/CIRCUITEXP2-2.DSN new file mode 100644 index 0000000..3c6481b Binary files /dev/null and b/CircuitExp2/2-2/CIRCUITEXP2-2.DSN differ diff --git a/CircuitExp2/2-2/CIRCUITEXP2-2_0.DBK b/CircuitExp2/2-2/CIRCUITEXP2-2_0.DBK new file mode 100644 index 0000000..180decd Binary files /dev/null and b/CircuitExp2/2-2/CIRCUITEXP2-2_0.DBK differ diff --git a/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2-summary.sim b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2-summary.sim new file mode 100644 index 0000000..e1518f5 --- /dev/null +++ b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2-summary.sim @@ -0,0 +1,137 @@ +@OrCAD Simulation Server Version: 1.0 + +@Settings: 1 1 +@General: +ProfileName= "ExpSim2-2-summary" +ProfileFile= "ExpSim2-2-summary.sim" +Connectivity= "SCHEMATIC1.net" +NetlistFile= "ExpSim2-2-summary.cir" +DataFile= "ExpSim2-2-summary.dat" +OutFile= "ExpSim2-2-summary.out" +Notes= +@#$BEGINNOTES +@#$ENDNOTES +@End General +@Analysis: 0 0 ++0 0 0 0 ++0 "1000ns" ++1 "" ++2 "0" ++3 "" ++4 "" ++5 "" ++6 "" +@End Analysis +@Analysis: 1 0 ++2 0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 2 1 ++0 1 ++0 "I1" ++1 "" ++2 "" ++3 "" ++4 "0.0001" ++5 "0.0004" ++6 "0.00001" ++7 "" +@End Analysis +@Analysis: 3 0 ++0 0 0 ++0 "" ++1 "" ++2 "" +@End Analysis +@Analysis: 4 0 ++0 0 1 0 0 0 1 0 0 0 1 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +LoadFile 0 "" +SaveFile 0 "" +@End Analysis +@Analysis: 5 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 6 0 ++1 ++0 "" +@End Analysis +@Analysis: 7 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 8 0 ++0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 9 0 ++0 "" +@End Analysis +@Analysis: 10 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 11 1 ++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 +@End Analysis +@Analysis: 12 0 ++2236960 0 +@End Analysis +@Analysis: 13 1 ++0 1 1 0 +@End Analysis +@Analysis: 14 1 ++1 1 1 "*" +@End Analysis +@Analysis: 15 0 +@End Analysis +@Analysis: 16 0 ++0 "0" ++1 "0" ++2 "chkpt_default, , ," +@End Analysis +@Analysis: 17 0 ++0 "-1" ++1 "" ++2 "-1" ++3 "-1" ++4 "1" +@End Analysis diff --git a/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2-summary/ExpSim2-2-summary.cir b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2-summary/ExpSim2-2-summary.cir new file mode 100644 index 0000000..cd6a31b --- /dev/null +++ b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2-summary/ExpSim2-2-summary.cir @@ -0,0 +1,18 @@ +** Profile: "SCHEMATIC1-ExpSim2-2-summary" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-2\CircuitExp2-2-PSpiceFiles\SCHEMATIC1\ExpSim2-2-summary.sim ] + +** Creating circuit file "ExpSim2-2-summary.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.DC LIN I_I1 0.0001 0.0004 0.00001 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + +.END diff --git a/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2-summary/ExpSim2-2-summary.mrk b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2-summary/ExpSim2-2-summary.mrk new file mode 100644 index 0000000..4239934 Binary files /dev/null and b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2-summary/ExpSim2-2-summary.mrk differ diff --git a/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2-summary/ExpSim2-2-summary.out b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2-summary/ExpSim2-2-summary.out new file mode 100644 index 0000000..814443f --- /dev/null +++ b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2-summary/ExpSim2-2-summary.out @@ -0,0 +1,61 @@ + +**** 09/27/24 10:43:57 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim2-2-summary" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-2\CircuitExp2-2-PSpiceFiles\SCHEMATIC1\ExpSi + + + **** CIRCUIT DESCRIPTION + + +****************************************************************************** + + + + +** Creating circuit file "ExpSim2-2-summary.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.DC LIN I_I1 0.0001 0.0004 0.00001 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + + +**** INCLUDING SCHEMATIC1.net **** +* source CIRCUITEXP2-2 +I_I1 0 N00144 DC 0.1Adc +X_H1 N00144 0 N00156 0 SCHEMATIC1_H1 +R_R1 0 N00156 1k TC=0,0 + +.subckt SCHEMATIC1_H1 1 2 3 4 +H_H1 3 4 VH_H1 10 +VH_H1 1 2 0V +.ends SCHEMATIC1_H1 + +**** RESUMING ExpSim2-2-summary.cir **** +.END + + + JOB CONCLUDED + +**** 09/27/24 10:43:57 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim2-2-summary" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-2\CircuitExp2-2-PSpiceFiles\SCHEMATIC1\ExpSi + + + **** JOB STATISTICS SUMMARY + + +****************************************************************************** + + + + Total job time (using Solver 1) = 0.00 + \ No newline at end of file diff --git a/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2-summary/ExpSim2-2-summary.prb b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2-summary/ExpSim2-2-summary.prb new file mode 100644 index 0000000..43ffb28 --- /dev/null +++ b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2-summary/ExpSim2-2-summary.prb @@ -0,0 +1,54 @@ +[DISPLAYS] +BEGIN DISPLAY LAST SESSION +ANALYSIS DC_SWEEP +SYMBOL ALWAYS +TRACECOLORSCHEME NORMAL +BEGIN ANAPLOT 1 +ACTIVE +XBASE +BEGIN XAXIS +XAXISUSERNAME 0 (null) +RANGEFLAG AUTO +TYPE LINEAR +UNIT A +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +END XAXIS +BEGIN YAXIS 1 +YAXISSIDE LEFT +ACTIVE +RANGEFLAG AUTO +TYPE LINEAR +UNIT V +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +BEGIN TRACE V2(R1) +MARKERID 2 +END TRACE V2(R1) +BEGIN LABEL +TYPE TEXT +TEXT 鐗╄仈缃234_2330110900_寮犻【鐨 +LABELTEXTSIZE 12 +LABELTEXTTYPE 0 +LABELTEXTFONT Arial +LABELTEXTCOLOR 0 +LABELTEXTSCRIPT 0 +STARTX 0.000192023346303502 +STARTY 0.00271212132054974 +COLOR 7 +END LABEL +END YAXIS 1 +END ANAPLOT 1 +END DISPLAY LAST SESSION diff --git a/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2.sim b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2.sim new file mode 100644 index 0000000..d85864d --- /dev/null +++ b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2.sim @@ -0,0 +1,137 @@ +@OrCAD Simulation Server Version: 1.0 + +@Settings: 0 1 +@General: +ProfileName= "ExpSim2-2" +ProfileFile= "ExpSim2-2.sim" +Connectivity= "SCHEMATIC1.net" +NetlistFile= "ExpSim2-2.cir" +DataFile= "ExpSim2-2.dat" +OutFile= "ExpSim2-2.out" +Notes= +@#$BEGINNOTES +@#$ENDNOTES +@End General +@Analysis: 0 1 ++0 0 0 0 ++0 "10ms" ++1 "" ++2 "0" ++3 "" ++4 "" ++5 "" ++6 "" +@End Analysis +@Analysis: 1 0 ++2 0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 2 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 3 0 ++0 0 0 ++0 "" ++1 "" ++2 "" +@End Analysis +@Analysis: 4 0 ++0 0 1 0 0 0 0 0 0 0 1 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +LoadFile 0 "" +SaveFile 0 "" +@End Analysis +@Analysis: 5 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 6 0 ++1 ++0 "" +@End Analysis +@Analysis: 7 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 8 0 ++0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 9 0 ++0 "" +@End Analysis +@Analysis: 10 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 11 1 ++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 +@End Analysis +@Analysis: 12 0 ++2236960 0 +@End Analysis +@Analysis: 13 1 ++0 1 1 0 +@End Analysis +@Analysis: 14 1 ++1 1 1 "*" +@End Analysis +@Analysis: 15 0 +@End Analysis +@Analysis: 16 0 ++0 "0" ++1 "0" ++2 "chkpt_default, , ," +@End Analysis +@Analysis: 17 0 ++0 "-1" ++1 "" ++2 "-1" ++3 "-1" ++4 "1" +@End Analysis diff --git a/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2/ExpSim2-2.1OP b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2/ExpSim2-2.1OP new file mode 100644 index 0000000..e8574e2 Binary files /dev/null and b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2/ExpSim2-2.1OP differ diff --git a/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2/ExpSim2-2.cir b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2/ExpSim2-2.cir new file mode 100644 index 0000000..8fa23cf --- /dev/null +++ b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2/ExpSim2-2.cir @@ -0,0 +1,18 @@ +** Profile: "SCHEMATIC1-ExpSim2-2" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-2\circuitexp2-2-pspicefiles\schematic1\expsim2-2.sim ] + +** Creating circuit file "ExpSim2-2.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.TRAN 0 10ms 0 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + +.END diff --git a/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2/ExpSim2-2.mrk b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2/ExpSim2-2.mrk new file mode 100644 index 0000000..a1c2448 Binary files /dev/null and b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2/ExpSim2-2.mrk differ diff --git a/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2/ExpSim2-2.out b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2/ExpSim2-2.out new file mode 100644 index 0000000..bd9dd7a --- /dev/null +++ b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/ExpSim2-2/ExpSim2-2.out @@ -0,0 +1,89 @@ + +**** 09/27/24 10:56:22 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim2-2" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-2\circuitexp2-2-pspicefiles\schematic1\expsim2-2.sim + + + **** CIRCUIT DESCRIPTION + + +****************************************************************************** + + + + +** Creating circuit file "ExpSim2-2.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.TRAN 0 10ms 0 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + + +**** INCLUDING SCHEMATIC1.net **** +* source CIRCUITEXP2-2 +I_I1 0 N00144 DC 0.3Adc +X_H1 N00144 0 N00156 0 SCHEMATIC1_H1 +R_R1 0 N00156 9k TC=0,0 + +.subckt SCHEMATIC1_H1 1 2 3 4 +H_H1 3 4 VH_H1 10 +VH_H1 1 2 0V +.ends SCHEMATIC1_H1 + +**** RESUMING ExpSim2-2.cir **** +.END + +**** 09/27/24 10:56:22 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim2-2" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-2\circuitexp2-2-pspicefiles\schematic1\expsim2-2.sim + + + **** INITIAL TRANSIENT SOLUTION TEMPERATURE = 27.000 DEG C + + +****************************************************************************** + + + + NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE + + +(N00144) 0.0000 (N00156) 3.0000 + + + + + VOLTAGE SOURCE CURRENTS + NAME CURRENT + + X_H1.VH_H1 3.000E-01 + + TOTAL POWER DISSIPATION 0.00E+00 WATTS + + + + JOB CONCLUDED + +**** 09/27/24 10:56:22 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim2-2" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-2\circuitexp2-2-pspicefiles\schematic1\expsim2-2.sim + + + **** JOB STATISTICS SUMMARY + + +****************************************************************************** + + + + Total job time (using Solver 1) = 0.00 + \ No newline at end of file diff --git a/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS new file mode 100644 index 0000000..abce036 --- /dev/null +++ b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS @@ -0,0 +1,5 @@ +.ALIASES +I_I1 I1(+=0 -=N00144 ) CN @CIRCUITEXP2-2.SCHEMATIC1(sch_1):INS26@SOURCE.IDC.Normal(chips) +X_H1 H1(1=N00144 2=0 3=N00156 4=0 ) CN @CIRCUITEXP2-2.SCHEMATIC1(sch_1):INS57@ANALOG.H.Normal(chips) +R_R1 R1(1=0 2=N00156 ) CN @CIRCUITEXP2-2.SCHEMATIC1(sch_1):INS90@ANALOG.R.Normal(chips) +.ENDALIASES diff --git a/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net new file mode 100644 index 0000000..d33d470 --- /dev/null +++ b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net @@ -0,0 +1,9 @@ +* source CIRCUITEXP2-2 +I_I1 0 N00144 DC 0.3Adc +X_H1 N00144 0 N00156 0 SCHEMATIC1_H1 +R_R1 0 N00156 9k TC=0,0 + +.subckt SCHEMATIC1_H1 1 2 3 4 +H_H1 3 4 VH_H1 10 +VH_H1 1 2 0V +.ends SCHEMATIC1_H1 diff --git a/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp new file mode 100644 index 0000000..a4616c9 --- /dev/null +++ b/CircuitExp2/2-2/CircuitExp2-2-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp @@ -0,0 +1,30 @@ +("FILE_TYPE" "PMAP File" + ("devices" + ("IDC") + ("R") + ) + ("instances" + ("I1" + ("device_name" "IDC") + ("pspice_path" "I_I1") + ("level" "0") + ("model_params" + ("DC" + ("value" "0.3Adc") + ("pspice_param" "DC") + ) + ) + ) + ("R1" + ("device_name" "R") + ("pspice_path" "R_R1") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "9k") + ("pspice_param" "VALUE") + ) + ) + ) + ) +) diff --git a/CircuitExp2/2-2/CircuitExp2-2.opj b/CircuitExp2/2-2/CircuitExp2-2.opj new file mode 100644 index 0000000..85a7909 --- /dev/null +++ b/CircuitExp2/2-2/CircuitExp2-2.opj @@ -0,0 +1,60 @@ +(ExpressProject "CircuitExp2-2" + (ProjectVersion "19981106") + (ProjectType "Analog or A/D Mixed Mode") + (Folder "Design Resources" + (Folder "Library") + (NoModify) + (File ".\circuitexp2-2.dsn" + (Type "Schematic Design")) + (BuildFileAddedOrDeleted "x") + (CompileFileAddedOrDeleted "x") + (PSPICE_Regenerate_Netlist_Flag "FALSE")) + (Folder "Outputs" + (File ".\circuitexp2-2-pspicefiles\schematic1\schematic1.net" + (Type "Report"))) + (Folder "PSpice Resources" + (Folder "Simulation Profiles" + (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91} + ".\circuitexp2-2-pspicefiles\schematic1\expsim2-2-summary.sim" + (DisplayName "SCHEMATIC1-ExpSim2-2-summary") + (Type "PSpice Profile")) + (ActiveProfile ".\circuitexp2-2-pspicefiles\schematic1\expsim2-2.sim") + (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91} + ".\circuitexp2-2-pspicefiles\schematic1\expsim2-2.sim" + (DisplayName "SCHEMATIC1-ExpSim2-2") + (Type "PSpice Profile"))) + (Folder "Model Libraries" + (Sort User)) + (Folder "Stimulus Files" + (Sort User)) + (Folder "Include Files" + (Sort User))) + (DefaultLibraryBrowseDirectory "library\PSpice") + (PartMRUSelector) + (GlobalState + (FileView + (Path "Design Resources") + (Path "Design Resources" + "F:\Schoolwork\AnalogCircuit\CircuitExp2\2-2\circuitexp2-2.dsn") + (Path "Design Resources" + "F:\Schoolwork\AnalogCircuit\CircuitExp2\2-2\circuitexp2-2.dsn" + "SCHEMATIC1") + (Path "Outputs") + (Path "PSpice Resources") + (Path "PSpice Resources" "Simulation Profiles")) + (HierarchyView) + (Doc + (Type "COrCapturePMDoc") + (Frame + (Placement "44 2 3 -1 -1 -8 -31 0 200 0 430")) + (Tab 0)) + (Doc + (Type "COrSchematicDoc") + (Frame + (Placement "44 0 1 -1 -1 -8 -31 52 1471 52 521") + (Scroll "353 316") + (Zoom "400") + (Occurrence "/")) + (Path "F:\SCHOOLWORK\ANALOGCIRCUIT\CIRCUITEXP2\2-2\CIRCUITEXP2-2.DSN") + (Schematic "SCHEMATIC1") + (Page "PAGE1")))) diff --git a/CircuitExp2/2-2/ExpSim2-2-summary.pdf b/CircuitExp2/2-2/ExpSim2-2-summary.pdf new file mode 100644 index 0000000..e532d89 Binary files /dev/null and b/CircuitExp2/2-2/ExpSim2-2-summary.pdf differ diff --git a/CircuitExp2/2-2/SCHEMATIC1 _ PAGE1.pdf b/CircuitExp2/2-2/SCHEMATIC1 _ PAGE1.pdf new file mode 100644 index 0000000..c09e97b Binary files /dev/null and b/CircuitExp2/2-2/SCHEMATIC1 _ PAGE1.pdf differ diff --git a/CircuitExp2/2-2/output2_1.pdf b/CircuitExp2/2-2/output2_1.pdf new file mode 100644 index 0000000..941489f Binary files /dev/null and b/CircuitExp2/2-2/output2_1.pdf differ diff --git a/CircuitExp2/2-2/output2_2.pdf b/CircuitExp2/2-2/output2_2.pdf new file mode 100644 index 0000000..205ff81 Binary files /dev/null and b/CircuitExp2/2-2/output2_2.pdf differ diff --git a/CircuitExp2/2-2/output2_3.pdf b/CircuitExp2/2-2/output2_3.pdf new file mode 100644 index 0000000..8d6ce5c Binary files /dev/null and b/CircuitExp2/2-2/output2_3.pdf differ diff --git a/CircuitExp2/2-2/output2_4.pdf b/CircuitExp2/2-2/output2_4.pdf new file mode 100644 index 0000000..719f707 Binary files /dev/null and b/CircuitExp2/2-2/output2_4.pdf differ diff --git a/CircuitExp2/2-2/output2_5.pdf b/CircuitExp2/2-2/output2_5.pdf new file mode 100644 index 0000000..0277d81 Binary files /dev/null and b/CircuitExp2/2-2/output2_5.pdf differ diff --git a/CircuitExp2/2-2/output2_6.pdf b/CircuitExp2/2-2/output2_6.pdf new file mode 100644 index 0000000..e29e06e Binary files /dev/null and b/CircuitExp2/2-2/output2_6.pdf differ diff --git a/CircuitExp2/2-2/output2_7.pdf b/CircuitExp2/2-2/output2_7.pdf new file mode 100644 index 0000000..2816145 Binary files /dev/null and b/CircuitExp2/2-2/output2_7.pdf differ diff --git a/CircuitExp2/2-2/output2_8.pdf b/CircuitExp2/2-2/output2_8.pdf new file mode 100644 index 0000000..ed7f7f1 Binary files /dev/null and b/CircuitExp2/2-2/output2_8.pdf differ diff --git a/CircuitExp2/2-2/output_1.pdf b/CircuitExp2/2-2/output_1.pdf new file mode 100644 index 0000000..da9a4dc Binary files /dev/null and b/CircuitExp2/2-2/output_1.pdf differ diff --git a/CircuitExp2/2-2/output_2.pdf b/CircuitExp2/2-2/output_2.pdf new file mode 100644 index 0000000..b326a1d Binary files /dev/null and b/CircuitExp2/2-2/output_2.pdf differ diff --git a/CircuitExp2/2-2/output_3.pdf b/CircuitExp2/2-2/output_3.pdf new file mode 100644 index 0000000..e97eb5c Binary files /dev/null and b/CircuitExp2/2-2/output_3.pdf differ diff --git a/CircuitExp2/2-2/output_4.pdf b/CircuitExp2/2-2/output_4.pdf new file mode 100644 index 0000000..838d2c6 Binary files /dev/null and b/CircuitExp2/2-2/output_4.pdf differ diff --git a/CircuitExp2/2-2/output_5.pdf b/CircuitExp2/2-2/output_5.pdf new file mode 100644 index 0000000..5d879c2 Binary files /dev/null and b/CircuitExp2/2-2/output_5.pdf differ diff --git a/CircuitExp2/2-2/output_6.pdf b/CircuitExp2/2-2/output_6.pdf new file mode 100644 index 0000000..36a2c85 Binary files /dev/null and b/CircuitExp2/2-2/output_6.pdf differ diff --git a/CircuitExp2/2-2/output_7.pdf b/CircuitExp2/2-2/output_7.pdf new file mode 100644 index 0000000..adcd98d Binary files /dev/null and b/CircuitExp2/2-2/output_7.pdf differ diff --git a/CircuitExp2/2-3/CIRCUITEXP2-3.DSN b/CircuitExp2/2-3/CIRCUITEXP2-3.DSN new file mode 100644 index 0000000..71d9d3a Binary files /dev/null and b/CircuitExp2/2-3/CIRCUITEXP2-3.DSN differ diff --git a/CircuitExp2/2-3/CIRCUITEXP2-3_0.DBK b/CircuitExp2/2-3/CIRCUITEXP2-3_0.DBK new file mode 100644 index 0000000..8c69036 Binary files /dev/null and b/CircuitExp2/2-3/CIRCUITEXP2-3_0.DBK differ diff --git a/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim-2-3(2).sim b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim-2-3(2).sim new file mode 100644 index 0000000..d95ccff --- /dev/null +++ b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim-2-3(2).sim @@ -0,0 +1,137 @@ +@OrCAD Simulation Server Version: 1.0 + +@Settings: 0 1 +@General: +ProfileName= "ExpSim-2-3(2)" +ProfileFile= "ExpSim-2-3(2).sim" +Connectivity= "SCHEMATIC1.net" +NetlistFile= "ExpSim-2-3(2).cir" +DataFile= "ExpSim-2-3(2).dat" +OutFile= "ExpSim-2-3(2).out" +Notes= +@#$BEGINNOTES +@#$ENDNOTES +@End General +@Analysis: 0 1 ++0 0 0 0 ++0 "10ms" ++1 "" ++2 "0" ++3 "" ++4 "" ++5 "" ++6 "" +@End Analysis +@Analysis: 1 0 ++2 0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 2 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 3 0 ++0 0 0 ++0 "" ++1 "" ++2 "" +@End Analysis +@Analysis: 4 0 ++0 0 1 0 0 0 0 0 0 0 1 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +LoadFile 0 "" +SaveFile 0 "" +@End Analysis +@Analysis: 5 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 6 0 ++1 ++0 "" +@End Analysis +@Analysis: 7 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 8 0 ++0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 9 0 ++0 "" +@End Analysis +@Analysis: 10 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 11 1 ++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 +@End Analysis +@Analysis: 12 0 ++2236960 0 +@End Analysis +@Analysis: 13 1 ++0 1 1 0 +@End Analysis +@Analysis: 14 1 ++1 1 1 "*" +@End Analysis +@Analysis: 15 0 +@End Analysis +@Analysis: 16 0 ++0 "0" ++1 "0" ++2 "chkpt_default, , ," +@End Analysis +@Analysis: 17 0 ++0 "-1" ++1 "" ++2 "-1" ++3 "-1" ++4 "1" +@End Analysis diff --git a/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim-2-3(2)/ExpSim-2-3(2).1OP b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim-2-3(2)/ExpSim-2-3(2).1OP new file mode 100644 index 0000000..f9dcf59 Binary files /dev/null and b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim-2-3(2)/ExpSim-2-3(2).1OP differ diff --git a/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim-2-3(2)/ExpSim-2-3(2).cir b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim-2-3(2)/ExpSim-2-3(2).cir new file mode 100644 index 0000000..f1c4603 --- /dev/null +++ b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim-2-3(2)/ExpSim-2-3(2).cir @@ -0,0 +1,18 @@ +** Profile: "SCHEMATIC1-ExpSim-2-3(2)" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-3\CircuitExp2-3-PSpiceFiles\SCHEMATIC1\ExpSim-2-3(2).sim ] + +** Creating circuit file "ExpSim-2-3(2).cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.TRAN 0 10ms 0 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + +.END diff --git a/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim-2-3(2)/ExpSim-2-3(2).mrk b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim-2-3(2)/ExpSim-2-3(2).mrk new file mode 100644 index 0000000..a1c2448 Binary files /dev/null and b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim-2-3(2)/ExpSim-2-3(2).mrk differ diff --git a/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim-2-3(2)/ExpSim-2-3(2).out b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim-2-3(2)/ExpSim-2-3(2).out new file mode 100644 index 0000000..e2d1f34 --- /dev/null +++ b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim-2-3(2)/ExpSim-2-3(2).out @@ -0,0 +1,84 @@ + +**** 09/27/24 11:33:16 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim-2-3(2)" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-3\CircuitExp2-3-PSpiceFiles\SCHEMATIC1\ExpSim-2- + + + **** CIRCUIT DESCRIPTION + + +****************************************************************************** + + + + +** Creating circuit file "ExpSim-2-3(2).cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.TRAN 0 10ms 0 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + + +**** INCLUDING SCHEMATIC1.net **** +* source CIRCUITEXP2-3 +V_V1 N00134 0 1Vdc +E_E1 N00146 0 N00134 0 2 +R_R1 0 N00146 9k TC=0,0 + +**** RESUMING ExpSim-2-3(2).cir **** +.END + +**** 09/27/24 11:33:16 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim-2-3(2)" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-3\CircuitExp2-3-PSpiceFiles\SCHEMATIC1\ExpSim-2- + + + **** INITIAL TRANSIENT SOLUTION TEMPERATURE = 27.000 DEG C + + +****************************************************************************** + + + + NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE + + +(N00134) 1.0000 (N00146) 2.0000 + + + + + VOLTAGE SOURCE CURRENTS + NAME CURRENT + + V_V1 0.000E+00 + + TOTAL POWER DISSIPATION 0.00E+00 WATTS + + + + JOB CONCLUDED + +**** 09/27/24 11:33:16 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim-2-3(2)" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-3\CircuitExp2-3-PSpiceFiles\SCHEMATIC1\ExpSim-2- + + + **** JOB STATISTICS SUMMARY + + +****************************************************************************** + + + + Total job time (using Solver 1) = 0.00 + \ No newline at end of file diff --git a/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim3-3.sim b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim3-3.sim new file mode 100644 index 0000000..f85adfe --- /dev/null +++ b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim3-3.sim @@ -0,0 +1,137 @@ +@OrCAD Simulation Server Version: 1.0 + +@Settings: 1 1 +@General: +ProfileName= "ExpSim3-3" +ProfileFile= "ExpSim3-3.sim" +Connectivity= "SCHEMATIC1.net" +NetlistFile= "ExpSim3-3.cir" +DataFile= "ExpSim3-3.dat" +OutFile= "ExpSim3-3.out" +Notes= +@#$BEGINNOTES +@#$ENDNOTES +@End General +@Analysis: 0 0 ++0 0 0 0 ++0 "1000ns" ++1 "" ++2 "0" ++3 "" ++4 "" ++5 "" ++6 "" +@End Analysis +@Analysis: 1 0 ++2 0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 2 1 ++0 0 ++0 "V1" ++1 "" ++2 "" ++3 "" ++4 "0" ++5 "4" ++6 "0.5" ++7 "" +@End Analysis +@Analysis: 3 0 ++0 0 0 ++0 "" ++1 "" ++2 "" +@End Analysis +@Analysis: 4 0 ++0 0 1 0 0 0 1 0 0 0 1 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +LoadFile 0 "" +SaveFile 0 "" +@End Analysis +@Analysis: 5 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 6 0 ++1 ++0 "" +@End Analysis +@Analysis: 7 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 8 0 ++0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 9 0 ++0 "" +@End Analysis +@Analysis: 10 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 11 1 ++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 +@End Analysis +@Analysis: 12 0 ++2236960 0 +@End Analysis +@Analysis: 13 1 ++0 1 1 0 +@End Analysis +@Analysis: 14 1 ++1 1 1 "*" +@End Analysis +@Analysis: 15 0 +@End Analysis +@Analysis: 16 0 ++0 "0" ++1 "0" ++2 "chkpt_default, , ," +@End Analysis +@Analysis: 17 0 ++0 "-1" ++1 "" ++2 "-1" ++3 "-1" ++4 "1" +@End Analysis diff --git a/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim3-3/ExpSim3-3.cir b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim3-3/ExpSim3-3.cir new file mode 100644 index 0000000..3cefe80 --- /dev/null +++ b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim3-3/ExpSim3-3.cir @@ -0,0 +1,18 @@ +** Profile: "SCHEMATIC1-ExpSim3-3" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-3\CircuitExp2-3-PSpiceFiles\SCHEMATIC1\ExpSim3-3.sim ] + +** Creating circuit file "ExpSim3-3.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.DC LIN V_V1 0 4 0.5 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + +.END diff --git a/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim3-3/ExpSim3-3.mrk b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim3-3/ExpSim3-3.mrk new file mode 100644 index 0000000..e51cf99 Binary files /dev/null and b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim3-3/ExpSim3-3.mrk differ diff --git a/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim3-3/ExpSim3-3.out b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim3-3/ExpSim3-3.out new file mode 100644 index 0000000..676e30f --- /dev/null +++ b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim3-3/ExpSim3-3.out @@ -0,0 +1,56 @@ + +**** 09/27/24 11:14:19 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim3-3" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-3\CircuitExp2-3-PSpiceFiles\SCHEMATIC1\ExpSim3-3.sim + + + **** CIRCUIT DESCRIPTION + + +****************************************************************************** + + + + +** Creating circuit file "ExpSim3-3.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.DC LIN V_V1 0 4 0.5 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + + +**** INCLUDING SCHEMATIC1.net **** +* source CIRCUITEXP2-3 +V_V1 N00134 0 1Vdc +E_E1 N00146 0 N00134 0 2 +R_R1 0 N00146 1k TC=0,0 + +**** RESUMING ExpSim3-3.cir **** +.END + + + JOB CONCLUDED + +**** 09/27/24 11:14:19 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim3-3" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-3\CircuitExp2-3-PSpiceFiles\SCHEMATIC1\ExpSim3-3.sim + + + **** JOB STATISTICS SUMMARY + + +****************************************************************************** + + + + Total job time (using Solver 1) = 0.00 + \ No newline at end of file diff --git a/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim3-3/ExpSim3-3.prb b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim3-3/ExpSim3-3.prb new file mode 100644 index 0000000..e4076bc --- /dev/null +++ b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/ExpSim3-3/ExpSim3-3.prb @@ -0,0 +1,54 @@ +[DISPLAYS] +BEGIN DISPLAY LAST SESSION +ANALYSIS DC_SWEEP +SYMBOL ALWAYS +TRACECOLORSCHEME NORMAL +BEGIN ANAPLOT 1 +ACTIVE +XBASE +BEGIN XAXIS +XAXISUSERNAME 0 (null) +RANGEFLAG AUTO +TYPE LINEAR +UNIT V +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +END XAXIS +BEGIN YAXIS 1 +YAXISSIDE LEFT +ACTIVE +RANGEFLAG AUTO +TYPE LINEAR +UNIT V +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +BEGIN TRACE V(R1:2) +MARKERID 1 +END TRACE V(R1:2) +BEGIN LABEL +TYPE TEXT +TEXT 鐗╄仈缃234_2330110900_寮犻【鐨 +LABELTEXTSIZE 12 +LABELTEXTTYPE 0 +LABELTEXTFONT Arial +LABELTEXTCOLOR 0 +LABELTEXTSCRIPT 0 +STARTX 1.2139175257732 +STARTY 5.41414141414141 +COLOR 7 +END LABEL +END YAXIS 1 +END ANAPLOT 1 +END DISPLAY LAST SESSION diff --git a/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS new file mode 100644 index 0000000..313962b --- /dev/null +++ b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS @@ -0,0 +1,5 @@ +.ALIASES +V_V1 V1(+=N00134 -=0 ) CN @CIRCUITEXP2-3.SCHEMATIC1(sch_1):INS26@SOURCE.VDC.Normal(chips) +E_E1 E1(3=N00146 4=0 1=N00134 2=0 ) CN @CIRCUITEXP2-3.SCHEMATIC1(sch_1):INS57@ANALOG.E.Normal(chips) +R_R1 R1(1=0 2=N00146 ) CN @CIRCUITEXP2-3.SCHEMATIC1(sch_1):INS90@ANALOG.R.Normal(chips) +.ENDALIASES diff --git a/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net new file mode 100644 index 0000000..d718c00 --- /dev/null +++ b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net @@ -0,0 +1,4 @@ +* source CIRCUITEXP2-3 +V_V1 N00134 0 1Vdc +E_E1 N00146 0 N00134 0 2 +R_R1 0 N00146 9k TC=0,0 diff --git a/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp new file mode 100644 index 0000000..b7085f8 --- /dev/null +++ b/CircuitExp2/2-3/CircuitExp2-3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp @@ -0,0 +1,30 @@ +("FILE_TYPE" "PMAP File" + ("devices" + ("VDC") + ("R") + ) + ("instances" + ("V1" + ("device_name" "VDC") + ("pspice_path" "V_V1") + ("level" "0") + ("model_params" + ("DC" + ("value" "1Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("R1" + ("device_name" "R") + ("pspice_path" "R_R1") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "9k") + ("pspice_param" "VALUE") + ) + ) + ) + ) +) diff --git a/CircuitExp2/2-3/CircuitExp2-3.opj b/CircuitExp2/2-3/CircuitExp2-3.opj new file mode 100644 index 0000000..44ac5d9 --- /dev/null +++ b/CircuitExp2/2-3/CircuitExp2-3.opj @@ -0,0 +1,71 @@ +(ExpressProject "CircuitExp2-3" + (ProjectVersion "19981106") + (ProjectType "Analog or A/D Mixed Mode") + (Folder "Design Resources" + (Folder "Library") + (NoModify) + (File ".\circuitexp2-3.dsn" + (Type "Schematic Design")) + (BuildFileAddedOrDeleted "x") + (CompileFileAddedOrDeleted "x") + (PSPICE_Regenerate_Netlist_Flag "FALSE")) + (Folder "Outputs" + (File ".\circuitexp2-3-pspicefiles\schematic1\schematic1.net" + (Type "Report"))) + (Folder "PSpice Resources" + (Folder "Simulation Profiles" + (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91} + ".\circuitexp2-3-pspicefiles\schematic1\expsim3-3.sim" + (DisplayName "SCHEMATIC1-ExpSim3-3") + (Type "PSpice Profile")) + (ActiveProfile ".\circuitexp2-3-pspicefiles\schematic1\expsim-2-3(2).sim") + (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91} + ".\circuitexp2-3-pspicefiles\schematic1\expsim-2-3(2).sim" + (DisplayName "SCHEMATIC1-ExpSim-2-3(2)") + (Type "PSpice Profile"))) + (Folder "Model Libraries" + (Sort User)) + (Folder "Stimulus Files" + (Sort User)) + (Folder "Include Files" + (Sort User))) + (DefaultLibraryBrowseDirectory "library\PSpice") + (PartMRUSelector + (0 + (LibraryName "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB") + (DeviceIndex "0")) + (R + (FullPartName "R.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\ANALOG.OLB") + (DeviceIndex "0")) + (E + (FullPartName "E.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\ANALOG.OLB") + (DeviceIndex "0")) + (VDC + (FullPartName "VDC.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\SOURCE.OLB") + (DeviceIndex "0"))) + (GlobalState + (FileView + (Path "Design Resources") + (Path "Outputs")) + (HierarchyView) + (Doc + (Type "COrCapturePMDoc") + (Frame + (Placement "44 0 1 -1 -1 -8 -31 0 200 0 430")) + (Tab 0)) + (Doc + (Type "COrSchematicDoc") + (Frame + (Placement "44 0 1 -1 -1 -8 -31 130 1514 130 599") + (Scroll "1210 985") + (Zoom "400") + (Occurrence "/")) + (Path "F:\SCHOOLWORK\ANALOGCIRCUIT\CIRCUITEXP2\2-3\CIRCUITEXP2-3.DSN") + (Schematic "SCHEMATIC1") + (Page "PAGE1")))) diff --git a/CircuitExp2/2-3/ExpSim2-3.pdf b/CircuitExp2/2-3/ExpSim2-3.pdf new file mode 100644 index 0000000..8294ea6 Binary files /dev/null and b/CircuitExp2/2-3/ExpSim2-3.pdf differ diff --git a/CircuitExp2/2-3/SCHEMATIC1 _ PAGE1.pdf b/CircuitExp2/2-3/SCHEMATIC1 _ PAGE1.pdf new file mode 100644 index 0000000..29e8ad1 Binary files /dev/null and b/CircuitExp2/2-3/SCHEMATIC1 _ PAGE1.pdf differ diff --git a/CircuitExp2/2-3/output_1.pdf b/CircuitExp2/2-3/output_1.pdf new file mode 100644 index 0000000..643d8f9 Binary files /dev/null and b/CircuitExp2/2-3/output_1.pdf differ diff --git a/CircuitExp2/2-3/output_2.pdf b/CircuitExp2/2-3/output_2.pdf new file mode 100644 index 0000000..509de3c Binary files /dev/null and b/CircuitExp2/2-3/output_2.pdf differ diff --git a/CircuitExp2/2-3/output_3.pdf b/CircuitExp2/2-3/output_3.pdf new file mode 100644 index 0000000..683b8d3 Binary files /dev/null and b/CircuitExp2/2-3/output_3.pdf differ diff --git a/CircuitExp2/2-3/output_4.pdf b/CircuitExp2/2-3/output_4.pdf new file mode 100644 index 0000000..efd46c0 Binary files /dev/null and b/CircuitExp2/2-3/output_4.pdf differ diff --git a/CircuitExp2/2-3/output_5.pdf b/CircuitExp2/2-3/output_5.pdf new file mode 100644 index 0000000..44d01c7 Binary files /dev/null and b/CircuitExp2/2-3/output_5.pdf differ diff --git a/CircuitExp2/2-3/output_6.pdf b/CircuitExp2/2-3/output_6.pdf new file mode 100644 index 0000000..82b1252 Binary files /dev/null and b/CircuitExp2/2-3/output_6.pdf differ diff --git a/CircuitExp2/2-3/output_7.pdf b/CircuitExp2/2-3/output_7.pdf new file mode 100644 index 0000000..b413f55 Binary files /dev/null and b/CircuitExp2/2-3/output_7.pdf differ diff --git a/CircuitExp2/2-3/output_8.pdf b/CircuitExp2/2-3/output_8.pdf new file mode 100644 index 0000000..42295b9 Binary files /dev/null and b/CircuitExp2/2-3/output_8.pdf differ diff --git a/CircuitExp2/2-3/output_9.pdf b/CircuitExp2/2-3/output_9.pdf new file mode 100644 index 0000000..42a4155 Binary files /dev/null and b/CircuitExp2/2-3/output_9.pdf differ diff --git a/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim-2-4.sim b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim-2-4.sim new file mode 100644 index 0000000..95750b3 --- /dev/null +++ b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim-2-4.sim @@ -0,0 +1,137 @@ +@OrCAD Simulation Server Version: 1.0 + +@Settings: 1 1 +@General: +ProfileName= "ExpSim-2-4" +ProfileFile= "ExpSim-2-4.sim" +Connectivity= "SCHEMATIC1.net" +NetlistFile= "ExpSim-2-4.cir" +DataFile= "ExpSim-2-4.dat" +OutFile= "ExpSim-2-4.out" +Notes= +@#$BEGINNOTES +@#$ENDNOTES +@End General +@Analysis: 0 0 ++0 0 0 0 ++0 "1000ns" ++1 "" ++2 "0" ++3 "" ++4 "" ++5 "" ++6 "" +@End Analysis +@Analysis: 1 0 ++2 0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 2 1 ++0 1 ++0 "I1" ++1 "" ++2 "" ++3 "" ++4 "0.0001" ++5 "0.0004" ++6 "0.00001" ++7 "" +@End Analysis +@Analysis: 3 0 ++0 0 0 ++0 "" ++1 "" ++2 "" +@End Analysis +@Analysis: 4 0 ++0 0 1 0 0 0 1 0 0 0 1 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +LoadFile 0 "" +SaveFile 0 "" +@End Analysis +@Analysis: 5 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 6 0 ++1 ++0 "" +@End Analysis +@Analysis: 7 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 8 0 ++0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 9 0 ++0 "" +@End Analysis +@Analysis: 10 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 11 1 ++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 +@End Analysis +@Analysis: 12 0 ++2236960 0 +@End Analysis +@Analysis: 13 1 ++0 1 1 0 +@End Analysis +@Analysis: 14 1 ++1 1 1 "*" +@End Analysis +@Analysis: 15 0 +@End Analysis +@Analysis: 16 0 ++0 "0" ++1 "0" ++2 "chkpt_default, , ," +@End Analysis +@Analysis: 17 0 ++0 "-1" ++1 "" ++2 "-1" ++3 "-1" ++4 "1" +@End Analysis diff --git a/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim-2-4/ExpSim-2-4.cir b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim-2-4/ExpSim-2-4.cir new file mode 100644 index 0000000..da00663 --- /dev/null +++ b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim-2-4/ExpSim-2-4.cir @@ -0,0 +1,18 @@ +** Profile: "SCHEMATIC1-ExpSim-2-4" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-4\2-4-PSpiceFiles\SCHEMATIC1\ExpSim-2-4.sim ] + +** Creating circuit file "ExpSim-2-4.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.DC LIN I_I1 0.0001 0.0004 0.00001 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + +.END diff --git a/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim-2-4/ExpSim-2-4.mrk b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim-2-4/ExpSim-2-4.mrk new file mode 100644 index 0000000..6968e20 Binary files /dev/null and b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim-2-4/ExpSim-2-4.mrk differ diff --git a/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim-2-4/ExpSim-2-4.out b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim-2-4/ExpSim-2-4.out new file mode 100644 index 0000000..fbec6f1 --- /dev/null +++ b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim-2-4/ExpSim-2-4.out @@ -0,0 +1,61 @@ + +**** 09/27/24 11:41:37 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim-2-4" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-4\2-4-PSpiceFiles\SCHEMATIC1\ExpSim-2-4.sim ] + + + **** CIRCUIT DESCRIPTION + + +****************************************************************************** + + + + +** Creating circuit file "ExpSim-2-4.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.DC LIN I_I1 0.0001 0.0004 0.00001 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + + +**** INCLUDING SCHEMATIC1.net **** +* source 2-4 +I_I1 0 N00130 DC 0.1Adc +X_F1 N00130 0 N00142 0 SCHEMATIC1_F1 +R_R1 0 N00142 1k TC=0,0 + +.subckt SCHEMATIC1_F1 1 2 3 4 +F_F1 3 4 VF_F1 3 +VF_F1 1 2 0V +.ends SCHEMATIC1_F1 + +**** RESUMING ExpSim-2-4.cir **** +.END + + + JOB CONCLUDED + +**** 09/27/24 11:41:37 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim-2-4" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-4\2-4-PSpiceFiles\SCHEMATIC1\ExpSim-2-4.sim ] + + + **** JOB STATISTICS SUMMARY + + +****************************************************************************** + + + + Total job time (using Solver 1) = 0.00 + \ No newline at end of file diff --git a/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim-2-4/ExpSim-2-4.prb b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim-2-4/ExpSim-2-4.prb new file mode 100644 index 0000000..148de1c --- /dev/null +++ b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim-2-4/ExpSim-2-4.prb @@ -0,0 +1,62 @@ +[DISPLAYS] +BEGIN DISPLAY LAST SESSION +ANALYSIS DC_SWEEP +SYMBOL ALWAYS +TRACECOLORSCHEME NORMAL +BEGIN ANAPLOT 1 +ACTIVE +XBASE +BEGIN XAXIS +XAXISUSERNAME 0 User Defined Title +RANGEFLAG MANUAL +TYPE LINEAR +UNIT A +BEGIN GRIDS +AUTOMATIC +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +REFMIN 9.99999999999998e-005 +REFMAX 0.0004 +REFUNIT A +END XAXIS +BEGIN YAXIS 1 +YAXISSIDE LEFT +ACTIVE +RANGEFLAG MANUAL +TYPE LINEAR +UNIT A +BEGIN GRIDS +MAJORSPACINGLINEAR 0.0002 +MAJORSPACINGLOG 1 +MINORINTERVALS 2 +MAJORNUMBERS +MAJORSTYLE LINES +MAJORPATTERN SOLID +MINORSTYLE LINES +MINORPATTERN DOT +END GRIDS +REFMIN 0 +REFMAX 0.00120000005699694 +REFUNIT A +BEGIN TRACE I(R1:1) +MARKERID 1 +END TRACE I(R1:1) +BEGIN LABEL +TYPE TEXT +TEXT 鐗╄仈缃234_2330110900_寮犻【鐨 +LABELTEXTSIZE 12 +LABELTEXTTYPE 0 +LABELTEXTFONT Arial +LABELTEXTCOLOR 0 +LABELTEXTSCRIPT 0 +STARTX 0.000188385826771654 +STARTY 0.00107878787878788 +COLOR 7 +END LABEL +END YAXIS 1 +END ANAPLOT 1 +END DISPLAY LAST SESSION diff --git a/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim2-4(2).sim b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim2-4(2).sim new file mode 100644 index 0000000..9ffd809 --- /dev/null +++ b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim2-4(2).sim @@ -0,0 +1,137 @@ +@OrCAD Simulation Server Version: 1.0 + +@Settings: 0 1 +@General: +ProfileName= "ExpSim2-4(2)" +ProfileFile= "ExpSim2-4(2).sim" +Connectivity= "SCHEMATIC1.net" +NetlistFile= "ExpSim2-4(2).cir" +DataFile= "ExpSim2-4(2).dat" +OutFile= "ExpSim2-4(2).out" +Notes= +@#$BEGINNOTES +@#$ENDNOTES +@End General +@Analysis: 0 1 ++0 0 0 0 ++0 "10ms" ++1 "" ++2 "0" ++3 "" ++4 "" ++5 "" ++6 "" +@End Analysis +@Analysis: 1 0 ++2 0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 2 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 3 0 ++0 0 0 ++0 "" ++1 "" ++2 "" +@End Analysis +@Analysis: 4 0 ++0 0 1 0 0 0 0 0 0 0 1 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +LoadFile 0 "" +SaveFile 0 "" +@End Analysis +@Analysis: 5 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 6 0 ++1 ++0 "" +@End Analysis +@Analysis: 7 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 8 0 ++0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 9 0 ++0 "" +@End Analysis +@Analysis: 10 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 11 1 ++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 +@End Analysis +@Analysis: 12 0 ++2236960 0 +@End Analysis +@Analysis: 13 1 ++0 1 1 0 +@End Analysis +@Analysis: 14 1 ++1 1 1 "*" +@End Analysis +@Analysis: 15 0 +@End Analysis +@Analysis: 16 0 ++0 "0" ++1 "0" ++2 "chkpt_default, , ," +@End Analysis +@Analysis: 17 0 ++0 "-1" ++1 "" ++2 "-1" ++3 "-1" ++4 "1" +@End Analysis diff --git a/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim2-4(2)/ExpSim2-4(2).1OP b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim2-4(2)/ExpSim2-4(2).1OP new file mode 100644 index 0000000..5a2957e Binary files /dev/null and b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim2-4(2)/ExpSim2-4(2).1OP differ diff --git a/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim2-4(2)/ExpSim2-4(2).cir b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim2-4(2)/ExpSim2-4(2).cir new file mode 100644 index 0000000..7dca845 --- /dev/null +++ b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim2-4(2)/ExpSim2-4(2).cir @@ -0,0 +1,18 @@ +** Profile: "SCHEMATIC1-ExpSim2-4(2)" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-4\2-4-PSpiceFiles\SCHEMATIC1\ExpSim2-4(2).sim ] + +** Creating circuit file "ExpSim2-4(2).cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.TRAN 0 10ms 0 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + +.END diff --git a/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim2-4(2)/ExpSim2-4(2).mrk b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim2-4(2)/ExpSim2-4(2).mrk new file mode 100644 index 0000000..a1c2448 Binary files /dev/null and b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim2-4(2)/ExpSim2-4(2).mrk differ diff --git a/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim2-4(2)/ExpSim2-4(2).out b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim2-4(2)/ExpSim2-4(2).out new file mode 100644 index 0000000..e5a7cad --- /dev/null +++ b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/ExpSim2-4(2)/ExpSim2-4(2).out @@ -0,0 +1,89 @@ + +**** 09/27/24 11:50:36 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim2-4(2)" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-4\2-4-PSpiceFiles\SCHEMATIC1\ExpSim2-4(2).sim ] + + + **** CIRCUIT DESCRIPTION + + +****************************************************************************** + + + + +** Creating circuit file "ExpSim2-4(2).cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.TRAN 0 10ms 0 +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + + +**** INCLUDING SCHEMATIC1.net **** +* source 2-4 +I_I1 0 N00130 DC 0.3Adc +X_F1 N00130 0 N00142 0 SCHEMATIC1_F1 +R_R1 0 N00142 9k TC=0,0 + +.subckt SCHEMATIC1_F1 1 2 3 4 +F_F1 3 4 VF_F1 3 +VF_F1 1 2 0V +.ends SCHEMATIC1_F1 + +**** RESUMING ExpSim2-4(2).cir **** +.END + +**** 09/27/24 11:50:36 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim2-4(2)" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-4\2-4-PSpiceFiles\SCHEMATIC1\ExpSim2-4(2).sim ] + + + **** INITIAL TRANSIENT SOLUTION TEMPERATURE = 27.000 DEG C + + +****************************************************************************** + + + + NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE + + +(N00130) 0.0000 (N00142)-8100.0000 + + + + + VOLTAGE SOURCE CURRENTS + NAME CURRENT + + X_F1.VF_F1 3.000E-01 + + TOTAL POWER DISSIPATION 0.00E+00 WATTS + + + + JOB CONCLUDED + +**** 09/27/24 11:50:36 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim2-4(2)" [ F:\Schoolwork\AnalogCircuit\CircuitExp2\2-4\2-4-PSpiceFiles\SCHEMATIC1\ExpSim2-4(2).sim ] + + + **** JOB STATISTICS SUMMARY + + +****************************************************************************** + + + + Total job time (using Solver 1) = 0.00 + \ No newline at end of file diff --git a/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS new file mode 100644 index 0000000..7d46f41 --- /dev/null +++ b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS @@ -0,0 +1,5 @@ +.ALIASES +I_I1 I1(+=0 -=N00130 ) CN @2-4.SCHEMATIC1(sch_1):INS26@SOURCE.IDC.Normal(chips) +X_F1 F1(1=N00130 2=0 3=N00142 4=0 ) CN @2-4.SCHEMATIC1(sch_1):INS57@ANALOG.F.Normal(chips) +R_R1 R1(1=0 2=N00142 ) CN @2-4.SCHEMATIC1(sch_1):INS90@ANALOG.R.Normal(chips) +.ENDALIASES diff --git a/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net new file mode 100644 index 0000000..c0a1144 --- /dev/null +++ b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net @@ -0,0 +1,9 @@ +* source 2-4 +I_I1 0 N00130 DC 0.3Adc +X_F1 N00130 0 N00142 0 SCHEMATIC1_F1 +R_R1 0 N00142 9k TC=0,0 + +.subckt SCHEMATIC1_F1 1 2 3 4 +F_F1 3 4 VF_F1 3 +VF_F1 1 2 0V +.ends SCHEMATIC1_F1 diff --git a/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp new file mode 100644 index 0000000..a4616c9 --- /dev/null +++ b/CircuitExp2/2-4/2-4-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp @@ -0,0 +1,30 @@ +("FILE_TYPE" "PMAP File" + ("devices" + ("IDC") + ("R") + ) + ("instances" + ("I1" + ("device_name" "IDC") + ("pspice_path" "I_I1") + ("level" "0") + ("model_params" + ("DC" + ("value" "0.3Adc") + ("pspice_param" "DC") + ) + ) + ) + ("R1" + ("device_name" "R") + ("pspice_path" "R_R1") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "9k") + ("pspice_param" "VALUE") + ) + ) + ) + ) +) diff --git a/CircuitExp2/2-4/2-4.DSN b/CircuitExp2/2-4/2-4.DSN new file mode 100644 index 0000000..1520536 Binary files /dev/null and b/CircuitExp2/2-4/2-4.DSN differ diff --git a/CircuitExp2/2-4/2-4.opj b/CircuitExp2/2-4/2-4.opj new file mode 100644 index 0000000..17e5e5f --- /dev/null +++ b/CircuitExp2/2-4/2-4.opj @@ -0,0 +1,73 @@ +(ExpressProject "2-4" + (ProjectVersion "19981106") + (ProjectType "Analog or A/D Mixed Mode") + (Folder "Design Resources" + (Folder "Library") + (NoModify) + (File ".\2-4.dsn" + (Type "Schematic Design")) + (BuildFileAddedOrDeleted "x") + (CompileFileAddedOrDeleted "x") + (PSPICE_Regenerate_Netlist_Flag "FALSE")) + (Folder "Outputs" + (File ".\2-4-pspicefiles\schematic1\schematic1.net" + (Type "Report"))) + (Folder "PSpice Resources" + (Folder "Simulation Profiles" + (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91} + ".\2-4-pspicefiles\schematic1\expsim-2-4.sim" + (DisplayName "SCHEMATIC1-ExpSim-2-4") + (Type "PSpice Profile")) + (ActiveProfile ".\2-4-pspicefiles\schematic1\expsim2-4(2).sim") + (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91} + ".\2-4-pspicefiles\schematic1\expsim2-4(2).sim" + (DisplayName "SCHEMATIC1-ExpSim2-4(2)") + (Type "PSpice Profile"))) + (Folder "Model Libraries" + (Sort User)) + (Folder "Stimulus Files" + (Sort User)) + (Folder "Include Files" + (Sort User))) + (DefaultLibraryBrowseDirectory "library\PSpice") + (PartMRUSelector + (0 + (LibraryName "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB") + (DeviceIndex "0")) + (R + (FullPartName "R.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\ANALOG.OLB") + (DeviceIndex "0")) + (F + (FullPartName "F.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\ANALOG.OLB") + (DeviceIndex "0")) + (IDC + (FullPartName "IDC.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\SOURCE.OLB") + (DeviceIndex "0"))) + (GlobalState + (FileView + (Path "Design Resources") + (Path "Outputs") + (Path "PSpice Resources") + (Path "PSpice Resources" "Simulation Profiles")) + (HierarchyView) + (Doc + (Type "COrCapturePMDoc") + (Frame + (Placement "44 2 3 -1 -1 -8 -31 0 200 0 430")) + (Tab 0)) + (Doc + (Type "COrSchematicDoc") + (Frame + (Placement "44 0 1 -1 -1 -8 -31 182 1272 182 651") + (Scroll "1118 901") + (Zoom "400") + (Occurrence "/")) + (Path "F:\SCHOOLWORK\ANALOGCIRCUIT\CIRCUITEXP2\2-4\2-4.DSN") + (Schematic "SCHEMATIC1") + (Page "PAGE1")))) diff --git a/CircuitExp2/2-4/2-4_0.DBK b/CircuitExp2/2-4/2-4_0.DBK new file mode 100644 index 0000000..4b20187 Binary files /dev/null and b/CircuitExp2/2-4/2-4_0.DBK differ diff --git a/CircuitExp2/2-4/ExpSim-2-4.pdf b/CircuitExp2/2-4/ExpSim-2-4.pdf new file mode 100644 index 0000000..1379a5e Binary files /dev/null and b/CircuitExp2/2-4/ExpSim-2-4.pdf differ diff --git a/CircuitExp2/2-4/SCHEMATIC1 _ PAGE1.pdf b/CircuitExp2/2-4/SCHEMATIC1 _ PAGE1.pdf new file mode 100644 index 0000000..55eaa2d Binary files /dev/null and b/CircuitExp2/2-4/SCHEMATIC1 _ PAGE1.pdf differ diff --git a/CircuitExp2/2-4/output_1.pdf b/CircuitExp2/2-4/output_1.pdf new file mode 100644 index 0000000..5e77c7f Binary files /dev/null and b/CircuitExp2/2-4/output_1.pdf differ diff --git a/CircuitExp2/2-4/output_2.pdf b/CircuitExp2/2-4/output_2.pdf new file mode 100644 index 0000000..ddb7645 Binary files /dev/null and b/CircuitExp2/2-4/output_2.pdf differ diff --git a/CircuitExp2/2-4/output_3.pdf b/CircuitExp2/2-4/output_3.pdf new file mode 100644 index 0000000..b586e8f Binary files /dev/null and b/CircuitExp2/2-4/output_3.pdf differ diff --git a/CircuitExp2/2-4/output_4.pdf b/CircuitExp2/2-4/output_4.pdf new file mode 100644 index 0000000..24a35df Binary files /dev/null and b/CircuitExp2/2-4/output_4.pdf differ diff --git a/CircuitExp2/2-4/output_5.pdf b/CircuitExp2/2-4/output_5.pdf new file mode 100644 index 0000000..291ac33 Binary files /dev/null and b/CircuitExp2/2-4/output_5.pdf differ diff --git a/CircuitExp2/2-4/output_6.pdf b/CircuitExp2/2-4/output_6.pdf new file mode 100644 index 0000000..e2090b2 Binary files /dev/null and b/CircuitExp2/2-4/output_6.pdf differ diff --git a/CircuitExp2/2-4/output_7.pdf b/CircuitExp2/2-4/output_7.pdf new file mode 100644 index 0000000..98c97fd Binary files /dev/null and b/CircuitExp2/2-4/output_7.pdf differ diff --git a/CircuitExp2/2-4/output_9.pdf b/CircuitExp2/2-4/output_9.pdf new file mode 100644 index 0000000..1327d08 Binary files /dev/null and b/CircuitExp2/2-4/output_9.pdf differ diff --git a/CircuitExp2/2.docx b/CircuitExp2/2.docx new file mode 100644 index 0000000..6d05612 Binary files /dev/null and b/CircuitExp2/2.docx differ diff --git a/CircuitExp2/2.pdf b/CircuitExp2/2.pdf new file mode 100644 index 0000000..bc76d03 Binary files /dev/null and b/CircuitExp2/2.pdf differ diff --git a/CircuitExp3/3.docx b/CircuitExp3/3.docx new file mode 100644 index 0000000..e3c185d Binary files /dev/null and b/CircuitExp3/3.docx differ diff --git a/CircuitExp3/3.pdf b/CircuitExp3/3.pdf new file mode 100644 index 0000000..1a21b18 Binary files /dev/null and b/CircuitExp3/3.pdf differ diff --git a/CircuitExp3/CIRCUITEXP3.DSN b/CircuitExp3/CIRCUITEXP3.DSN new file mode 100644 index 0000000..c57d5b3 Binary files /dev/null and b/CircuitExp3/CIRCUITEXP3.DSN differ diff --git a/CircuitExp3/CIRCUITEXP3_0.DBK b/CircuitExp3/CIRCUITEXP3_0.DBK new file mode 100644 index 0000000..53e780b Binary files /dev/null and b/CircuitExp3/CIRCUITEXP3_0.DBK differ diff --git a/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/ExpSim3.sim b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/ExpSim3.sim new file mode 100644 index 0000000..eb91b3f --- /dev/null +++ b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/ExpSim3.sim @@ -0,0 +1,137 @@ +@OrCAD Simulation Server Version: 1.0 + +@Settings: 3 1 +@General: +ProfileName= "ExpSim3" +ProfileFile= "ExpSim3.sim" +Connectivity= "SCHEMATIC1.net" +NetlistFile= "ExpSim3.cir" +DataFile= "ExpSim3.dat" +OutFile= "ExpSim3.out" +Notes= +@#$BEGINNOTES +@#$ENDNOTES +@End General +@Analysis: 0 0 ++0 0 0 0 ++0 "1000ns" ++1 "" ++2 "0" ++3 "" ++4 "" ++5 "" ++6 "" +@End Analysis +@Analysis: 1 0 ++2 0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 2 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 3 1 ++1 0 0 ++0 "" ++1 "" ++2 "" +@End Analysis +@Analysis: 4 0 ++0 0 1 0 0 0 3 0 0 0 1 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +LoadFile 0 "" +SaveFile 0 "" +@End Analysis +@Analysis: 5 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 6 0 ++1 ++0 "" +@End Analysis +@Analysis: 7 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 8 0 ++0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" +@End Analysis +@Analysis: 9 0 ++0 "" +@End Analysis +@Analysis: 10 0 ++0 0 ++0 "" ++1 "" ++2 "" ++3 "" ++4 "" ++5 "" ++6 "" ++7 "" +@End Analysis +@Analysis: 11 1 ++ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0 0 0 +@End Analysis +@Analysis: 12 0 ++2236960 0 +@End Analysis +@Analysis: 13 1 ++0 1 1 0 +@End Analysis +@Analysis: 14 1 ++1 1 1 "*" +@End Analysis +@Analysis: 15 0 +@End Analysis +@Analysis: 16 0 ++0 "0" ++1 "0" ++2 "chkpt_default, , ," +@End Analysis +@Analysis: 17 0 ++0 "-1" ++1 "" ++2 "-1" ++3 "-1" ++4 "1" +@End Analysis diff --git a/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/ExpSim3/ExpSim3.1OP b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/ExpSim3/ExpSim3.1OP new file mode 100644 index 0000000..c16a9bc Binary files /dev/null and b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/ExpSim3/ExpSim3.1OP differ diff --git a/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/ExpSim3/ExpSim3.cir b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/ExpSim3/ExpSim3.cir new file mode 100644 index 0000000..46b3b3c --- /dev/null +++ b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/ExpSim3/ExpSim3.cir @@ -0,0 +1,18 @@ +** Profile: "SCHEMATIC1-ExpSim3" [ F:\Schoolwork\AnalogCircuit\CircuitExp3\CircuitExp3-PSpiceFiles\SCHEMATIC1\ExpSim3.sim ] + +** Creating circuit file "ExpSim3.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.OP +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + +.END diff --git a/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/ExpSim3/ExpSim3.mrk b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/ExpSim3/ExpSim3.mrk new file mode 100644 index 0000000..a1c2448 Binary files /dev/null and b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/ExpSim3/ExpSim3.mrk differ diff --git a/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/ExpSim3/ExpSim3.out b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/ExpSim3/ExpSim3.out new file mode 100644 index 0000000..cb2a672 --- /dev/null +++ b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/ExpSim3/ExpSim3.out @@ -0,0 +1,137 @@ + +**** 11/27/24 05:07:59 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim3" [ F:\Schoolwork\AnalogCircuit\CircuitExp3\CircuitExp3-PSpiceFiles\SCHEMATIC1\ExpSim3.sim ] + + + **** CIRCUIT DESCRIPTION + + +****************************************************************************** + + + + +** Creating circuit file "ExpSim3.cir" +** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS + +*Libraries: +* Profile Libraries : +* Local Libraries : +* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file: +.lib "nomd.lib" + +*Analysis directives: +.OP +.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) +.INC "..\SCHEMATIC1.net" + + + +**** INCLUDING SCHEMATIC1.net **** +* source CIRCUITEXP3 +R_R1 N00147 N00156 470 TC=0,0 +R_R2 N00156 N00170 100 TC=0,0 +R_R3 0 N00156 200 TC=0,0 +V_V1 N00147 0 10Vdc +V_V2 N00170 0 5Vdc +V_V3 N00616 0 10Vdc +R_R5 N00626 0 100 TC=0,0 +R_R6 0 N00626 200 TC=0,0 +R_R4 N00616 N00626 470 TC=0,0 +V_V5 N01002 0 5Vdc +R_R8 N00988 N01002 100 TC=0,0 +R_R9 0 N00988 200 TC=0,0 +R_R7 0 N00988 470 TC=0,0 +V_V6 N01457 0 5Vdc +R_R11 N01475 0 100 TC=0,0 +R_R10 N01457 N01475 470 TC=0,0 +R_R12 0 N01475 200 TC=0,0 +V_V7 N01878 0 10Vdc +V_V8 N01902 0 5Vdc +R_R13 N01878 N01888 470 TC=0,0 +R_R14 N01888 N01902 100 TC=0,0 +R_R17 0 N02307 100 TC=0,0 +R_R16 N02283 0 470 TC=0,0 +V_V10 N02307 0 5Vdc +V_V9 N02283 0 10Vdc +R_Ro N03369 N03376 82.449 TC=0,0 +R_R200 0 N03376 200 TC=0,0 +V_Uoc N03369 0 5.877Vdc + +**** RESUMING ExpSim3.cir **** +.END + +**** 11/27/24 05:07:59 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim3" [ F:\Schoolwork\AnalogCircuit\CircuitExp3\CircuitExp3-PSpiceFiles\SCHEMATIC1\ExpSim3.sim ] + + + **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C + + +****************************************************************************** + + + + NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE + + +(N00147) 10.0000 (N00156) 4.1615 (N00170) 5.0000 (N00616) 10.0000 + +(N00626) 1.2422 (N00988) 2.9193 (N01002) 5.0000 (N01457) 5.0000 + +(N01475) .6211 (N01878) 10.0000 (N01888) 5.8772 (N01902) 5.0000 + +(N02283) 10.0000 (N02307) 5.0000 (N03369) 5.8770 (N03376) 4.1615 + + + + + VOLTAGE SOURCE CURRENTS + NAME CURRENT + + V_V1 -1.242E-02 + V_V2 -8.385E-03 + V_V3 -1.863E-02 + V_V5 -2.081E-02 + V_V6 -9.317E-03 + V_V7 -8.772E-03 + V_V8 8.772E-03 + V_V10 -5.000E-02 + V_V9 -2.128E-02 + V_Uoc -2.081E-02 + + TOTAL POWER DISSIPATION 1.13E+00 WATTS + + +**** 11/27/24 05:07:59 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim3" [ F:\Schoolwork\AnalogCircuit\CircuitExp3\CircuitExp3-PSpiceFiles\SCHEMATIC1\ExpSim3.sim ] + + + **** OPERATING POINT INFORMATION TEMPERATURE = 27.000 DEG C + + +****************************************************************************** + + + + + + JOB CONCLUDED + +**** 11/27/24 05:07:59 ******* PSpice Lite (April 2011) ******* ID# 10813 **** + + ** Profile: "SCHEMATIC1-ExpSim3" [ F:\Schoolwork\AnalogCircuit\CircuitExp3\CircuitExp3-PSpiceFiles\SCHEMATIC1\ExpSim3.sim ] + + + **** JOB STATISTICS SUMMARY + + +****************************************************************************** + + + + Total job time (using Solver 1) = 0.00 + \ No newline at end of file diff --git a/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS new file mode 100644 index 0000000..f6ce6e5 --- /dev/null +++ b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.ALS @@ -0,0 +1,30 @@ +.ALIASES +R_R1 R1(1=N00147 2=N00156 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS26@ANALOG.R.Normal(chips) +R_R2 R2(1=N00156 2=N00170 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS51@ANALOG.R.Normal(chips) +R_R3 R3(1=0 2=N00156 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS76@ANALOG.R.Normal(chips) +V_V1 V1(+=N00147 -=0 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS101@SOURCE.VDC.Normal(chips) +V_V2 V2(+=N00170 -=0 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS117@SOURCE.VDC.Normal(chips) +V_V3 V3(+=N00616 -=0 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS566@SOURCE.VDC.Normal(chips) +R_R5 R5(1=N00626 2=0 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS526@ANALOG.R.Normal(chips) +R_R6 R6(1=0 2=N00626 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS546@ANALOG.R.Normal(chips) +R_R4 R4(1=N00616 2=N00626 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS506@ANALOG.R.Normal(chips) +V_V5 V5(+=N01002 -=0 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS948@SOURCE.VDC.Normal(chips) +R_R8 R8(1=N00988 2=N01002 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS888@ANALOG.R.Normal(chips) +R_R9 R9(1=0 2=N00988 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS908@ANALOG.R.Normal(chips) +R_R7 R7(1=0 2=N00988 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS868@ANALOG.R.Normal(chips) +V_V6 V6(+=N01457 -=0 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS1435@SOURCE.VDC.Normal(chips) +R_R11 R11(1=N01475 2=0 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS1393@ANALOG.R.Normal(chips) +R_R10 R10(1=N01457 2=N01475 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS1373@ANALOG.R.Normal(chips) +R_R12 R12(1=0 2=N01475 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS1415@ANALOG.R.Normal(chips) +V_V7 V7(+=N01878 -=0 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS1828@SOURCE.VDC.Normal(chips) +V_V8 V8(+=N01902 -=0 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS1848@SOURCE.VDC.Normal(chips) +R_R13 R13(1=N01878 2=N01888 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS1768@ANALOG.R.Normal(chips) +R_R14 R14(1=N01888 2=N01902 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS1788@ANALOG.R.Normal(chips) +R_R17 R17(1=0 2=N02307 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS2213@ANALOG.R.Normal(chips) +R_R16 R16(1=N02283 2=0 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS2193@ANALOG.R.Normal(chips) +V_V10 V10(+=N02307 -=0 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS2261@SOURCE.VDC.Normal(chips) +V_V9 V9(+=N02283 -=0 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS2233@SOURCE.VDC.Normal(chips) +R_Ro Ro(1=N03369 2=N03376 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS3141@ANALOG.R.Normal(chips) +R_R200 R200(1=0 2=N03376 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS3166@ANALOG.R.Normal(chips) +V_Uoc Uoc(+=N03369 -=0 ) CN @CIRCUITEXP3.SCHEMATIC1(sch_1):INS3285@SOURCE.VDC.Normal(chips) +.ENDALIASES diff --git a/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net new file mode 100644 index 0000000..7858ec5 --- /dev/null +++ b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1.net @@ -0,0 +1,29 @@ +* source CIRCUITEXP3 +R_R1 N00147 N00156 470 TC=0,0 +R_R2 N00156 N00170 100 TC=0,0 +R_R3 0 N00156 200 TC=0,0 +V_V1 N00147 0 10Vdc +V_V2 N00170 0 5Vdc +V_V3 N00616 0 10Vdc +R_R5 N00626 0 100 TC=0,0 +R_R6 0 N00626 200 TC=0,0 +R_R4 N00616 N00626 470 TC=0,0 +V_V5 N01002 0 5Vdc +R_R8 N00988 N01002 100 TC=0,0 +R_R9 0 N00988 200 TC=0,0 +R_R7 0 N00988 470 TC=0,0 +V_V6 N01457 0 5Vdc +R_R11 N01475 0 100 TC=0,0 +R_R10 N01457 N01475 470 TC=0,0 +R_R12 0 N01475 200 TC=0,0 +V_V7 N01878 0 10Vdc +V_V8 N01902 0 5Vdc +R_R13 N01878 N01888 470 TC=0,0 +R_R14 N01888 N01902 100 TC=0,0 +R_R17 0 N02307 100 TC=0,0 +R_R16 N02283 0 470 TC=0,0 +V_V10 N02307 0 5Vdc +V_V9 N02283 0 10Vdc +R_Ro N03369 N03376 82.449 TC=0,0 +R_R200 0 N03376 200 TC=0,0 +V_Uoc N03369 0 5.877Vdc diff --git a/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp new file mode 100644 index 0000000..d62b31a --- /dev/null +++ b/CircuitExp3/CircuitExp3-PSpiceFiles/SCHEMATIC1/SCHEMATIC1_sch.prp @@ -0,0 +1,316 @@ +("FILE_TYPE" "PMAP File" + ("devices" + ("R") + ("VDC") + ) + ("instances" + ("R1" + ("device_name" "R") + ("pspice_path" "R_R1") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "470") + ("pspice_param" "VALUE") + ) + ) + ) + ("R2" + ("device_name" "R") + ("pspice_path" "R_R2") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "100") + ("pspice_param" "VALUE") + ) + ) + ) + ("R3" + ("device_name" "R") + ("pspice_path" "R_R3") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "200") + ("pspice_param" "VALUE") + ) + ) + ) + ("V1" + ("device_name" "VDC") + ("pspice_path" "V_V1") + ("level" "0") + ("model_params" + ("DC" + ("value" "10Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("V2" + ("device_name" "VDC") + ("pspice_path" "V_V2") + ("level" "0") + ("model_params" + ("DC" + ("value" "5Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("V3" + ("device_name" "VDC") + ("pspice_path" "V_V3") + ("level" "0") + ("model_params" + ("DC" + ("value" "10Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("R5" + ("device_name" "R") + ("pspice_path" "R_R5") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "100") + ("pspice_param" "VALUE") + ) + ) + ) + ("R6" + ("device_name" "R") + ("pspice_path" "R_R6") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "200") + ("pspice_param" "VALUE") + ) + ) + ) + ("R4" + ("device_name" "R") + ("pspice_path" "R_R4") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "470") + ("pspice_param" "VALUE") + ) + ) + ) + ("V5" + ("device_name" "VDC") + ("pspice_path" "V_V5") + ("level" "0") + ("model_params" + ("DC" + ("value" "5Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("R8" + ("device_name" "R") + ("pspice_path" "R_R8") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "100") + ("pspice_param" "VALUE") + ) + ) + ) + ("R9" + ("device_name" "R") + ("pspice_path" "R_R9") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "200") + ("pspice_param" "VALUE") + ) + ) + ) + ("R7" + ("device_name" "R") + ("pspice_path" "R_R7") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "470") + ("pspice_param" "VALUE") + ) + ) + ) + ("V6" + ("device_name" "VDC") + ("pspice_path" "V_V6") + ("level" "0") + ("model_params" + ("DC" + ("value" "5Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("R11" + ("device_name" "R") + ("pspice_path" "R_R11") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "100") + ("pspice_param" "VALUE") + ) + ) + ) + ("R10" + ("device_name" "R") + ("pspice_path" "R_R10") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "470") + ("pspice_param" "VALUE") + ) + ) + ) + ("R12" + ("device_name" "R") + ("pspice_path" "R_R12") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "200") + ("pspice_param" "VALUE") + ) + ) + ) + ("V7" + ("device_name" "VDC") + ("pspice_path" "V_V7") + ("level" "0") + ("model_params" + ("DC" + ("value" "10Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("V8" + ("device_name" "VDC") + ("pspice_path" "V_V8") + ("level" "0") + ("model_params" + ("DC" + ("value" "5Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("R13" + ("device_name" "R") + ("pspice_path" "R_R13") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "470") + ("pspice_param" "VALUE") + ) + ) + ) + ("R14" + ("device_name" "R") + ("pspice_path" "R_R14") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "100") + ("pspice_param" "VALUE") + ) + ) + ) + ("R17" + ("device_name" "R") + ("pspice_path" "R_R17") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "100") + ("pspice_param" "VALUE") + ) + ) + ) + ("R16" + ("device_name" "R") + ("pspice_path" "R_R16") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "470") + ("pspice_param" "VALUE") + ) + ) + ) + ("V10" + ("device_name" "VDC") + ("pspice_path" "V_V10") + ("level" "0") + ("model_params" + ("DC" + ("value" "5Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("V9" + ("device_name" "VDC") + ("pspice_path" "V_V9") + ("level" "0") + ("model_params" + ("DC" + ("value" "10Vdc") + ("pspice_param" "DC") + ) + ) + ) + ("Ro" + ("device_name" "R") + ("pspice_path" "R_Ro") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "82.449") + ("pspice_param" "VALUE") + ) + ) + ) + ("R200" + ("device_name" "R") + ("pspice_path" "R_R200") + ("level" "0") + ("model_params" + ("VALUE" + ("value" "200") + ("pspice_param" "VALUE") + ) + ) + ) + ("Uoc" + ("device_name" "VDC") + ("pspice_path" "V_Uoc") + ("level" "0") + ("model_params" + ("DC" + ("value" "5.877Vdc") + ("pspice_param" "DC") + ) + ) + ) + ) +) diff --git a/CircuitExp3/CircuitExp3.opj b/CircuitExp3/CircuitExp3.opj new file mode 100644 index 0000000..94d3af8 --- /dev/null +++ b/CircuitExp3/CircuitExp3.opj @@ -0,0 +1,70 @@ +(ExpressProject "CircuitExp3" + (ProjectVersion "19981106") + (ProjectType "Analog or A/D Mixed Mode") + (Folder "Design Resources" + (Folder "Library") + (NoModify) + (File ".\circuitexp3.dsn" + (Type "Schematic Design")) + (BuildFileAddedOrDeleted "x") + (CompileFileAddedOrDeleted "x") + (PSPICE_Regenerate_Netlist_Flag "FALSE")) + (Folder "Outputs" + (File ".\circuitexp3-pspicefiles\schematic1\schematic1.net" + (Type "Report"))) + (Folder "PSpice Resources" + (Folder "Simulation Profiles" + (ActiveProfile ".\circuitexp3-pspicefiles\schematic1\expsim3.sim") + (File.PSpice.{09528990-3187-11D2-BC7B-00A0C90CBF91} + ".\circuitexp3-pspicefiles\schematic1\expsim3.sim" + (DisplayName "SCHEMATIC1-ExpSim3") + (Type "PSpice Profile"))) + (Folder "Model Libraries" + (Sort User)) + (Folder "Stimulus Files" + (Sort User)) + (Folder "Include Files" + (Sort User))) + (DefaultLibraryBrowseDirectory "library\PSpice") + (PartMRUSelector + (0 + (LibraryName "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB") + (DeviceIndex "0")) + (VDC + (FullPartName "VDC.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\SOURCE.OLB") + (DeviceIndex "0")) + (R + (FullPartName "R.Normal") + (LibraryName + "D:\ORCAD\ORCAD_16.5_LITE\TOOLS\CAPTURE\LIBRARY\PSPICE\ANALOG.OLB") + (DeviceIndex "0"))) + (GlobalState + (FileView + (Path "Design Resources") + (Path "Design Resources" + "D:\Schoolwork\AnalogCircuit\CircuitExp3\circuitexp3.dsn") + (Path "Design Resources" + "D:\Schoolwork\AnalogCircuit\CircuitExp3\circuitexp3.dsn" "SCHEMATIC1") + (Path "Outputs") + (Select "Design Resources" + "D:\Schoolwork\AnalogCircuit\CircuitExp3\circuitexp3.dsn" "SCHEMATIC1" + "PAGE1")) + (HierarchyView) + (Doc + (Type "COrCapturePMDoc") + (Frame + (Placement "44 0 1 -1 -1 -8 -31 0 200 0 430")) + (Tab 0)) + (Doc + (Type "COrSchematicDoc") + (Frame + (Placement "44 2 3 -1 -1 -8 -31 52 1475 52 485") + (Scroll "0 0") + (Zoom "321") + (Occurrence "/")) + (Path "D:\SCHOOLWORK\ANALOGCIRCUIT\CIRCUITEXP3\CIRCUITEXP3.DSN") + (Schematic "SCHEMATIC1") + (Page "PAGE1"))) + (MPSSessionName "launchcore")) diff --git a/CircuitExp3/Output1-1.pdf b/CircuitExp3/Output1-1.pdf new file mode 100644 index 0000000..40d3022 Binary files /dev/null and b/CircuitExp3/Output1-1.pdf differ diff --git a/CircuitExp3/Output1-2.pdf b/CircuitExp3/Output1-2.pdf new file mode 100644 index 0000000..657a753 Binary files /dev/null and b/CircuitExp3/Output1-2.pdf differ diff --git a/CircuitExp3/Output1-3.pdf b/CircuitExp3/Output1-3.pdf new file mode 100644 index 0000000..1c5af92 Binary files /dev/null and b/CircuitExp3/Output1-3.pdf differ diff --git a/CircuitExp3/Output1-4.pdf b/CircuitExp3/Output1-4.pdf new file mode 100644 index 0000000..d550777 Binary files /dev/null and b/CircuitExp3/Output1-4.pdf differ diff --git a/CircuitExp3/Output1-5.pdf b/CircuitExp3/Output1-5.pdf new file mode 100644 index 0000000..4549b08 Binary files /dev/null and b/CircuitExp3/Output1-5.pdf differ diff --git a/CircuitExp3/Output1-6.pdf b/CircuitExp3/Output1-6.pdf new file mode 100644 index 0000000..6a08a42 Binary files /dev/null and b/CircuitExp3/Output1-6.pdf differ diff --git a/CircuitExp3/Output2-1.pdf b/CircuitExp3/Output2-1.pdf new file mode 100644 index 0000000..ff5fe53 Binary files /dev/null and b/CircuitExp3/Output2-1.pdf differ diff --git a/CircuitExp3/Output2-2.pdf b/CircuitExp3/Output2-2.pdf new file mode 100644 index 0000000..6915ff2 Binary files /dev/null and b/CircuitExp3/Output2-2.pdf differ diff --git a/CircuitExp3/Output2-3.pdf b/CircuitExp3/Output2-3.pdf new file mode 100644 index 0000000..6d392cd Binary files /dev/null and b/CircuitExp3/Output2-3.pdf differ diff --git a/CircuitExp3/Output2-4.pdf b/CircuitExp3/Output2-4.pdf new file mode 100644 index 0000000..4a7cc12 Binary files /dev/null and b/CircuitExp3/Output2-4.pdf differ diff --git a/CircuitExp3/SCHEMATIC1 _ PAGE1.pdf b/CircuitExp3/SCHEMATIC1 _ PAGE1.pdf new file mode 100644 index 0000000..e173227 Binary files /dev/null and b/CircuitExp3/SCHEMATIC1 _ PAGE1.pdf differ diff --git a/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/鏂板缓鏂囨湰鏂囨。.txt b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/鏂板缓鏂囨湰鏂囨。.txt new file mode 100644 index 0000000..9ca6903 --- /dev/null +++ b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/鏂板缓鏂囨湰鏂囨。.txt @@ -0,0 +1,10 @@ +鐢佃矾3涓 +瀹為獙1 鐢佃矾鍏冧欢浼忓畨鐗规х殑鍒嗘瀽娴嬭瘯 +瀹為獙2 鍙楁帶婧愮爺绌 +瀹為獙3 缃戠粶瀹氱悊鐨勬祴璇 +妯＄數5涓 +瀹為獙1 妯℃嫙杩愮畻鐢佃矾(浠跨湡) +瀹為獙2 BJT鍏卞皠鏋佺數鍘嬫斁澶х數璺垎鏋(浠跨湡) +瀹為獙3 鍦烘晥搴旂鏀惧ぇ鐢佃矾锛堜豢鐪燂級 +瀹為獙4 宸垎鏀惧ぇ鐢佃矾(浠跨湡) +瀹為獙5 璐熷弽棣堟斁澶х數璺(浠跨湡) \ No newline at end of file diff --git a/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/妯＄數瀹為獙1 妯℃嫙杩愮畻鐢佃矾(浠跨湡).pdf b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/妯＄數瀹為獙1 妯℃嫙杩愮畻鐢佃矾(浠跨湡).pdf new file mode 100644 index 0000000..2fa6588 Binary files /dev/null and b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/妯＄數瀹為獙1 妯℃嫙杩愮畻鐢佃矾(浠跨湡).pdf differ diff --git a/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/妯＄數瀹為獙2 BJT鍏卞皠鏋佺數鍘嬫斁澶х數璺垎鏋(浠跨湡).pdf b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/妯＄數瀹為獙2 BJT鍏卞皠鏋佺數鍘嬫斁澶х數璺垎鏋(浠跨湡).pdf new file mode 100644 index 0000000..9ac509f Binary files /dev/null and b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/妯＄數瀹為獙2 BJT鍏卞皠鏋佺數鍘嬫斁澶х數璺垎鏋(浠跨湡).pdf differ diff --git a/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/妯＄數瀹為獙3 鍦烘晥搴旂鏀惧ぇ鐢佃矾锛堜豢鐪燂級.pdf b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/妯＄數瀹為獙3 鍦烘晥搴旂鏀惧ぇ鐢佃矾锛堜豢鐪燂級.pdf new file mode 100644 index 0000000..dd4ba54 Binary files /dev/null and b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/妯＄數瀹為獙3 鍦烘晥搴旂鏀惧ぇ鐢佃矾锛堜豢鐪燂級.pdf differ diff --git a/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/妯＄數瀹為獙4 宸垎鏀惧ぇ鐢佃矾(浠跨湡).pdf b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/妯＄數瀹為獙4 宸垎鏀惧ぇ鐢佃矾(浠跨湡).pdf new file mode 100644 index 0000000..facded1 Binary files /dev/null and b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/妯＄數瀹為獙4 宸垎鏀惧ぇ鐢佃矾(浠跨湡).pdf differ diff --git a/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/妯＄數瀹為獙5 璐熷弽棣堟斁澶х數璺(浠跨湡).pdf b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/妯＄數瀹為獙5 璐熷弽棣堟斁澶х數璺(浠跨湡).pdf new file mode 100644 index 0000000..1f4e0c5 Binary files /dev/null and b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/妯＄數瀹為獙5 璐熷弽棣堟斁澶х數璺(浠跨湡).pdf differ diff --git a/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/鐢佃矾瀹為獙1 鐢佃矾鍏冧欢浼忓畨鐗规х殑鍒嗘瀽娴嬭瘯.pdf b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/鐢佃矾瀹為獙1 鐢佃矾鍏冧欢浼忓畨鐗规х殑鍒嗘瀽娴嬭瘯.pdf new file mode 100644 index 0000000..e2e9fa6 Binary files /dev/null and b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/鐢佃矾瀹為獙1 鐢佃矾鍏冧欢浼忓畨鐗规х殑鍒嗘瀽娴嬭瘯.pdf differ diff --git a/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/鐢佃矾瀹為獙2 鍙楁帶婧愮爺绌.pdf b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/鐢佃矾瀹為獙2 鍙楁帶婧愮爺绌.pdf new file mode 100644 index 0000000..e214967 Binary files /dev/null and b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/鐢佃矾瀹為獙2 鍙楁帶婧愮爺绌.pdf differ diff --git a/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/鐢佃矾瀹為獙3 缃戠粶瀹氱悊鐨勬祴璇.pdf b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/鐢佃矾瀹為獙3 缃戠粶瀹氱悊鐨勬祴璇.pdf new file mode 100644 index 0000000..25329b7 Binary files /dev/null and b/鐢佃矾涓庢ā鎷熺數瀛愭妧鏈豢鐪熷疄楠屾寚瀵间功/鐢佃矾瀹為獙3 缃戠粶瀹氱悊鐨勬祴璇.pdf differ