`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/05/30 20:48:55
// Design Name: 
// Module Name: PC
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module PC (
    input  wire        rst,
    input  wire        clk,
    input  wire [31:0] offset,
    input  wire        pc_inc,
    output reg  [31:0] PCdata
);
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            PCdata <= 32'h00000000;
        end
        else begin
            if (pc_inc) begin
                PCdata <= PCdata + 1;
            end
            else begin
                PCdata <= PCdata + offset;
            end
        end
    end
endmodule
