`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/05/30 19:43:40
// Design Name: 
// Module Name: DR
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module DR (
    input  wire [31:0] Datain,
    input  wire        clk,
    input  wire        WE,
    output reg  [31:0] DataOut
);
    always @(posedge clk) begin
        if (WE) begin
            DataOut <= Datain;
        end
    end
endmodule
