module Registers(
    input         clk,
    input         RegWr,
    input  [4:0]  Ra, Rb, Rw,
    input  [31:0] busW,
    output [31:0] busA,
    output [31:0] busB
);
    reg [31:0] regs[0:31];
    integer i;
    initial begin
        for (i = 0; i < 32; i = i + 1) begin
            regs[i] = 32'd0;
        end
    end

    always @(posedge clk) begin
        if (RegWr && (Rw != 5'd0)) begin
            regs[Rw] <= busW;
        end
    end

    assign busA = (Ra == 5'd0) ? 32'd0 : regs[Ra];
    assign busB = (Rb == 5'd0) ? 32'd0 : regs[Rb];
endmodule