module DataRAM(
    input         clk,
    input         MemWrEn,
    input  [31:0] addr,
    input  [31:0] data_in,
    output [31:0] data_out
);
    reg [31:0] ram[0:1023];
    wire [9:0] word_addr = addr[11:2];

    always @(posedge clk) begin
        if (MemWrEn) begin
            ram[word_addr] <= data_in;
        end
    end
    assign data_out = ram[word_addr];
endmodule