commit 07678f510c244ec5108f35a7c09046c75a077857 Author: Launchcore Date: Thu Nov 6 09:35:54 2025 +0800 Initial commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..b58b8a6 --- /dev/null +++ b/.gitignore @@ -0,0 +1,133 @@ +### MicrosoftOffice ### +*.tmp + +# Word temporary +~$*.doc* + +# Word Auto Backup File +Backup of *.doc* + +# Excel temporary +~$*.xls* + +# Excel Backup File +*.xlk + +# PowerPoint temporary +~$*.ppt* + +# Visio autosave temporary files +*.~vsd* + +### VisualStudioCode ### +.vscode/* +!.vscode/settings.json +!.vscode/tasks.json +!.vscode/launch.json +!.vscode/extensions.json +!.vscode/*.code-snippets + +# Local History for Visual Studio Code +.history/ + +# Built Visual Studio Code Extensions +*.vsix + +### VisualStudioCode Patch ### +# Ignore all local history of files +.history +.ionide + +### Vivado ### +######################################################################################################### +## This is an example .gitignore file for Vivado, please treat it as an example as +## it might not be complete. In addition, XAPP 1165 should be followed. +######### +#Exclude all +Exp**/* +!*/ +!.gitignore +!Exp**.docx +########################################################################### +## VIVADO +#Source files: +#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. +!*.vhd +!*.v +!*.sv +!*.bd +!*.edif +#IP files +#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products +#.xci + .dcp: implementation possible but not re-synthesis +#*.xci(www.spiritconsortium.org) +!*.xci +#.xcix: Core container file +#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41) +!*.xcix +#*.dcp(checkpoint files) +!*.dcp +!*.vds +!*.pb +#All bd comments and layout coordinates are stored within .ui +!*.ui +!*.ooc +#System Generator +!*.mdl +!*.slx +!*.bxml +#Simulation logic analyzer +!*.wcfg +!*.coe +#MIG +!*.prj +!*.mem +#Project files +#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version) +#Do NOT ignore *.xpr files +!*.xpr +#Include *.xml files for 2013.4 or earlier version +!*.xml +#Constraint files +#Do NOT ignore *.xdc files +!*.xdc +#TCL - files +!*.tcl +#Journal - files +!*.jou +#Reports +!*.rpt +!*.txt +!*.vdi +#C-files +!*.c +!*.h +!*.elf +!*.bmm +!*.xmp + +### Windows ### +# Windows thumbnail cache files +Thumbs.db +Thumbs.db:encryptable +ehthumbs.db +ehthumbs_vista.db + +# Dump file +*.stackdump + +# Folder config file +[Dd]esktop.ini + +# Recycle Bin used on file shares +$RECYCLE.BIN/ + +# Windows Installer files +*.cab +*.msi +*.msix +*.msm +*.msp + +# Windows shortcuts +*.lnk diff --git a/2025-计算机组成原理实验讲义LA32R.docx b/2025-计算机组成原理实验讲义LA32R.docx new file mode 100644 index 0000000..9194d18 Binary files /dev/null and b/2025-计算机组成原理实验讲义LA32R.docx differ diff --git a/Exp1/Exp1.cache/wt/webtalk_pa.xml b/Exp1/Exp1.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..0deb9d1 --- /dev/null +++ b/Exp1/Exp1.cache/wt/webtalk_pa.xml @@ -0,0 +1,44 @@ + + + + +
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+ + diff --git a/Exp1/Exp1.xpr b/Exp1/Exp1.xpr new file mode 100644 index 0000000..a0a2e64 --- /dev/null +++ b/Exp1/Exp1.xpr @@ -0,0 +1,128 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + diff --git a/Exp1Report.docx b/Exp1Report.docx new file mode 100644 index 0000000..44c7a57 Binary files /dev/null and b/Exp1Report.docx differ diff --git a/Exp2/Exp2.cache/wt/webtalk_pa.xml b/Exp2/Exp2.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..a37a708 --- /dev/null +++ b/Exp2/Exp2.cache/wt/webtalk_pa.xml @@ -0,0 +1,30 @@ + + + + +
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+ + diff --git a/Exp2/Exp2.srcs/sources_1/new/DR.v b/Exp2/Exp2.srcs/sources_1/new/DR.v new file mode 100644 index 0000000..db92ef8 --- /dev/null +++ b/Exp2/Exp2.srcs/sources_1/new/DR.v @@ -0,0 +1,34 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/05/30 19:43:40 +// Design Name: +// Module Name: DR +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module DR ( + input wire [31:0] Datain, + input wire clk, + input wire WE, + output reg [31:0] DataOut +); + always @(posedge clk) begin + if (WE) begin + DataOut <= Datain; + end + end +endmodule diff --git a/Exp2/Exp2.srcs/sources_1/new/PC.v b/Exp2/Exp2.srcs/sources_1/new/PC.v new file mode 100644 index 0000000..cd79057 --- /dev/null +++ b/Exp2/Exp2.srcs/sources_1/new/PC.v @@ -0,0 +1,43 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/05/30 20:48:55 +// Design Name: +// Module Name: PC +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module PC ( + input wire rst, + input wire clk, + input wire [31:0] offset, + input wire pc_inc, + output reg [31:0] PCdata +); + always @(posedge clk or posedge rst) begin + if (rst) begin + PCdata <= 32'h00000000; + end + else begin + if (pc_inc) begin + PCdata <= PCdata + 1; + end + else begin + PCdata <= PCdata + offset; + end + end + end +endmodule diff --git a/Exp2/Exp2.srcs/sources_1/new/RAM.v b/Exp2/Exp2.srcs/sources_1/new/RAM.v new file mode 100644 index 0000000..6735cea --- /dev/null +++ b/Exp2/Exp2.srcs/sources_1/new/RAM.v @@ -0,0 +1,37 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/05/30 20:50:37 +// Design Name: +// Module Name: RAM +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module RAM ( + input wire clk, + input wire MemWrEn, + input wire [31:0] addr, + input wire [31:0] data_in, + output wire [31:0] data_out +); + reg [31:0] memory_array [2^32-1:0]; + always @(posedge clk) begin + if (MemWrEn) begin + memory_array[addr] <= data_in; + end + end + assign data_out = memory_array[addr]; +endmodule diff --git a/Exp2/Exp2.srcs/sources_1/new/Registers.v b/Exp2/Exp2.srcs/sources_1/new/Registers.v new file mode 100644 index 0000000..55eea8f --- /dev/null +++ b/Exp2/Exp2.srcs/sources_1/new/Registers.v @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/05/30 20:49:51 +// Design Name: +// Module Name: Registers +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Registers ( + input wire clk, + input wire RegWr, + input wire [4:0] Ra, + input wire [4:0] Rb, + input wire [4:0] Rw, + input wire [31:0] busW, + output wire [31:0] busA, + output wire [31:0] busB +); + reg [31:0] register_file [31:0]; + always @(posedge clk) begin + if (RegWr && (Rw != 5'b00000)) begin + register_file[Rw] <= busW; + end + end + assign busA = (Ra == 5'b00000) ? 32'h00000000 : register_file[Ra]; + assign busB = (Rb == 5'b00000) ? 32'h00000000 : register_file[Rb]; +endmodule diff --git a/Exp2/Exp2.xpr b/Exp2/Exp2.xpr new file mode 100644 index 0000000..5991905 --- /dev/null +++ b/Exp2/Exp2.xpr @@ -0,0 +1,162 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + diff --git a/Exp2Report.docx b/Exp2Report.docx new file mode 100644 index 0000000..29cf22f Binary files /dev/null and b/Exp2Report.docx differ diff --git a/Exp3/Exp3.cache/wt/webtalk_pa.xml b/Exp3/Exp3.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..9e615d6 --- /dev/null +++ b/Exp3/Exp3.cache/wt/webtalk_pa.xml @@ -0,0 +1,57 @@ + + + + +
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+ + diff --git a/Exp3/Exp3.srcs/sources_1/new/ALU.v b/Exp3/Exp3.srcs/sources_1/new/ALU.v new file mode 100644 index 0000000..e69de29 diff --git a/Exp3/Exp3.srcs/sources_1/new/DataRAM.v b/Exp3/Exp3.srcs/sources_1/new/DataRAM.v new file mode 100644 index 0000000..e69de29 diff --git a/Exp3/Exp3.srcs/sources_1/new/Datapath.v b/Exp3/Exp3.srcs/sources_1/new/Datapath.v new file mode 100644 index 0000000..a365546 --- /dev/null +++ b/Exp3/Exp3.srcs/sources_1/new/Datapath.v @@ -0,0 +1,76 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/06/06 15:26:45 +// Design Name: +// Module Name: Datapath +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module DataPath ( + input wire clk, + input wire rst, + input wire [31:0] Instr, + input wire srcReg, + input wire ALUBsrc, + input wire MemToReg, + input wire RegWr, + input wire MemWrEn, + input wire [2:0] ALUop, + input wire [1:0] Extop +); + wire [4:0] rd = Instr[4:0]; + wire [4:0] rj = Instr[9:5]; + wire [4:0] rk = Instr[14:10]; + wire [31:0] immExt; + Ext u_ext ( + .DataIn (Instr), + .Extop (Extop), + .DataOut(immExt) + ); + wire [4:0] Rb_sel = srcReg ? rd : rk; + wire [31:0] busA, busB_reg; + wire [31:0] WriteData; + Registers u_regs ( + .clk (clk), + .RegWr(RegWr), + .Ra (rj), + .Rb (Rb_sel), + .Rw (rd), + .busW (WriteData), + .busA (busA), + .busB (busB_reg) + ); + wire [31:0] aluB = ALUBsrc ? immExt : busB_reg; + wire [31:0] aluResult; + wire aluZero; + ALU u_alu ( + .a (busA), + .b (aluB), + .op (ALUop), + .result (aluResult), + .Zero (aluZero) + ); + wire [31:0] ramDataOut; + DataRAM u_dram ( + .clk (clk), + .MemWrEn (MemWrEn), + .addr (aluResult), + .data_in (busB_reg), + .data_out(ramDataOut) + ); + assign WriteData = MemToReg ? ramDataOut : aluResult; +endmodule \ No newline at end of file diff --git a/Exp3/Exp3.srcs/sources_1/new/Ext.v b/Exp3/Exp3.srcs/sources_1/new/Ext.v new file mode 100644 index 0000000..e69de29 diff --git a/Exp3/Exp3.srcs/sources_1/new/Mux.v b/Exp3/Exp3.srcs/sources_1/new/Mux.v new file mode 100644 index 0000000..86dc13a --- /dev/null +++ b/Exp3/Exp3.srcs/sources_1/new/Mux.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/06/06 15:29:28 +// Design Name: +// Module Name: Mux +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Mux( + + ); +endmodule diff --git a/Exp3/Exp3.srcs/sources_1/new/Registers.v b/Exp3/Exp3.srcs/sources_1/new/Registers.v new file mode 100644 index 0000000..e69de29 diff --git a/Exp3/Exp3.xpr b/Exp3/Exp3.xpr new file mode 100644 index 0000000..74e1f47 --- /dev/null +++ b/Exp3/Exp3.xpr @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + diff --git a/Exp3Report.docx b/Exp3Report.docx new file mode 100644 index 0000000..d565fbf Binary files /dev/null and b/Exp3Report.docx differ diff --git a/Exp4/Exp4.cache/wt/webtalk_pa.xml b/Exp4/Exp4.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..cdede95 --- /dev/null +++ b/Exp4/Exp4.cache/wt/webtalk_pa.xml @@ -0,0 +1,40 @@ + + + + +
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+ + diff --git a/Exp4/Exp4.srcs/sources_1/new/Controller.v b/Exp4/Exp4.srcs/sources_1/new/Controller.v new file mode 100644 index 0000000..7f1222e --- /dev/null +++ b/Exp4/Exp4.srcs/sources_1/new/Controller.v @@ -0,0 +1,107 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/06/13 14:23:19 +// Design Name: +// Module Name: Controller +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Controller ( + input [31:15] Instr, + output reg RegWr, + output reg ALUBsrc, + output reg MemToReg, + output reg MemWrEn, + output reg srcReg, + output reg [2:0] AluCtrl, + output reg [1:0] ExtOp +); + localparam ADD_W = 17'b00000010001000000; + localparam SLT_W = 17'b00000010010000000; + localparam SLTU_W = 17'b00000010011000000; + localparam LU12I_W = 7'b0001010; + localparam LD_W = 7'b0010100; + localparam ST_W = 7'b0010101; + localparam ALU_ADD = 3'b000; + localparam ALU_SLT = 3'b101; + localparam ALU_SLTU = 3'b110; + localparam EXT_SIGN_12 = 2'b00; + localparam EXT_ZERO_20 = 2'b10; + always @(*) begin + RegWr = 1'b0; + ALUBsrc = 1'b0; + MemToReg = 1'b0; + MemWrEn = 1'b0; + srcReg = 1'b0; + AluCtrl = 3'bxxx; + ExtOp = 2'bxx; + if (Instr == ADD_W) begin + RegWr = 1'b1; + ALUBsrc = 1'b0; + MemToReg = 1'b0; + MemWrEn = 1'b0; + srcReg = 1'b0; + AluCtrl = ALU_ADD; + ExtOp = 2'bxx; + end + else if (Instr == SLT_W) begin + RegWr = 1'b1; + ALUBsrc = 1'b0; + MemToReg = 1'b0; + MemWrEn = 1'b0; + srcReg = 1'b0; + AluCtrl = ALU_SLT; + ExtOp = 2'bxx; + end + else if (Instr == SLTU_W) begin + RegWr = 1'b1; + ALUBsrc = 1'b0; + MemToReg = 1'b0; + MemWrEn = 1'b0; + srcReg = 1'b0; + AluCtrl = ALU_SLTU; + ExtOp = 2'bxx; + end + else if (Instr[31:25] == LU12I_W) begin + RegWr = 1'b1; + ALUBsrc = 1'b1; + MemToReg = 1'b0; + MemWrEn = 1'b0; + srcReg = 1'b0; + AluCtrl = ALU_ADD; + ExtOp = EXT_ZERO_20; + end + else if (Instr[31:25] == LD_W) begin + RegWr = 1'b1; + ALUBsrc = 1'b1; + MemToReg = 1'b1; + MemWrEn = 1'b0; + srcReg = 1'b0; + AluCtrl = ALU_ADD; + ExtOp = EXT_SIGN_12; + end + else if (Instr[31:25] == ST_W) begin + RegWr = 1'b0; + ALUBsrc = 1'b1; + MemToReg = 1'bx; + MemWrEn = 1'b1; + srcReg = 1'b1; + AluCtrl = ALU_ADD; + ExtOp = EXT_SIGN_12; + end + end +endmodule diff --git a/Exp4/Exp4.xpr b/Exp4/Exp4.xpr new file mode 100644 index 0000000..c7f42c2 --- /dev/null +++ b/Exp4/Exp4.xpr @@ -0,0 +1,138 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + diff --git a/Exp4Report.docx b/Exp4Report.docx new file mode 100644 index 0000000..0a6cd14 Binary files /dev/null and b/Exp4Report.docx differ diff --git a/Experiments/Exp1/Exp1.ip_user_files/README.txt b/Experiments/Exp1/Exp1.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Experiments/Exp1/Exp1.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/glbl.v b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/tb_exp1.tcl b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/tb_exp1.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/tb_exp1.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/tb_exp1_vlog.prj b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/tb_exp1_vlog.prj new file mode 100644 index 0000000..6c4d608 --- /dev/null +++ b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/tb_exp1_vlog.prj @@ -0,0 +1,11 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../../Shared/ALU.v" \ +"../../../../../Shared/Ext.v" \ +"../../../../Exp1.srcs/sim_1/new/tb_exp1.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/webtalk.jou b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..ed47d89 --- /dev/null +++ b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Jul 2 00:04:46 2025 +# Process ID: 16772 +# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xelab.pb b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..3c6a215 Binary files /dev/null and b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/Compile_Options.txt b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/Compile_Options.txt new file mode 100644 index 0000000..cce0349 --- /dev/null +++ b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "37682ab63326475c8c4702befd41712b" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_exp1_behav" "xil_defaultlib.tb_exp1" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/TempBreakPointFile.txt b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/obj/xsim_1.c b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/obj/xsim_1.c new file mode 100644 index 0000000..bf0c0e3 --- /dev/null +++ b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/obj/xsim_1.c @@ -0,0 +1,118 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_6(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_3(char*, char *); +extern void execute_5(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +extern void execute_8(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_25(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[24] = {(funcp)execute_6, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_3, (funcp)execute_5, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 24; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/tb_exp1_behav/xsim.reloc", (void **)funcTab, 24); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/tb_exp1_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_exp1_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/tb_exp1_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/tb_exp1_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/tb_exp1_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/xsim.mem b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/xsim.mem new file mode 100644 index 0000000..bb64d8f Binary files /dev/null and b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/xsim.mem differ diff --git a/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xvlog.pb b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..833e58e Binary files /dev/null and b/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Experiments/Exp1/Exp1.srcs/sim_1/new/tb_exp1.v b/Experiments/Exp1/Exp1.srcs/sim_1/new/tb_exp1.v new file mode 100644 index 0000000..4af65f3 --- /dev/null +++ b/Experiments/Exp1/Exp1.srcs/sim_1/new/tb_exp1.v @@ -0,0 +1,48 @@ +`timescale 1ns / 1ps +module tb_exp1; + + reg [31:0] alu_a, alu_b; + reg [2:0] AluCtrl; + wire [31:0] AddResult; + wire Zero; + + reg [31:0] Ext_DataIn; + reg [1:0] ExtOp; + wire [31:0] Ext_DataOut; + + ALU u_ALU ( + .a(alu_a), .b(alu_b), .AluCtrl(AluCtrl), + .AddResult(AddResult), .Zero(Zero) + ); + + Ext u_Ext ( + .DataIn(Ext_DataIn), .ExtOp(ExtOp), .DataOut(Ext_DataOut) + ); + + initial begin + $display("----------------- 开始实验一仿真 -----------------"); + $display("=========== 测试 ALU 模块 ==========="); + alu_a = 32'd10; alu_b = 32'd5; AluCtrl = 3'b000; #10; + $display("ALU ADD: %d + %d = %d", alu_a, alu_b, AddResult); + alu_a = 32'd10; alu_b = 32'd10; AluCtrl = 3'b001; #10; + $display("ALU SUB: %d - %d = %d, Zero = %b", alu_a, alu_b, AddResult, Zero); + alu_a = 32'hFFFFFFFF; + alu_b = 32'd1; + AluCtrl = 3'b101; #10; + $display("ALU SLT: $signed(%h) < $signed(%h) is %d", alu_a, alu_b, AddResult); + AluCtrl = 3'b110; #10; + $display("ALU SLTU: %h < %h is %d", alu_a, alu_b, AddResult); + + $display("\n=========== 测试 Ext 模块 ==========="); + Ext_DataIn = 32'h02A4C503; + ExtOp = 2'b00; #10; + $display("ExtOp=00, DataIn=%h, DataOut=%h (符号扩展[21:10])", Ext_DataIn, Ext_DataOut); + ExtOp = 2'b01; #10; + $display("ExtOp=01, DataIn=%h, DataOut=%h (符号扩展[25:10] << 2)", Ext_DataIn, Ext_DataOut); + ExtOp = 2'b10; #10; + $display("ExtOp=10, DataIn=%h, DataOut=%h ([24:5] << 12)", Ext_DataIn, Ext_DataOut); + + $display("\n----------------- 实验一仿真结束 -----------------"); + $stop; + end +endmodule \ No newline at end of file diff --git a/Experiments/Exp1/Exp1.xpr b/Experiments/Exp1/Exp1.xpr new file mode 100644 index 0000000..cc10c4e --- /dev/null +++ b/Experiments/Exp1/Exp1.xpr @@ -0,0 +1,153 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + diff --git a/Experiments/Exp2/Exp2.ip_user_files/README.txt b/Experiments/Exp2/Exp2.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Experiments/Exp2/Exp2.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/glbl.v b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/tb_exp2.tcl b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/tb_exp2.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/tb_exp2.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/tb_exp2_vlog.prj b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/tb_exp2_vlog.prj new file mode 100644 index 0000000..5735c67 --- /dev/null +++ b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/tb_exp2_vlog.prj @@ -0,0 +1,13 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../../Shared/DR.v" \ +"../../../../../Shared/DataRAM.v" \ +"../../../../../Shared/PC.v" \ +"../../../../../Shared/Registers.v" \ +"../../../../Exp2.srcs/sim_1/new/tb_exp2.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.jou b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..a318586 --- /dev/null +++ b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Jul 3 04:25:52 2025 +# Process ID: 1908 +# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk_10888.backup.jou b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk_10888.backup.jou new file mode 100644 index 0000000..1f0ef57 --- /dev/null +++ b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk_10888.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Jul 3 04:22:12 2025 +# Process ID: 10888 +# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk_28652.backup.jou b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk_28652.backup.jou new file mode 100644 index 0000000..d5f22ee --- /dev/null +++ b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk_28652.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Jul 2 00:25:00 2025 +# Process ID: 28652 +# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/Schoolwork/ComputerComposition/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xelab.pb b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..392604b Binary files /dev/null and b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/Compile_Options.txt b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/Compile_Options.txt new file mode 100644 index 0000000..e38ea4f --- /dev/null +++ b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "164e4d51dc2148f893b981e9cc10cb15" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_exp2_behav" "xil_defaultlib.tb_exp2" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/TempBreakPointFile.txt b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/obj/xsim_1.c b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/obj/xsim_1.c new file mode 100644 index 0000000..fc063a4 --- /dev/null +++ b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/obj/xsim_1.c @@ -0,0 +1,133 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_25(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_28(char*, char *); +extern void execute_29(char*, char *); +extern void execute_30(char*, char *); +extern void execute_31(char*, char *); +extern void execute_32(char*, char *); +extern void execute_33(char*, char *); +extern void execute_34(char*, char *); +extern void execute_35(char*, char *); +extern void execute_36(char*, char *); +extern void execute_37(char*, char *); +extern void execute_38(char*, char *); +extern void execute_39(char*, char *); +extern void execute_3(char*, char *); +extern void execute_5(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_10(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_40(char*, char *); +extern void execute_41(char*, char *); +extern void execute_42(char*, char *); +extern void execute_43(char*, char *); +extern void execute_44(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[39] = {(funcp)execute_11, (funcp)execute_12, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_3, (funcp)execute_5, (funcp)execute_7, (funcp)execute_8, (funcp)execute_17, (funcp)execute_18, (funcp)execute_10, (funcp)execute_19, (funcp)execute_20, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 39; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/tb_exp2_behav/xsim.reloc", (void **)funcTab, 39); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/tb_exp2_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_exp2_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/tb_exp2_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/tb_exp2_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/tb_exp2_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/xsim.mem b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/xsim.mem new file mode 100644 index 0000000..fb2ff80 Binary files /dev/null and b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_exp2_behav/xsim.mem differ diff --git a/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xvlog.pb b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..afbf4e7 Binary files /dev/null and b/Experiments/Exp2/Exp2.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Experiments/Exp2/Exp2.srcs/sim_1/new/tb_exp2.v b/Experiments/Exp2/Exp2.srcs/sim_1/new/tb_exp2.v new file mode 100644 index 0000000..4324ee3 --- /dev/null +++ b/Experiments/Exp2/Exp2.srcs/sim_1/new/tb_exp2.v @@ -0,0 +1,67 @@ +module tb_exp2; + reg clk; + + reg DR_WE; + reg [31:0] DR_DataIn; + wire [31:0] DR_DataOut; + + reg PC_rst, PC_pc_inc; + reg [31:0] PC_offset; + wire [31:0] PC_PCdata; + + reg RegWr; + reg [4:0] Ra, Rb, Rw; + reg [31:0] busW; + wire [31:0] busA, busB; + + reg MemWrEn; + reg [31:0] addr, data_in; + wire [31:0] data_out; + + DR u_DR (.clk(clk), .WE(DR_WE), .DataIn(DR_DataIn), .DataOut(DR_DataOut)); + PC u_PC (.clk(clk), .rst(PC_rst), .pc_inc(PC_pc_inc), .offset(PC_offset), .PCdata(PC_PCdata)); + Registers u_Registers (.clk(clk), .RegWr(RegWr), .Ra(Ra), .Rb(Rb), .Rw(Rw), .busW(busW), .busA(busA), .busB(busB)); + DataRAM u_DataRAM (.clk(clk), .MemWrEn(MemWrEn), .addr(addr), .data_in(data_in), .data_out(data_out)); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + initial begin + $display("----------------- 开始实验二仿真 -----------------"); + + $display("\n=========== 1. 测试 DR 模块 ==========="); + DR_DataIn = 32'h12345678; DR_WE = 1; #10; + $display("T=%0t: 写入 DR, DataIn=%h. 期望 DataOut=%h. 实际 DataOut=%h", $time, DR_DataIn, DR_DataIn, DR_DataOut); + DR_WE = 0; DR_DataIn = 32'hFFFFFFFF; #10; + $display("T=%0t: 禁用写入, DataIn=%h. 期望 DataOut保持不变. 实际 DataOut=%h", $time, DR_DataIn, DR_DataOut); + + $display("\n=========== 2. 测试 PC 模块 ==========="); + PC_rst = 1; #10; + $display("T=%0t: 异步复位. 期望 PCdata=0. 实际 PCdata=%d", $time, PC_PCdata); + PC_rst = 0; PC_pc_inc = 1; #10; + $display("T=%0t: PC自增. 期望 PCdata=4. 实际 PCdata=%d", $time, PC_PCdata); + PC_pc_inc = 1; #10; + $display("T=%0t: PC再次自增. 期望 PCdata=8. 实际 PCdata=%d", $time, PC_PCdata); + PC_pc_inc = 0; PC_offset = 32'd100; #10; + $display("T=%0t: PC加偏移量100. 期望 PCdata=108. 实际 PCdata=%d", $time, PC_PCdata); + + $display("\n=========== 3. 测试 Registers 模块 ==========="); + RegWr = 1; Rw = 5; busW = 32'hAAAAAAAA; #10; + $display("T=%0t: 写入 r5 数据 0xAAAAAAAA", $time); + Rw = 10; busW = 32'hBBBBBBBB; #10; + $display("T=%0t: 写入 r10 数据 0xBBBBBBBB", $time); + RegWr = 0; Ra = 5; Rb = 10; #10; + $display("T=%0t: 读取 r5, r10. busA=%h, busB=%h", $time, busA, busB); + + $display("\n=========== 4. 测试 DataRAM 模块 ==========="); + MemWrEn = 1; addr = 32'd100; data_in = 32'hCAFECAFE; #10; + $display("T=%0t: 写入内存地址 100, 数据 0xCAFECAFE", $time); + MemWrEn = 0; addr = 32'd100; #10; + $display("T=%0t: 读取内存地址 100. data_out=%h", $time, data_out); + + $display("\n----------------- 实验二仿真结束 -----------------"); + $stop; + end +endmodule \ No newline at end of file diff --git a/Experiments/Exp2/Exp2.xpr b/Experiments/Exp2/Exp2.xpr new file mode 100644 index 0000000..dbe5433 --- /dev/null +++ b/Experiments/Exp2/Exp2.xpr @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + diff --git a/Experiments/Exp3/Exp3.ip_user_files/README.txt b/Experiments/Exp3/Exp3.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Experiments/Exp3/Exp3.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/glbl.v b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/tb_exp3.tcl b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/tb_exp3.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/tb_exp3.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/tb_exp3_vlog.prj b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/tb_exp3_vlog.prj new file mode 100644 index 0000000..3263b2b --- /dev/null +++ b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/tb_exp3_vlog.prj @@ -0,0 +1,14 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../../Shared/ALU.v" \ +"../../../../../Shared/DataRAM.v" \ +"../../../../../Shared/Datapath.v" \ +"../../../../../Shared/Ext.v" \ +"../../../../../Shared/Registers.v" \ +"../../../../Exp3.srcs/sim_1/new/tb_exp3.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk.jou b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..3008841 --- /dev/null +++ b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Jul 3 04:44:33 2025 +# Process ID: 32088 +# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk_28872.backup.jou b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk_28872.backup.jou new file mode 100644 index 0000000..d933176 --- /dev/null +++ b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk_28872.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Jul 3 04:43:32 2025 +# Process ID: 28872 +# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk_9612.backup.jou b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk_9612.backup.jou new file mode 100644 index 0000000..2151a7b --- /dev/null +++ b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk_9612.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Jul 2 00:32:33 2025 +# Process ID: 9612 +# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/Schoolwork/ComputerComposition/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xelab.pb b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..61bdb11 Binary files /dev/null and b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/Compile_Options.txt b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/Compile_Options.txt new file mode 100644 index 0000000..d31e52e --- /dev/null +++ b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0aa8d4d9ab684dbeab8e7342bdb2daf9" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_exp3_behav" "xil_defaultlib.tb_exp3" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/TempBreakPointFile.txt b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/obj/xsim_1.c b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/obj/xsim_1.c new file mode 100644 index 0000000..3d8e66e --- /dev/null +++ b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/obj/xsim_1.c @@ -0,0 +1,139 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_35(char*, char *); +extern void execute_36(char*, char *); +extern void execute_37(char*, char *); +extern void execute_38(char*, char *); +extern void execute_39(char*, char *); +extern void execute_40(char*, char *); +extern void execute_41(char*, char *); +extern void execute_42(char*, char *); +extern void execute_43(char*, char *); +extern void execute_44(char*, char *); +extern void execute_45(char*, char *); +extern void execute_46(char*, char *); +extern void execute_25(char*, char *); +extern void execute_28(char*, char *); +extern void execute_29(char*, char *); +extern void execute_30(char*, char *); +extern void execute_31(char*, char *); +extern void execute_32(char*, char *); +extern void execute_33(char*, char *); +extern void execute_34(char*, char *); +extern void execute_4(char*, char *); +extern void execute_5(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_7(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +extern void execute_9(char*, char *); +extern void execute_11(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_47(char*, char *); +extern void execute_48(char*, char *); +extern void execute_49(char*, char *); +extern void execute_50(char*, char *); +extern void execute_51(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[45] = {(funcp)execute_12, (funcp)execute_13, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_25, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)execute_33, (funcp)execute_34, (funcp)execute_4, (funcp)execute_5, (funcp)execute_18, (funcp)execute_19, (funcp)execute_7, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_9, (funcp)execute_11, (funcp)execute_26, (funcp)execute_27, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 45; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/tb_exp3_behav/xsim.reloc", (void **)funcTab, 45); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/tb_exp3_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_exp3_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/tb_exp3_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/tb_exp3_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/tb_exp3_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/xsim.mem b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/xsim.mem new file mode 100644 index 0000000..4f855e8 Binary files /dev/null and b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xsim.dir/tb_exp3_behav/xsim.mem differ diff --git a/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xvlog.pb b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..1041c6c Binary files /dev/null and b/Experiments/Exp3/Exp3.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Experiments/Exp3/Exp3.srcs/sim_1/new/tb_exp3.v b/Experiments/Exp3/Exp3.srcs/sim_1/new/tb_exp3.v new file mode 100644 index 0000000..b6bb2b5 --- /dev/null +++ b/Experiments/Exp3/Exp3.srcs/sim_1/new/tb_exp3.v @@ -0,0 +1,44 @@ +`timescale 1ns / 1ps +module tb_exp3; + reg clk; + reg [31:0] Instr; + reg RegWr, MemToReg, MemWrEn, ALUBSrc, srcReg; + reg [1:0] ExtOp; + reg [2:0] AluCtrl; + wire Zero; + + Datapath uut ( + .clk(clk), .Instr(Instr), .RegWr(RegWr), .MemToReg(MemToReg), .MemWrEn(MemWrEn), + .ALUBSrc(ALUBSrc), .srcReg(srcReg), .ExtOp(ExtOp), .AluCtrl(AluCtrl), .Zero(Zero) + ); + + wire [31:0] r1_val = uut.u_Registers.regs[1]; + wire [31:0] r2_val = uut.u_Registers.regs[2]; + wire [31:0] r3_val = uut.u_Registers.regs[3]; + + initial begin clk = 0; forever #5 clk = ~clk; end + + initial begin + $display("----------------- 开始实验三仿真 -----------------"); + uut.u_Registers.regs[1] = 32'd10; + uut.u_Registers.regs[2] = 32'd20; + #10; + $display("T=%0t: 初始化 r1=10, r2=20", $time); + + $display("\n模拟 add.w r3, r1, r2"); + Instr = {11'b0, 5'd2, 5'd1, 5'd3}; + RegWr=1; MemToReg=0; MemWrEn=0; ALUBSrc=0; srcReg=0; ExtOp=2'bxx; AluCtrl=3'b000; + #10; + $display("T=%0t: 执行 add.w. 期望 r3 = 30. 实际 r3 = %d", $time, r3_val); + + uut.u_DataRAM.ram[120/4] = 32'hDEADBEEF; + $display("\n模拟 ld.w r1, 100(r2)"); + Instr = {12'd100, 5'd2, 5'd1}; + RegWr=1; MemToReg=1; MemWrEn=0; ALUBSrc=1; srcReg=0; ExtOp=2'b00; AluCtrl=3'b000; + #10; + $display("T=%0t: 执行 ld.w. 期望 r1 = 0xDEADBEEF. 实际 r1 = %h", $time, r1_val); + + $display("\n----------------- 实验三仿真结束 -----------------"); + $stop; + end +endmodule diff --git a/Experiments/Exp3/Exp3.xpr b/Experiments/Exp3/Exp3.xpr new file mode 100644 index 0000000..56d402f --- /dev/null +++ b/Experiments/Exp3/Exp3.xpr @@ -0,0 +1,173 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + diff --git a/Experiments/Exp4/Exp4.ip_user_files/README.txt b/Experiments/Exp4/Exp4.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Experiments/Exp4/Exp4.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/glbl.v b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/tb_exp4.tcl b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/tb_exp4.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/tb_exp4.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/tb_exp4_vlog.prj b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/tb_exp4_vlog.prj new file mode 100644 index 0000000..fb7851f --- /dev/null +++ b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/tb_exp4_vlog.prj @@ -0,0 +1,16 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../../Shared/ALU.v" \ +"../../../../../Shared/Controller.v" \ +"../../../../../Shared/DataRAM.v" \ +"../../../../../Shared/Datapath.v" \ +"../../../../../Shared/Ext.v" \ +"../../../../../Shared/LA32R_CPU.v" \ +"../../../../../Shared/Registers.v" \ +"../../../../Exp4.srcs/sim_1/new/tb_exp4.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.jou b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..9de0295 --- /dev/null +++ b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Jul 3 05:15:51 2025 +# Process ID: 26536 +# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk_26240.backup.jou b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk_26240.backup.jou new file mode 100644 index 0000000..baa6cd8 --- /dev/null +++ b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk_26240.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Jul 2 00:40:08 2025 +# Process ID: 26240 +# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk_26568.backup.jou b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk_26568.backup.jou new file mode 100644 index 0000000..93c914b --- /dev/null +++ b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk_26568.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Jul 2 00:39:32 2025 +# Process ID: 26568 +# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk_33472.backup.jou b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk_33472.backup.jou new file mode 100644 index 0000000..10d3f29 --- /dev/null +++ b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk_33472.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Jul 3 05:13:39 2025 +# Process ID: 33472 +# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/Schoolwork/ComputerComposition/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xelab.pb b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..c6ccf26 Binary files /dev/null and b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/Compile_Options.txt b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/Compile_Options.txt new file mode 100644 index 0000000..4dc711f --- /dev/null +++ b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "ae2a6b03df4749b48fa62497cdcfc9a7" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_exp4_behav" "xil_defaultlib.tb_exp4" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/TempBreakPointFile.txt b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/obj/xsim_1.c b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/obj/xsim_1.c new file mode 100644 index 0000000..6fe6aec --- /dev/null +++ b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/obj/xsim_1.c @@ -0,0 +1,144 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_47(char*, char *); +extern void execute_48(char*, char *); +extern void execute_49(char*, char *); +extern void execute_50(char*, char *); +extern void execute_51(char*, char *); +extern void execute_52(char*, char *); +extern void execute_53(char*, char *); +extern void execute_40(char*, char *); +extern void execute_41(char*, char *); +extern void execute_42(char*, char *); +extern void execute_43(char*, char *); +extern void execute_44(char*, char *); +extern void execute_45(char*, char *); +extern void execute_46(char*, char *); +extern void execute_4(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_30(char*, char *); +extern void execute_33(char*, char *); +extern void execute_34(char*, char *); +extern void execute_35(char*, char *); +extern void execute_36(char*, char *); +extern void execute_37(char*, char *); +extern void execute_38(char*, char *); +extern void execute_39(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_10(char*, char *); +extern void execute_25(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_28(char*, char *); +extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +extern void execute_12(char*, char *); +extern void execute_14(char*, char *); +extern void execute_31(char*, char *); +extern void execute_32(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_54(char*, char *); +extern void execute_55(char*, char *); +extern void execute_56(char*, char *); +extern void execute_57(char*, char *); +extern void execute_58(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[50] = {(funcp)execute_15, (funcp)execute_16, (funcp)execute_47, (funcp)execute_48, (funcp)execute_49, (funcp)execute_50, (funcp)execute_51, (funcp)execute_52, (funcp)execute_53, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)execute_43, (funcp)execute_44, (funcp)execute_45, (funcp)execute_46, (funcp)execute_4, (funcp)execute_21, (funcp)execute_22, (funcp)execute_30, (funcp)execute_33, (funcp)execute_34, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_7, (funcp)execute_8, (funcp)execute_23, (funcp)execute_24, (funcp)execute_10, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_12, (funcp)execute_14, (funcp)execute_31, (funcp)execute_32, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_54, (funcp)execute_55, (funcp)execute_56, (funcp)execute_57, (funcp)execute_58, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 50; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/tb_exp4_behav/xsim.reloc", (void **)funcTab, 50); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/tb_exp4_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_exp4_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/tb_exp4_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/tb_exp4_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/tb_exp4_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/xsim.mem b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/xsim.mem new file mode 100644 index 0000000..82b15db Binary files /dev/null and b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/tb_exp4_behav/xsim.mem differ diff --git a/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xvlog.pb b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..e1fdfe4 Binary files /dev/null and b/Experiments/Exp4/Exp4.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Experiments/Exp4/Exp4.srcs/sim_1/new/tb_exp4.v b/Experiments/Exp4/Exp4.srcs/sim_1/new/tb_exp4.v new file mode 100644 index 0000000..4703a7e --- /dev/null +++ b/Experiments/Exp4/Exp4.srcs/sim_1/new/tb_exp4.v @@ -0,0 +1,43 @@ +`timescale 1ns / 1ps +module tb_exp4; + reg clk; + reg [31:0] Instr; + + LA32R_CPU uut (.clk(clk), .Instr(Instr)); + + wire [31:0] r1_val = uut.u_Datapath.u_Registers.regs[1]; + wire [31:0] r2_val = uut.u_Datapath.u_Registers.regs[2]; + wire [31:0] r3_val = uut.u_Datapath.u_Registers.regs[3]; + wire [31:0] r4_val = uut.u_Datapath.u_Registers.regs[4]; + wire [31:0] r5_val = uut.u_Datapath.u_Registers.regs[5]; + + initial begin clk = 0; forever #5 clk = ~clk; end + + initial begin + $display("----------------- 开始实验四仿真-----------------"); + + Instr = {3'b001, 4'b0, 20'h12345, 5'd1}; #10; + $display("执行 lu12i.w r1, 0x12345. 期望 r1=12345000. 实际 r1=%h", r1_val); + + Instr = {3'b001, 4'b0, 20'hABCDE, 5'd2}; #10; + $display("执行 lu12i.w r2, 0xABCDE. 期望 r2=abcde000. 实际 r2=%h", r2_val); + + Instr = {3'b000, 7'b0, 7'b0000010, 5'd2, 5'd1, 5'd3}; #10; + $display("执行 add.w r3, r1, r2. 期望 r3=be023000. 实际 r3=%h", r3_val); + + Instr = {3'b000, 7'b0, 7'b0000100, 5'd2, 5'd1, 5'd4}; #10; + $display("执行 slt r4, r1, r2. 期望 r4=00000000. 实际 r4=%h", r4_val); + + Instr = {3'b000, 7'b0, 7'b0000101, 5'd2, 5'd1, 5'd5}; #10; + $display("执行 sltu r5, r1, r2. 期望 r5=00000001. 实际 r5=%h", r5_val); + + Instr = {3'b011, 7'b0, 12'd100, 5'd2, 5'd1}; #10; + $display("执行 st.w r1, r2, 100. 将r1的值存入内存"); + + Instr = {3'b010, 7'b0, 12'd100, 5'd2, 5'd3}; #10; + $display("执行 ld.w r3, r2, 100. 期望 r3=12345000. 实际 r3=%h", r3_val); + + $display("\n----------------- 实验四仿真结束 -----------------"); + $stop; + end +endmodule diff --git a/Experiments/Exp4/Exp4.xpr b/Experiments/Exp4/Exp4.xpr new file mode 100644 index 0000000..c18bb38 --- /dev/null +++ b/Experiments/Exp4/Exp4.xpr @@ -0,0 +1,187 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + diff --git a/Experiments/Shared/ALU.v b/Experiments/Shared/ALU.v new file mode 100644 index 0000000..762c254 --- /dev/null +++ b/Experiments/Shared/ALU.v @@ -0,0 +1,31 @@ +module ALU( + input [31:0] a, + input [31:0] b, + input [2:0] AluCtrl, + output reg [31:0] AddResult, + output reg Zero +); + parameter ADD = 3'b000; + parameter SUB = 3'b001; + parameter AND = 3'b010; + parameter OR = 3'b011; + parameter NOR = 3'b100; + parameter SLT = 3'b101; + parameter SLTU = 3'b110; + parameter PASSB= 3'b111; + + always @(*) begin + case (AluCtrl) + ADD: AddResult = a + b; + SUB: AddResult = a - b; + AND: AddResult = a & b; + OR: AddResult = a | b; + NOR: AddResult = ~(a | b); + SLT: AddResult = ($signed(a) < $signed(b)) ? 32'd1 : 32'd0; + SLTU: AddResult = (a < b) ? 32'd1 : 32'd0; + PASSB:AddResult = b; + default: AddResult = 32'hxxxxxxxx; + endcase + Zero = (AddResult == 32'd0); + end +endmodule \ No newline at end of file diff --git a/Experiments/Shared/Controller.v b/Experiments/Shared/Controller.v new file mode 100644 index 0000000..21045d3 --- /dev/null +++ b/Experiments/Shared/Controller.v @@ -0,0 +1,43 @@ +module Controller( + input [31:15] Opcode_in, + output reg RegWr, + output reg MemToReg, + output reg MemWrEn, + output reg ALUBSrc, + output reg srcReg, + output reg [1:0] ExtOp, + output reg [2:0] AluCtrl +); + parameter OP_RTYPE = 3'b000, OP_LU12I = 3'b001, OP_LOAD = 3'b010, OP_STORE = 3'b011; + + parameter FUNC_ADD = 7'b0000010, FUNC_SLT = 7'b0000100, FUNC_SLTU= 7'b0000101; + + wire [2:0] main_op = Opcode_in[31:29]; + wire [6:0] func_op = Opcode_in[21:15]; + + always @(*) begin + RegWr=0; MemToReg=0; MemWrEn=0; ALUBSrc=0; srcReg=0; ExtOp=2'bxx; AluCtrl=3'bxxx; + + case(main_op) + OP_RTYPE: begin + RegWr=1; ALUBSrc=0; + case(func_op) + FUNC_ADD: AluCtrl = 3'b000; + FUNC_SLT: AluCtrl = 3'b101; + FUNC_SLTU: AluCtrl = 3'b110; + default: ; + endcase + end + OP_LU12I: begin + RegWr=1; ALUBSrc=1; ExtOp=2'b10; AluCtrl=3'b111; + end + OP_LOAD: begin + RegWr=1; MemToReg=1; ALUBSrc=1; ExtOp=2'b00; AluCtrl=3'b000; + end + OP_STORE: begin + MemWrEn=1; ALUBSrc=1; srcReg=1; ExtOp=2'b00; AluCtrl=3'b000; + end + default: ; + endcase + end +endmodule \ No newline at end of file diff --git a/Experiments/Shared/DR.v b/Experiments/Shared/DR.v new file mode 100644 index 0000000..8dd339e --- /dev/null +++ b/Experiments/Shared/DR.v @@ -0,0 +1,12 @@ +module DR( + input clk, + input WE, + input [31:0] DataIn, + output reg [31:0] DataOut +); + always @(posedge clk) begin + if (WE) begin + DataOut <= DataIn; + end + end +endmodule \ No newline at end of file diff --git a/Experiments/Shared/DataRAM.v b/Experiments/Shared/DataRAM.v new file mode 100644 index 0000000..4afc4ea --- /dev/null +++ b/Experiments/Shared/DataRAM.v @@ -0,0 +1,17 @@ +module DataRAM( + input clk, + input MemWrEn, + input [31:0] addr, + input [31:0] data_in, + output [31:0] data_out +); + reg [31:0] ram[0:1023]; + wire [9:0] word_addr = addr[11:2]; + + always @(posedge clk) begin + if (MemWrEn) begin + ram[word_addr] <= data_in; + end + end + assign data_out = ram[word_addr]; +endmodule \ No newline at end of file diff --git a/Experiments/Shared/Datapath.v b/Experiments/Shared/Datapath.v new file mode 100644 index 0000000..e5362ca --- /dev/null +++ b/Experiments/Shared/Datapath.v @@ -0,0 +1,24 @@ +module Datapath( + input clk, + input [31:0] Instr, + input RegWr, + input MemToReg, + input MemWrEn, + input ALUBSrc, + input srcReg, + input [1:0] ExtOp, + input [2:0] AluCtrl, + output Zero +); + wire [31:0] busA_out, busB_out, ext_out, alu_in_b, alu_result, ram_data_out, reg_write_data; + wire [4:0] rj = Instr[9:5]; + wire [4:0] rk_or_rd_store = Instr[14:10]; + wire [4:0] rd_write = Instr[4:0]; + + Registers u_Registers(.clk(clk), .RegWr(RegWr), .Ra(rj), .Rb(srcReg ? Instr[4:0] : rk_or_rd_store), .Rw(rd_write), .busW(reg_write_data), .busA(busA_out), .busB(busB_out)); + Ext u_Ext(.DataIn(Instr), .ExtOp(ExtOp), .DataOut(ext_out)); + assign alu_in_b = ALUBSrc ? ext_out : busB_out; + ALU u_ALU(.a(busA_out), .b(alu_in_b), .AluCtrl(AluCtrl), .AddResult(alu_result), .Zero(Zero)); + DataRAM u_DataRAM(.clk(clk), .MemWrEn(MemWrEn), .addr(alu_result), .data_in(busB_out), .data_out(ram_data_out)); + assign reg_write_data = MemToReg ? ram_data_out : alu_result; +endmodule \ No newline at end of file diff --git a/Experiments/Shared/Ext.v b/Experiments/Shared/Ext.v new file mode 100644 index 0000000..47eca25 --- /dev/null +++ b/Experiments/Shared/Ext.v @@ -0,0 +1,23 @@ +module Ext( + input [31:0] DataIn, + input [1:0] ExtOp, + output [31:0] DataOut +); + wire [31:0] imm12, imm16, imm20, imm26; + assign imm12 = {{20{DataIn[21]}}, DataIn[21:10]}; + assign imm16 = {{14{DataIn[25]}}, DataIn[25:10], 2'b0}; + assign imm20 = {DataIn[24:5], 12'b0}; + assign imm26 = {{4{DataIn[9]}}, DataIn[9:0], DataIn[25:10], 2'b0}; + + reg [31:0] temp_DataOut; + always @(*) begin + case (ExtOp) + 2'b00: temp_DataOut = imm12; + 2'b01: temp_DataOut = imm16; + 2'b10: temp_DataOut = imm20; + 2'b11: temp_DataOut = imm26; + default: temp_DataOut = 32'hxxxxxxxx; + endcase + end + assign DataOut = temp_DataOut; +endmodule \ No newline at end of file diff --git a/Experiments/Shared/LA32R_CPU.v b/Experiments/Shared/LA32R_CPU.v new file mode 100644 index 0000000..f1a4175 --- /dev/null +++ b/Experiments/Shared/LA32R_CPU.v @@ -0,0 +1,14 @@ +module LA32R_CPU( + input clk, + input [31:0] Instr +); + wire RegWr, MemToReg, MemWrEn, ALUBSrc, srcReg; + wire [1:0] ExtOp; + wire [2:0] AluCtrl; + wire Zero; + + Controller u_Controller(.Opcode_in(Instr[31:15]), .RegWr(RegWr), .MemToReg(MemToReg), .MemWrEn(MemWrEn), + .ALUBSrc(ALUBSrc), .srcReg(srcReg), .ExtOp(ExtOp), .AluCtrl(AluCtrl)); + Datapath u_Datapath(.clk(clk), .Instr(Instr), .RegWr(RegWr), .MemToReg(MemToReg), .MemWrEn(MemWrEn), + .ALUBSrc(ALUBSrc), .srcReg(srcReg), .ExtOp(ExtOp), .AluCtrl(AluCtrl), .Zero(Zero)); +endmodule \ No newline at end of file diff --git a/Experiments/Shared/PC.v b/Experiments/Shared/PC.v new file mode 100644 index 0000000..fcd4bcd --- /dev/null +++ b/Experiments/Shared/PC.v @@ -0,0 +1,19 @@ +module PC( + input clk, + input rst, + input pc_inc, + input [31:0] offset, + output reg [31:0] PCdata +); + always @(posedge clk or posedge rst) begin + if (rst) begin + PCdata <= 32'd0; + end else begin + if (pc_inc) begin + PCdata <= PCdata + 4; + end else begin + PCdata <= PCdata + offset; + end + end + end +endmodule \ No newline at end of file diff --git a/Experiments/Shared/Registers.v b/Experiments/Shared/Registers.v new file mode 100644 index 0000000..313ea8d --- /dev/null +++ b/Experiments/Shared/Registers.v @@ -0,0 +1,25 @@ +module Registers( + input clk, + input RegWr, + input [4:0] Ra, Rb, Rw, + input [31:0] busW, + output [31:0] busA, + output [31:0] busB +); + reg [31:0] regs[0:31]; + integer i; + initial begin + for (i = 0; i < 32; i = i + 1) begin + regs[i] = 32'd0; + end + end + + always @(posedge clk) begin + if (RegWr && (Rw != 5'd0)) begin + regs[Rw] <= busW; + end + end + + assign busA = (Ra == 5'd0) ? 32'd0 : regs[Ra]; + assign busB = (Rb == 5'd0) ? 32'd0 : regs[Rb]; +endmodule \ No newline at end of file