`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/05/30 20:49:51
// Design Name: 
// Module Name: Registers
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Registers (
    input  wire        clk,
    input  wire        RegWr,
    input  wire [4:0]  Ra,
    input  wire [4:0]  Rb,
    input  wire [4:0]  Rw,
    input  wire [31:0] busW,
    output wire [31:0] busA,
    output wire [31:0] busB
);
    reg [31:0] register_file [31:0];
    always @(posedge clk) begin
        if (RegWr && (Rw != 5'b00000)) begin
            register_file[Rw] <= busW;
        end
    end
    assign busA = (Ra == 5'b00000) ? 32'h00000000 : register_file[Ra];
    assign busB = (Rb == 5'b00000) ? 32'h00000000 : register_file[Rb];
endmodule