44 lines
961 B
Verilog
44 lines
961 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2025/05/30 20:48:55
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// Design Name:
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// Module Name: PC
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module PC (
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input wire rst,
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input wire clk,
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input wire [31:0] offset,
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input wire pc_inc,
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output reg [31:0] PCdata
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);
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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PCdata <= 32'h00000000;
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end
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else begin
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if (pc_inc) begin
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PCdata <= PCdata + 1;
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end
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else begin
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PCdata <= PCdata + offset;
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end
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end
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end
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endmodule
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