38 lines
849 B
Verilog
38 lines
849 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2025/05/30 20:50:37
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// Design Name:
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// Module Name: RAM
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module RAM (
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input wire clk,
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input wire MemWrEn,
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input wire [31:0] addr,
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input wire [31:0] data_in,
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output wire [31:0] data_out
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);
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reg [31:0] memory_array [2^32-1:0];
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always @(posedge clk) begin
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if (MemWrEn) begin
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memory_array[addr] <= data_in;
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end
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end
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assign data_out = memory_array[addr];
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endmodule
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