17 lines
380 B
Verilog
17 lines
380 B
Verilog
module DataRAM(
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input clk,
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input MemWrEn,
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input [31:0] addr,
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input [31:0] data_in,
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output [31:0] data_out
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);
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reg [31:0] ram[0:1023];
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wire [9:0] word_addr = addr[11:2];
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always @(posedge clk) begin
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if (MemWrEn) begin
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ram[word_addr] <= data_in;
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end
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end
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assign data_out = ram[word_addr];
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endmodule |