76 lines
1.8 KiB
Verilog
76 lines
1.8 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2025/06/06 15:26:45
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// Design Name:
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// Module Name: Datapath
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module DataPath (
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input wire clk,
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input wire rst,
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input wire [31:0] Instr,
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input wire srcReg,
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input wire ALUBsrc,
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input wire MemToReg,
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input wire RegWr,
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input wire MemWrEn,
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input wire [2:0] ALUop,
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input wire [1:0] Extop
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);
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wire [4:0] rd = Instr[4:0];
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wire [4:0] rj = Instr[9:5];
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wire [4:0] rk = Instr[14:10];
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wire [31:0] immExt;
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Ext u_ext (
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.DataIn (Instr),
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.Extop (Extop),
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.DataOut(immExt)
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);
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wire [4:0] Rb_sel = srcReg ? rd : rk;
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wire [31:0] busA, busB_reg;
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wire [31:0] WriteData;
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Registers u_regs (
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.clk (clk),
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.RegWr(RegWr),
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.Ra (rj),
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.Rb (Rb_sel),
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.Rw (rd),
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.busW (WriteData),
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.busA (busA),
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.busB (busB_reg)
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);
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wire [31:0] aluB = ALUBsrc ? immExt : busB_reg;
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wire [31:0] aluResult;
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wire aluZero;
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ALU u_alu (
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.a (busA),
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.b (aluB),
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.op (ALUop),
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.result (aluResult),
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.Zero (aluZero)
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);
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wire [31:0] ramDataOut;
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DataRAM u_dram (
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.clk (clk),
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.MemWrEn (MemWrEn),
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.addr (aluResult),
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.data_in (busB_reg),
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.data_out(ramDataOut)
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);
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assign WriteData = MemToReg ? ramDataOut : aluResult;
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endmodule |