43 lines
1.3 KiB
Verilog
43 lines
1.3 KiB
Verilog
module Controller(
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input [31:15] Opcode_in,
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output reg RegWr,
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output reg MemToReg,
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output reg MemWrEn,
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output reg ALUBSrc,
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output reg srcReg,
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output reg [1:0] ExtOp,
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output reg [2:0] AluCtrl
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);
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parameter OP_RTYPE = 3'b000, OP_LU12I = 3'b001, OP_LOAD = 3'b010, OP_STORE = 3'b011;
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parameter FUNC_ADD = 7'b0000010, FUNC_SLT = 7'b0000100, FUNC_SLTU= 7'b0000101;
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wire [2:0] main_op = Opcode_in[31:29];
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wire [6:0] func_op = Opcode_in[21:15];
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always @(*) begin
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RegWr=0; MemToReg=0; MemWrEn=0; ALUBSrc=0; srcReg=0; ExtOp=2'bxx; AluCtrl=3'bxxx;
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case(main_op)
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OP_RTYPE: begin
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RegWr=1; ALUBSrc=0;
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case(func_op)
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FUNC_ADD: AluCtrl = 3'b000;
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FUNC_SLT: AluCtrl = 3'b101;
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FUNC_SLTU: AluCtrl = 3'b110;
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default: ;
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endcase
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end
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OP_LU12I: begin
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RegWr=1; ALUBSrc=1; ExtOp=2'b10; AluCtrl=3'b111;
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end
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OP_LOAD: begin
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RegWr=1; MemToReg=1; ALUBSrc=1; ExtOp=2'b00; AluCtrl=3'b000;
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end
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OP_STORE: begin
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MemWrEn=1; ALUBSrc=1; srcReg=1; ExtOp=2'b00; AluCtrl=3'b000;
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end
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default: ;
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endcase
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end
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endmodule |