19 lines
447 B
Verilog
19 lines
447 B
Verilog
module PC(
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input clk,
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input rst,
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input pc_inc,
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input [31:0] offset,
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output reg [31:0] PCdata
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);
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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PCdata <= 32'd0;
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end else begin
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if (pc_inc) begin
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PCdata <= PCdata + 4;
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end else begin
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PCdata <= PCdata + offset;
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end
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end
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end
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endmodule |