25 lines
560 B
Verilog
25 lines
560 B
Verilog
module Registers(
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input clk,
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input RegWr,
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input [4:0] Ra, Rb, Rw,
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input [31:0] busW,
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output [31:0] busA,
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output [31:0] busB
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);
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reg [31:0] regs[0:31];
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integer i;
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initial begin
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for (i = 0; i < 32; i = i + 1) begin
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regs[i] = 32'd0;
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end
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end
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always @(posedge clk) begin
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if (RegWr && (Rw != 5'd0)) begin
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regs[Rw] <= busW;
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end
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end
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assign busA = (Ra == 5'd0) ? 32'd0 : regs[Ra];
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assign busB = (Rb == 5'd0) ? 32'd0 : regs[Rb];
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endmodule |