`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/12/05 11:21:41
// Design Name: 
// Module Name: slow_clock
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module slow_clock(clk, reset, speed_ctrl, clk_out);
    input clk, reset, speed_ctrl;
    output reg clk_out;
    parameter sys_clk = 100_000_000;
    parameter clk_slow = 1;
    parameter clk_fast = 5;
    parameter max_slow = sys_clk / (2 * clk_slow) - 1;
//  parameter max_slow = 10 - 1; // for simulation
    parameter max_fast = sys_clk / (2 * clk_fast) - 1;
//  parameter max_fast = 5 - 1; // for simulation
    reg [25:0] counter;
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            counter <= 0;
            clk_out <= 0;
        end
        else begin
            if (speed_ctrl == 0) begin
                if (counter == max_slow) begin
                    counter <= 0;
                    clk_out <= ~clk_out;
                end
                else begin
                    counter <= counter + 1;
                end
            end
            else if (speed_ctrl == 1) begin
                if (counter == max_fast) begin
                    counter <= 0;
                    clk_out <= ~clk_out;
                end
                else begin
                    counter <= counter + 1;
                end
            end
        end
    end
endmodule
