`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 2024/10/18 21:46:41
// Design Name: 
// Module Name: CoreModule
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module CoreModule(
    input wire [4:0] votes,
    output reg [2:0] count,
    output reg pass
);
integer i;
always @(*) begin
    count = 0;
    for (i = 0; i < 5; i = i + 1)
        count = count + votes[i];
    pass = (count >= 3);
end
endmodule
