`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 2024/12/01 22:50:46
// Design Name: 
// Module Name: counter_10
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
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// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
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module counter_10 (clrn, clk, enp, ent, ldn, din, qout, rco);
    // clrn: Asynchronous clear (active low)
    // clk: Clock signal
    // ent: Enable counting terminal
    // enp: Enable counting parallel
    // ldn: Load enable (active low)
    // din: Input data
    // qout: Current counter value
    // rco: Ripple Carry Out
    parameter din_width = 'd4;
    parameter qout_width = 'd4;
    parameter counter_size = 'd10;
    input clrn, clk, ent, enp, ldn;
    input [din_width - 1 : 0] din;
    output [qout_width - 1 : 0] qout;
    output rco;
    reg [qout_width - 1 : 0] qout;
    always @(posedge clk or negedge clrn) begin
        if (~clrn) qout <= 0; // Async clear
        else if (!ldn) qout <= din; // Async preset initial value
        else if (enp && ent == 1)
            if (qout == counter_size - 1) qout <= 0; // If maximum clear
            else qout <= qout + 1; // Counter ++
        else qout <= qout; // Keep
    end
    assign rco = (qout == counter_size - 1 && ent) ? 1 : 0; // Output highest bit
endmodule
