`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/12/04 22:53:45
// Design Name: 
// Module Name: slowClock
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module slowClock(
    input clk,
    input reset,
    output reg clk_1Hz,
    output reg clk_12Hz,
    output reg clk_48Hz,
    output reg clk_190Hz
);

parameter sys_clk = 100_000_000;  // 100 MHz
parameter clk_out1 = 1;
parameter clk_out12 = 12;
parameter clk_out48 = 48;
parameter clk_out190 = 190;

parameter max1 = sys_clk / (2 * clk_out1) - 1;
parameter max12 = sys_clk / (2 * clk_out12) - 1;
parameter max48 = sys_clk / (2 * clk_out48) - 1;
parameter max190 = sys_clk / (2 * clk_out190) - 1;

reg [25:0] counter1Hz;
reg [22:0] counter12Hz;
reg [20:0] counter48Hz;
reg [18:0] counter190Hz;

always @(posedge clk or posedge reset) begin
    if (reset) begin
        counter1Hz <= 0;
        clk_1Hz <= 0;
        counter12Hz <= 0;
        clk_12Hz <= 0;
        counter48Hz <= 0;
        clk_48Hz <= 0;
        counter190Hz <= 0;
        clk_190Hz <= 0;
    end
    else begin
        // 1 Hz
        if (counter1Hz == max1) begin
            counter1Hz <= 0;
            clk_1Hz <= ~clk_1Hz;
        end
        else begin
            counter1Hz <= counter1Hz + 1;
        end
        // 12 Hz
        if (counter12Hz == max12) begin
            counter12Hz <= 0;
            clk_12Hz <= ~clk_12Hz;
        end
        else begin
            counter12Hz <= counter12Hz + 1;
        end
        // 48 Hz
        if (counter48Hz == max48) begin
            counter48Hz <= 0;
            clk_48Hz <= ~clk_48Hz;
        end
        else begin
            counter48Hz <= counter48Hz + 1;
        end
        // 190 Hz
        if (counter190Hz == max190) begin
            counter190Hz <= 0;
            clk_190Hz <= ~clk_190Hz;
        end
        else begin
            counter190Hz <= counter190Hz + 1;
        end
    end
end
endmodule
