`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/12/16 15:44:41
// Design Name: 
// Module Name: slow
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module clk(clk,rst,clk_1HZ,clk_20kHZ);
input clk,rst;
output clk_1HZ,clk_20kHZ;
reg clk_1HZ,clk_20kHZ;
reg [25:0]counter1;
reg [11:0]counter20k;
parameter sys_clk=100_000_000;
parameter clk_out1=1;
parameter clk_out20k=20_000;
parameter max1=sys_clk/(2*clk_out1)-1;
parameter max20k=sys_clk/(2*clk_out20k)-1;
always@(posedge clk or posedge rst) begin
if(rst)begin
clk_1HZ<=0;
clk_20kHZ<=0;
counter1<=0;
counter20k<=0;
end
else
begin
 if(counter20k==max20k)begin
  clk_20kHZ<=~clk_20kHZ;
  counter20k<=0;
  end
 else
 counter20k<=(counter20k)+1;
 if(counter1==max1)begin
  clk_1HZ<=~clk_1HZ;
  counter1<=0;
  end
  else
  counter1<=(counter1)+1;
 end
end
endmodule
