`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/12/01 23:02:08
// Design Name: 
// Module Name: counter_10_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module counter_10_tb;
reg clrn, clk, enp, ldn, ent;
reg [3:0] din;
wire [3:0] qout;
wire rco;
counter_10 dut (
    .clrn(clrn), 
    .clk(clk),
    .enp(enp),
    .ent(ent),
    .ldn(ldn),
    .din(din),
    .qout(qout),
    .rco(rco)
);
always #5 clk = ~clk;
initial begin
    // Initialize inputs
    clrn = 1'b1;
    clk = 1'b0;
    enp = 1'b0;
    ent = 1'b1;
    ldn = 1'b1;
    din = 4'b0000;
    // Test async reset
    #10 clrn = 1'b0;
    #10 clrn = 1'b1;
    // Test async preset
    #10 ldn = 1'b0;
    din = 4'b1001;
    #10 ldn = 1'b1;
    // Test counting up
    #10 enp = 1'b1;
    repeat (15) #10;
    // Test holding
    #10 enp = 1'b0;
    repeat (5) #10;
    $finish;
end
endmodule
