`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/11/27 03:58:06
// Design Name: 
// Module Name: SyncDFlipFlop_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module SyncDFlipFlop_tb;
reg D, clk, rst, set;
wire Q;
SyncDFlipFlop uut (
    .D(D),
    .clk(clk),
    .rst(rst),
    .set(set),
    .Q(Q)
);
initial begin
    clk = 0;
    forever #10 clk = ~clk;
end
initial begin
    D = 0; rst = 0; set = 0; #15;
    // Reset test
    rst = 1; #20;
    rst = 0; #20;
    // Set test
    set = 1; #20;
    set = 0; #20;
    // Data input test
    D = 1; #30;
    D = 0; #30;
    $stop;
end
endmodule
