`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/12/05 11:33:38
// Design Name: 
// Module Name: shift_reg
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module shift_reg(reset, clk, direction_ctrl, cnt);
parameter CNT_SIZE = 16;
input reset, clk, direction_ctrl;
output reg [CNT_SIZE-1 : 0] cnt;
always @(posedge clk or posedge reset) begin
    if (reset)
    cnt <= 16'b0000000000000001;
    else begin
        if (direction_ctrl == 0)
            cnt <= {cnt[0], cnt[CNT_SIZE-1 : 1]};
        else
            cnt <= {cnt[CNT_SIZE-2 : 0], cnt[CNT_SIZE-1]};
    end
end
endmodule
