Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr  4 18:40:38 MDT 2018
| Date         : Thu Oct 31 10:39:44 2024
| Host         : W10-20240912132 running 64-bit major release  (build 9200)
| Command      : report_drc -file prior_encoder_drc_routed.rpt -pb prior_encoder_drc_routed.pb -rpx prior_encoder_drc_routed.rpx
| Design       : prior_encoder
| Device       : xc7a35tcsg324-1
| Speed File   : -1
| Design State : Routed
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Report DRC

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
           Ruledeck: default
             Max violations: <unlimited>
             Violations found: 3
+----------+----------+-----------------------------------------------------+------------+
| Rule     | Severity | Description                                         | Violations |
+----------+----------+-----------------------------------------------------+------------+
| CFGBVS-1 | Warning  | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1          |
| PDRC-153 | Warning  | Gated clock check                                   | 2          |
+----------+----------+-----------------------------------------------------+------------+

2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties  
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
Related violations: <none>

PDRC-153#1 Warning
Gated clock check  
Net Y_reg[2]_i_2_n_0 is a gated clock net sourced by a combinational pin Y_reg[2]_i_2/O, cell Y_reg[2]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PDRC-153#2 Warning
Gated clock check  
Net i_sig_reg[7]_i_2_n_0 is a gated clock net sourced by a combinational pin i_sig_reg[7]_i_2/O, cell i_sig_reg[7]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>


