Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr  4 18:40:38 MDT 2018
| Date         : Thu Oct 31 10:39:44 2024
| Host         : W10-20240912132 running 64-bit major release  (build 9200)
| Command      : report_methodology -file prior_encoder_methodology_drc_routed.rpt -pb prior_encoder_methodology_drc_routed.pb -rpx prior_encoder_methodology_drc_routed.rpx
| Design       : prior_encoder
| Device       : xc7a35tcsg324-1
| Speed File   : -1
| Design State : Routed
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Report Methodology

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
             Max violations: <unlimited>
             Violations found: 11
+-----------+----------+-------------------+------------+
| Rule      | Severity | Description       | Violations |
+-----------+----------+-------------------+------------+
| TIMING-20 | Warning  | Non-clocked latch | 11         |
+-----------+----------+-------------------+------------+

2. REPORT DETAILS
-----------------
TIMING-20#1 Warning
Non-clocked latch  
The latch Y_reg[0] cannot be properly analyzed as its control pin Y_reg[0]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#2 Warning
Non-clocked latch  
The latch Y_reg[1] cannot be properly analyzed as its control pin Y_reg[1]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#3 Warning
Non-clocked latch  
The latch Y_reg[2] cannot be properly analyzed as its control pin Y_reg[2]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#4 Warning
Non-clocked latch  
The latch i_sig_reg[0] cannot be properly analyzed as its control pin i_sig_reg[0]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#5 Warning
Non-clocked latch  
The latch i_sig_reg[1] cannot be properly analyzed as its control pin i_sig_reg[1]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#6 Warning
Non-clocked latch  
The latch i_sig_reg[2] cannot be properly analyzed as its control pin i_sig_reg[2]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#7 Warning
Non-clocked latch  
The latch i_sig_reg[3] cannot be properly analyzed as its control pin i_sig_reg[3]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#8 Warning
Non-clocked latch  
The latch i_sig_reg[4] cannot be properly analyzed as its control pin i_sig_reg[4]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#9 Warning
Non-clocked latch  
The latch i_sig_reg[5] cannot be properly analyzed as its control pin i_sig_reg[5]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#10 Warning
Non-clocked latch  
The latch i_sig_reg[6] cannot be properly analyzed as its control pin i_sig_reg[6]/G is not reached by a timing clock
Related violations: <none>

TIMING-20#11 Warning
Non-clocked latch  
The latch i_sig_reg[7] cannot be properly analyzed as its control pin i_sig_reg[7]/G is not reached by a timing clock
Related violations: <none>


