Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr  4 18:40:38 MDT 2018
| Date         : Thu Dec 12 11:43:41 2024
| Host         : W10-20240912132 running 64-bit major release  (build 9200)
| Command      : report_methodology -file counter_10_methodology_drc_routed.rpt -pb counter_10_methodology_drc_routed.pb -rpx counter_10_methodology_drc_routed.rpx
| Design       : counter_10
| Device       : xc7a35tcsg324-1
| Speed File   : -1
| Design State : Routed
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Report Methodology

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
             Max violations: <unlimited>
             Violations found: 4
+-----------+----------+-----------------------------+------------+
| Rule      | Severity | Description                 | Violations |
+-----------+----------+-----------------------------+------------+
| TIMING-17 | Warning  | Non-clocked sequential cell | 4          |
+-----------+----------+-----------------------------+------------+

2. REPORT DETAILS
-----------------
TIMING-17#1 Warning
Non-clocked sequential cell  
The clock pin qout_reg[0]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#2 Warning
Non-clocked sequential cell  
The clock pin qout_reg[1]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#3 Warning
Non-clocked sequential cell  
The clock pin qout_reg[2]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#4 Warning
Non-clocked sequential cell  
The clock pin qout_reg[3]/C is not reached by a timing clock
Related violations: <none>


