#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr  4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr  4 20:55:05 MDT 2018
# Start of session at: Thu Oct 31 10:39:06 2024
# Process ID: 10496
# Current directory: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1
# Command line: vivado.exe -log prior_encoder.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source prior_encoder.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder.vdi
# Journal file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source prior_encoder.tcl -notrace
Command: link_design -top prior_encoder -part xc7a35tcsg324-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.1
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/constrs_1/new/encoder.xdc]
Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/constrs_1/new/encoder.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 607.816 ; gain = 302.820
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.399 . Memory (MB): peak = 621.617 ; gain = 13.801
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1a0efe7be

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1169.441 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1a0efe7be

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1169.441 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 1a0efe7be

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1169.441 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 1a0efe7be

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1169.441 ; gain = 0.000
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 1a0efe7be

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1169.441 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 1a0efe7be

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1169.441 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells

Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1169.441 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1a0efe7be

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1169.441 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1a0efe7be

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1169.441 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1169.441 ; gain = 561.625
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1169.441 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file prior_encoder_drc_opted.rpt -pb prior_encoder_drc_opted.pb -rpx prior_encoder_drc_opted.rpx
Command: report_drc -file prior_encoder_drc_opted.rpt -pb prior_encoder_drc_opted.pb -rpx prior_encoder_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1169.441 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 10b3cc5b1

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1169.441 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1169.441 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 10b3cc5b1

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.462 . Memory (MB): peak = 1182.070 ; gain = 12.629

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1e2cf7632

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.472 . Memory (MB): peak = 1182.070 ; gain = 12.629

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1e2cf7632

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.473 . Memory (MB): peak = 1182.070 ; gain = 12.629
Phase 1 Placer Initialization | Checksum: 1e2cf7632

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.473 . Memory (MB): peak = 1182.070 ; gain = 12.629

Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 18e95721a

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.646 . Memory (MB): peak = 1182.070 ; gain = 12.629

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 18e95721a

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.647 . Memory (MB): peak = 1182.070 ; gain = 12.629

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1766832ee

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.655 . Memory (MB): peak = 1182.070 ; gain = 12.629

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1a96c420c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.658 . Memory (MB): peak = 1182.070 ; gain = 12.629

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1a96c420c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.659 . Memory (MB): peak = 1182.070 ; gain = 12.629

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 143829d4b

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.705 . Memory (MB): peak = 1182.070 ; gain = 12.629

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 143829d4b

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.707 . Memory (MB): peak = 1182.070 ; gain = 12.629

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 143829d4b

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.708 . Memory (MB): peak = 1182.070 ; gain = 12.629
Phase 3 Detail Placement | Checksum: 143829d4b

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.708 . Memory (MB): peak = 1182.070 ; gain = 12.629

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 143829d4b

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.710 . Memory (MB): peak = 1182.070 ; gain = 12.629

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 143829d4b

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.712 . Memory (MB): peak = 1182.070 ; gain = 12.629

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 143829d4b

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.712 . Memory (MB): peak = 1182.070 ; gain = 12.629

Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 143829d4b

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.713 . Memory (MB): peak = 1182.070 ; gain = 12.629
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 143829d4b

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.713 . Memory (MB): peak = 1182.070 ; gain = 12.629
Ending Placer Task | Checksum: e791b51c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.715 . Memory (MB): peak = 1182.070 ; gain = 12.629
INFO: [Common 17-83] Releasing license: Implementation
41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1182.070 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file prior_encoder_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1187.117 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file prior_encoder_utilization_placed.rpt -pb prior_encoder_utilization_placed.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1187.117 ; gain = 0.000
INFO: [runtcl-4] Executing : report_control_sets -verbose -file prior_encoder_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1187.117 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: d11c5d6 ConstDB: 0 ShapeSum: da7fef46 RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 112c02765

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1301.633 ; gain = 114.516
Post Restoration Checksum: NetGraph: 75abcc6c NumContArr: 9d145af9 Constraints: 0 Timing: 0

Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 112c02765

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1307.668 ; gain = 120.551

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 112c02765

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1307.668 ; gain = 120.551
 Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: 1c130cb9b

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.371 ; gain = 122.254

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 1243fa08a

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.371 ; gain = 122.254

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: 18460bc16

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281
Phase 4 Rip-up And Reroute | Checksum: 18460bc16

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281

Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: 18460bc16

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: 18460bc16

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281
Phase 6 Post Hold Fix | Checksum: 18460bc16

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.0509447 %
  Global Horizontal Routing Utilization  = 0.0118428 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Congestion Report
North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 39.6396%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 25%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions.

------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0

Phase 7 Route finalize | Checksum: 18460bc16

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 18460bc16

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1311.676 ; gain = 124.559

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: ab5fb207

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1311.676 ; gain = 124.559
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1311.676 ; gain = 124.559

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1311.676 ; gain = 124.559
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1311.676 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file prior_encoder_drc_routed.rpt -pb prior_encoder_drc_routed.pb -rpx prior_encoder_drc_routed.rpx
Command: report_drc -file prior_encoder_drc_routed.rpt -pb prior_encoder_drc_routed.pb -rpx prior_encoder_drc_routed.rpx
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file prior_encoder_methodology_drc_routed.rpt -pb prior_encoder_methodology_drc_routed.pb -rpx prior_encoder_methodology_drc_routed.rpx
Command: report_methodology -file prior_encoder_methodology_drc_routed.rpt -pb prior_encoder_methodology_drc_routed.pb -rpx prior_encoder_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file prior_encoder_power_routed.rpt -pb prior_encoder_power_summary_routed.pb -rpx prior_encoder_power_routed.rpx
Command: report_power -file prior_encoder_power_routed.rpt -pb prior_encoder_power_summary_routed.pb -rpx prior_encoder_power_routed.rpx
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file prior_encoder_route_status.rpt -pb prior_encoder_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file prior_encoder_timing_summary_routed.rpt -pb prior_encoder_timing_summary_routed.pb -rpx prior_encoder_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
INFO: [runtcl-4] Executing : report_incremental_reuse -file prior_encoder_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file prior_encoder_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Thu Oct 31 10:39:45 2024...
