commit 0bded5b86e0943ab19e9e2874b31164dfc344274 Author: Launchcore Date: Thu Nov 6 10:08:01 2025 +0800 Initial commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..52916fb --- /dev/null +++ b/.gitignore @@ -0,0 +1,134 @@ +### MicrosoftOffice ### +*.tmp + +# Word temporary +~$*.doc* + +# Word Auto Backup File +Backup of *.doc* + +# Excel temporary +~$*.xls* + +# Excel Backup File +*.xlk + +# PowerPoint temporary +~$*.ppt* + +# Visio autosave temporary files +*.~vsd* + +### VisualStudioCode ### +.vscode/* +!.vscode/settings.json +!.vscode/tasks.json +!.vscode/launch.json +!.vscode/extensions.json +!.vscode/*.code-snippets + +# Local History for Visual Studio Code +.history/ + +# Built Visual Studio Code Extensions +*.vsix + +### VisualStudioCode Patch ### +# Ignore all local history of files +.history +.ionide + +### Vivado ### +######################################################################################################### +## This is an example .gitignore file for Vivado, please treat it as an example as +## it might not be complete. In addition, XAPP 1165 should be followed. +######### +#Exclude all +* +!*/ +!Experiment Requirements/* +!Reports/* +!.gitignore +########################################################################### +## VIVADO +#Source files: +#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. +!*.vhd +!*.v +!*.sv +!*.bd +!*.edif +#IP files +#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products +#.xci + .dcp: implementation possible but not re-synthesis +#*.xci(www.spiritconsortium.org) +!*.xci +#.xcix: Core container file +#.xcix: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug896-vivado-ip.pdf (Page 41) +!*.xcix +#*.dcp(checkpoint files) +!*.dcp +!*.vds +!*.pb +#All bd comments and layout coordinates are stored within .ui +!*.ui +!*.ooc +#System Generator +!*.mdl +!*.slx +!*.bxml +#Simulation logic analyzer +!*.wcfg +!*.coe +#MIG +!*.prj +!*.mem +#Project files +#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version) +#Do NOT ignore *.xpr files +!*.xpr +#Include *.xml files for 2013.4 or earlier version +!*.xml +#Constraint files +#Do NOT ignore *.xdc files +!*.xdc +#TCL - files +!*.tcl +#Journal - files +!*.jou +#Reports +!*.rpt +!*.txt +!*.vdi +#C-files +!*.c +!*.h +!*.elf +!*.bmm +!*.xmp + +### Windows ### +# Windows thumbnail cache files +Thumbs.db +Thumbs.db:encryptable +ehthumbs.db +ehthumbs_vista.db + +# Dump file +*.stackdump + +# Folder config file +[Dd]esktop.ini + +# Recycle Bin used on file shares +$RECYCLE.BIN/ + +# Windows Installer files +*.cab +*.msi +*.msix +*.msm +*.msp + +# Windows shortcuts +*.lnk \ No newline at end of file diff --git a/Ch8421_Yv3/Ch8421_Yv3.cache/wt/webtalk_pa.xml b/Ch8421_Yv3/Ch8421_Yv3.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..0a80646 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.cache/wt/webtalk_pa.xml @@ -0,0 +1,82 @@ + + + + +
+ + +
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Ch8421_Yv3/Ch8421_Yv3.hw/hw_1/hw.xml b/Ch8421_Yv3/Ch8421_Yv3.hw/hw_1/hw.xml new file mode 100644 index 0000000..1e01a46 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/Ch8421_Yv3/Ch8421_Yv3.ip_user_files/README.txt b/Ch8421_Yv3/Ch8421_Yv3.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/.jobs/vrs_config_1.xml b/Ch8421_Yv3/Ch8421_Yv3.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..d2a5027 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/.jobs/vrs_config_2.xml b/Ch8421_Yv3/Ch8421_Yv3.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..ad85de4 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/.jobs/vrs_config_3.xml b/Ch8421_Yv3/Ch8421_Yv3.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..47f8782 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3.tcl b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3.tcl new file mode 100644 index 0000000..43616bc --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3.tcl @@ -0,0 +1,86 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + set_param synth.incrementalSynthesisCache C:/Users/Launchcore/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-15680-W10-20240912132/incrSyn + open_checkpoint Ch8421_Yv3_routed.dcp + set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.cache/wt [current_project] + catch { write_mem_info -force Ch8421_Yv3.mmi } + write_bitstream -force Ch8421_Yv3.bit + catch {write_debug_probes -quiet -force Ch8421_Yv3} + catch {file copy -force Ch8421_Yv3.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3.vdi b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3.vdi new file mode 100644 index 0000000..44346cb --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3.vdi @@ -0,0 +1,486 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 10 10:32:46 2024 +# Process ID: 11696 +# Current directory: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1 +# Command line: vivado.exe -log Ch8421_Yv3.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Ch8421_Yv3.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Ch8421_Yv3.tcl -notrace +Command: link_design -top Ch8421_Yv3 -part xc7a35tcsg324-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.srcs/constrs_1/new/Ch8421_Yv3.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.srcs/constrs_1/new/Ch8421_Yv3.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 607.328 ; gain = 302.281 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.077 . Memory (MB): peak = 609.395 ; gain = 2.066 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1119.109 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1119.109 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1119.109 ; gain = 511.781 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Ch8421_Yv3_drc_opted.rpt -pb Ch8421_Yv3_drc_opted.pb -rpx Ch8421_Yv3_drc_opted.rpx +Command: report_drc -file Ch8421_Yv3_drc_opted.rpt -pb Ch8421_Yv3_drc_opted.pb -rpx Ch8421_Yv3_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1131.883 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15ab95234 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1131.883 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1131.883 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15ab95234 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.409 . Memory (MB): peak = 1149.512 ; gain = 17.629 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1fe411adc + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.429 . Memory (MB): peak = 1149.512 ; gain = 17.629 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1fe411adc + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.431 . Memory (MB): peak = 1149.512 ; gain = 17.629 +Phase 1 Placer Initialization | Checksum: 1fe411adc + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.434 . Memory (MB): peak = 1149.512 ; gain = 17.629 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 167d22d82 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.623 . Memory (MB): peak = 1149.770 ; gain = 17.887 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 167d22d82 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.626 . Memory (MB): peak = 1149.770 ; gain = 17.887 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1f9a45945 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.634 . Memory (MB): peak = 1149.770 ; gain = 17.887 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 18873ea51 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.637 . Memory (MB): peak = 1149.770 ; gain = 17.887 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 18873ea51 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.637 . Memory (MB): peak = 1149.770 ; gain = 17.887 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.691 . Memory (MB): peak = 1152.586 ; gain = 20.703 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.692 . Memory (MB): peak = 1152.586 ; gain = 20.703 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.693 . Memory (MB): peak = 1152.586 ; gain = 20.703 +Phase 3 Detail Placement | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.693 . Memory (MB): peak = 1152.586 ; gain = 20.703 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.694 . Memory (MB): peak = 1152.586 ; gain = 20.703 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.700 . Memory (MB): peak = 1152.586 ; gain = 20.703 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.701 . Memory (MB): peak = 1152.586 ; gain = 20.703 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.701 . Memory (MB): peak = 1152.586 ; gain = 20.703 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.702 . Memory (MB): peak = 1152.586 ; gain = 20.703 +Ending Placer Task | Checksum: 1a459aa1e + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.704 . Memory (MB): peak = 1152.586 ; gain = 20.703 +INFO: [Common 17-83] Releasing license: Implementation +41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1152.945 ; gain = 0.359 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file Ch8421_Yv3_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1163.027 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file Ch8421_Yv3_utilization_placed.rpt -pb Ch8421_Yv3_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1163.027 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Ch8421_Yv3_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1163.027 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: d7cd8338 ConstDB: 0 ShapeSum: cc8c26e6 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 2ad64a48 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1284.242 ; gain = 121.215 +Post Restoration Checksum: NetGraph: 88edc5d NumContArr: 22476deb Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 2ad64a48 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1290.254 ; gain = 127.227 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 2ad64a48 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1290.254 ; gain = 127.227 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 117da245c + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.922 ; gain = 128.895 + +Phase 3 Initial Routing + Number of Nodes with overlaps = 0 +Phase 3 Initial Routing | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.926 ; gain = 128.898 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 +Phase 4.1 Global Iteration 0 | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.926 ; gain = 128.898 +Phase 4 Rip-up And Reroute | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.926 ; gain = 128.898 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.926 ; gain = 128.898 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.926 ; gain = 128.898 +Phase 6 Post Hold Fix | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.926 ; gain = 128.898 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0136331 % + Global Horizontal Routing Utilization = 0.00221239 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.926 ; gain = 128.898 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1294.242 ; gain = 131.215 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1294.242 ; gain = 131.215 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1294.242 ; gain = 131.215 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1294.242 ; gain = 131.215 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1294.242 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Ch8421_Yv3_drc_routed.rpt -pb Ch8421_Yv3_drc_routed.pb -rpx Ch8421_Yv3_drc_routed.rpx +Command: report_drc -file Ch8421_Yv3_drc_routed.rpt -pb Ch8421_Yv3_drc_routed.pb -rpx Ch8421_Yv3_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file Ch8421_Yv3_methodology_drc_routed.rpt -pb Ch8421_Yv3_methodology_drc_routed.pb -rpx Ch8421_Yv3_methodology_drc_routed.rpx +Command: report_methodology -file Ch8421_Yv3_methodology_drc_routed.rpt -pb Ch8421_Yv3_methodology_drc_routed.pb -rpx Ch8421_Yv3_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file Ch8421_Yv3_power_routed.rpt -pb Ch8421_Yv3_power_summary_routed.pb -rpx Ch8421_Yv3_power_routed.rpx +Command: report_power -file Ch8421_Yv3_power_routed.rpt -pb Ch8421_Yv3_power_summary_routed.pb -rpx Ch8421_Yv3_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file Ch8421_Yv3_route_status.rpt -pb Ch8421_Yv3_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Ch8421_Yv3_timing_summary_routed.rpt -pb Ch8421_Yv3_timing_summary_routed.pb -rpx Ch8421_Yv3_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file Ch8421_Yv3_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file Ch8421_Yv3_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Thu Oct 10 10:33:23 2024... +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 10 10:33:41 2024 +# Process ID: 12568 +# Current directory: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1 +# Command line: vivado.exe -log Ch8421_Yv3.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Ch8421_Yv3.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Ch8421_Yv3.tcl -notrace +Command: open_checkpoint Ch8421_Yv3_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 241.477 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1111.473 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1111.473 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600 +open_checkpoint: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1111.473 ; gain = 878.215 +Command: write_bitstream -force Ch8421_Yv3.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./Ch8421_Yv3.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +22 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1578.262 ; gain = 466.789 +INFO: [Common 17-206] Exiting Vivado at Thu Oct 10 10:34:13 2024... diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_11696.backup.vdi b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_11696.backup.vdi new file mode 100644 index 0000000..8dbe457 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_11696.backup.vdi @@ -0,0 +1,415 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 10 10:32:46 2024 +# Process ID: 11696 +# Current directory: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1 +# Command line: vivado.exe -log Ch8421_Yv3.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Ch8421_Yv3.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Ch8421_Yv3.tcl -notrace +Command: link_design -top Ch8421_Yv3 -part xc7a35tcsg324-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.srcs/constrs_1/new/Ch8421_Yv3.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.srcs/constrs_1/new/Ch8421_Yv3.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 607.328 ; gain = 302.281 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.077 . Memory (MB): peak = 609.395 ; gain = 2.066 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1119.109 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1119.109 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1b28f8f1c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1119.109 ; gain = 511.781 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1119.109 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Ch8421_Yv3_drc_opted.rpt -pb Ch8421_Yv3_drc_opted.pb -rpx Ch8421_Yv3_drc_opted.rpx +Command: report_drc -file Ch8421_Yv3_drc_opted.rpt -pb Ch8421_Yv3_drc_opted.pb -rpx Ch8421_Yv3_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1131.883 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15ab95234 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1131.883 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1131.883 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15ab95234 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.409 . Memory (MB): peak = 1149.512 ; gain = 17.629 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1fe411adc + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.429 . Memory (MB): peak = 1149.512 ; gain = 17.629 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1fe411adc + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.431 . Memory (MB): peak = 1149.512 ; gain = 17.629 +Phase 1 Placer Initialization | Checksum: 1fe411adc + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.434 . Memory (MB): peak = 1149.512 ; gain = 17.629 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 167d22d82 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.623 . Memory (MB): peak = 1149.770 ; gain = 17.887 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 167d22d82 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.626 . Memory (MB): peak = 1149.770 ; gain = 17.887 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1f9a45945 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.634 . Memory (MB): peak = 1149.770 ; gain = 17.887 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 18873ea51 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.637 . Memory (MB): peak = 1149.770 ; gain = 17.887 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 18873ea51 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.637 . Memory (MB): peak = 1149.770 ; gain = 17.887 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.691 . Memory (MB): peak = 1152.586 ; gain = 20.703 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.692 . Memory (MB): peak = 1152.586 ; gain = 20.703 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.693 . Memory (MB): peak = 1152.586 ; gain = 20.703 +Phase 3 Detail Placement | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.693 . Memory (MB): peak = 1152.586 ; gain = 20.703 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.694 . Memory (MB): peak = 1152.586 ; gain = 20.703 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.700 . Memory (MB): peak = 1152.586 ; gain = 20.703 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.701 . Memory (MB): peak = 1152.586 ; gain = 20.703 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.701 . Memory (MB): peak = 1152.586 ; gain = 20.703 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1a4c354f1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.702 . Memory (MB): peak = 1152.586 ; gain = 20.703 +Ending Placer Task | Checksum: 1a459aa1e + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.704 . Memory (MB): peak = 1152.586 ; gain = 20.703 +INFO: [Common 17-83] Releasing license: Implementation +41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1152.945 ; gain = 0.359 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file Ch8421_Yv3_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1163.027 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file Ch8421_Yv3_utilization_placed.rpt -pb Ch8421_Yv3_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1163.027 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file Ch8421_Yv3_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1163.027 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: d7cd8338 ConstDB: 0 ShapeSum: cc8c26e6 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 2ad64a48 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1284.242 ; gain = 121.215 +Post Restoration Checksum: NetGraph: 88edc5d NumContArr: 22476deb Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 2ad64a48 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1290.254 ; gain = 127.227 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 2ad64a48 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1290.254 ; gain = 127.227 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 117da245c + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.922 ; gain = 128.895 + +Phase 3 Initial Routing + Number of Nodes with overlaps = 0 +Phase 3 Initial Routing | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.926 ; gain = 128.898 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 +Phase 4.1 Global Iteration 0 | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.926 ; gain = 128.898 +Phase 4 Rip-up And Reroute | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.926 ; gain = 128.898 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.926 ; gain = 128.898 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.926 ; gain = 128.898 +Phase 6 Post Hold Fix | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.926 ; gain = 128.898 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0136331 % + Global Horizontal Routing Utilization = 0.00221239 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.926 ; gain = 128.898 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1294.242 ; gain = 131.215 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 152bf75dc + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1294.242 ; gain = 131.215 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1294.242 ; gain = 131.215 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1294.242 ; gain = 131.215 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1294.242 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file Ch8421_Yv3_drc_routed.rpt -pb Ch8421_Yv3_drc_routed.pb -rpx Ch8421_Yv3_drc_routed.rpx +Command: report_drc -file Ch8421_Yv3_drc_routed.rpt -pb Ch8421_Yv3_drc_routed.pb -rpx Ch8421_Yv3_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file Ch8421_Yv3_methodology_drc_routed.rpt -pb Ch8421_Yv3_methodology_drc_routed.pb -rpx Ch8421_Yv3_methodology_drc_routed.rpx +Command: report_methodology -file Ch8421_Yv3_methodology_drc_routed.rpt -pb Ch8421_Yv3_methodology_drc_routed.pb -rpx Ch8421_Yv3_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file Ch8421_Yv3_power_routed.rpt -pb Ch8421_Yv3_power_summary_routed.pb -rpx Ch8421_Yv3_power_routed.rpx +Command: report_power -file Ch8421_Yv3_power_routed.rpt -pb Ch8421_Yv3_power_summary_routed.pb -rpx Ch8421_Yv3_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file Ch8421_Yv3_route_status.rpt -pb Ch8421_Yv3_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Ch8421_Yv3_timing_summary_routed.rpt -pb Ch8421_Yv3_timing_summary_routed.pb -rpx Ch8421_Yv3_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file Ch8421_Yv3_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file Ch8421_Yv3_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Thu Oct 10 10:33:23 2024... diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_clock_utilization_routed.rpt b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_clock_utilization_routed.rpt new file mode 100644 index 0000000..3e969d0 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_clock_utilization_routed.rpt @@ -0,0 +1,92 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 10 10:33:23 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file Ch8421_Yv3_clock_utilization_routed.rpt +| Design : Ch8421_Yv3 +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +---------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 0 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_control_sets_placed.rpt b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_control_sets_placed.rpt new file mode 100644 index 0000000..30f8979 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_control_sets_placed.rpt @@ -0,0 +1,61 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 10 10:33:09 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file Ch8421_Yv3_control_sets_placed.rpt +| Design : Ch8421_Yv3 +| Device : xc7a35t +--------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 0 | +| Unused register locations in slices containing registers | 0 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++--------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++--------------+---------------+------------------+------------------+----------------+ + + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_opted.pb b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_opted.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_opted.rpt b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_opted.rpt new file mode 100644 index 0000000..d8c8cc6 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 10 10:33:08 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file Ch8421_Yv3_drc_opted.rpt -pb Ch8421_Yv3_drc_opted.pb -rpx Ch8421_Yv3_drc_opted.rpx +| Design : Ch8421_Yv3 +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_routed.pb b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_routed.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_routed.rpt b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_routed.rpt new file mode 100644 index 0000000..2de5c5c --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_drc_routed.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 10 10:33:22 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file Ch8421_Yv3_drc_routed.rpt -pb Ch8421_Yv3_drc_routed.pb -rpx Ch8421_Yv3_drc_routed.rpx +| Design : Ch8421_Yv3 +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_io_placed.rpt b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_io_placed.rpt new file mode 100644 index 0000000..1661edb --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_io_placed.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 10 10:33:09 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_io -file Ch8421_Yv3_io_placed.rpt +| Design : Ch8421_Yv3 +| Device : xc7a35t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2013-12-19 +| Package Pin Delay Version : VERS. 2.0 2013-12-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 8 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | Yout[3] | High Range | IO_L19N_T3_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | Yout[1] | High Range | IO_L20N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G4 | Yout[2] | High Range | IO_L20P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J4 | Yout[0] | High Range | IO_L21P_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N4 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | Bin[0] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P3 | Bin[1] | High Range | IO_L14N_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P4 | Bin[2] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P5 | Bin[3] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R2 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_methodology_drc_routed.pb b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_methodology_drc_routed.pb new file mode 100644 index 0000000..210b56b Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_methodology_drc_routed.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_methodology_drc_routed.rpt b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_methodology_drc_routed.rpt new file mode 100644 index 0000000..3ec6194 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_methodology_drc_routed.rpt @@ -0,0 +1,34 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 10 10:33:22 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_methodology -file Ch8421_Yv3_methodology_drc_routed.rpt -pb Ch8421_Yv3_methodology_drc_routed.pb -rpx Ch8421_Yv3_methodology_drc_routed.rpx +| Design : Ch8421_Yv3 +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 0 ++------+----------+-------------+------------+ +| Rule | Severity | Description | Violations | ++------+----------+-------------+------------+ ++------+----------+-------------+------------+ + +2. REPORT DETAILS +----------------- + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_opt.dcp b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_opt.dcp new file mode 100644 index 0000000..6d9d064 Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_opt.dcp differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_placed.dcp b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_placed.dcp new file mode 100644 index 0000000..3e5cf5f Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_placed.dcp differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_power_routed.rpt b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_power_routed.rpt new file mode 100644 index 0000000..f050a8e --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_power_routed.rpt @@ -0,0 +1,140 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 10 10:33:23 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_power -file Ch8421_Yv3_power_routed.rpt -pb Ch8421_Yv3_power_summary_routed.pb -rpx Ch8421_Yv3_power_routed.rpx +| Design : Ch8421_Yv3 +| Device : xc7a35tcsg324-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 4.238 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 4.153 | +| Device Static (W) | 0.085 | +| Effective TJA (C/W) | 4.8 | +| Max Ambient (C) | 64.7 | +| Junction Temperature (C) | 45.3 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.013 | 4 | --- | --- | +| LUT as Logic | 0.013 | 2 | 20800 | <0.01 | +| Signals | 0.054 | 8 | --- | --- | +| I/O | 4.086 | 8 | 210 | 3.81 | +| Static Power | 0.085 | | | | +| Total | 4.238 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.104 | 0.083 | 0.021 | +| Vccaux | 1.800 | 0.163 | 0.149 | 0.014 | +| Vcco33 | 3.300 | 1.153 | 1.152 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.8 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------------+-----------+ +| Name | Power (W) | ++------------+-----------+ +| Ch8421_Yv3 | 4.153 | ++------------+-----------+ + + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_power_summary_routed.pb b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_power_summary_routed.pb new file mode 100644 index 0000000..d3050fc Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_power_summary_routed.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_route_status.pb b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_route_status.pb new file mode 100644 index 0000000..e975e2c Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_route_status.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_route_status.rpt b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_route_status.rpt new file mode 100644 index 0000000..3a4cce0 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 16 : + # of nets not needing routing.......... : 8 : + # of internally routed nets........ : 8 : + # of routable nets..................... : 8 : + # of fully routed nets............. : 8 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_routed.dcp b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_routed.dcp new file mode 100644 index 0000000..0f9a255 Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_routed.dcp differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_timing_summary_routed.pb b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_timing_summary_routed.pb new file mode 100644 index 0000000..4526e93 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_timing_summary_routed.rpt b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_timing_summary_routed.rpt new file mode 100644 index 0000000..5c9c293 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_timing_summary_routed.rpt @@ -0,0 +1,173 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 10 10:33:23 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file Ch8421_Yv3_timing_summary_routed.rpt -pb Ch8421_Yv3_timing_summary_routed.pb -rpx Ch8421_Yv3_timing_summary_routed.rpx -warn_on_violation +| Design : Ch8421_Yv3 +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 0 register/latch pins with no clock. + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 0 ports with no output delay specified. + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_utilization_placed.pb b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_utilization_placed.pb new file mode 100644 index 0000000..0c28293 Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_utilization_placed.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_utilization_placed.rpt b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_utilization_placed.rpt new file mode 100644 index 0000000..ac53c6c --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3_utilization_placed.rpt @@ -0,0 +1,194 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 10 10:33:09 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file Ch8421_Yv3_utilization_placed.rpt -pb Ch8421_Yv3_utilization_placed.pb +| Design : Ch8421_Yv3 +| Device : 7a35tcsg324-1 +| Design State : Fully Placed +----------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 2 | 0 | 20800 | <0.01 | +| LUT as Logic | 2 | 0 | 20800 | <0.01 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++--------------------------+------+-------+-----------+-------+ +| Slice | 1 | 0 | 8150 | 0.01 | +| SLICEL | 1 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 2 | 0 | 20800 | <0.01 | +| using O5 output only | 0 | | | | +| using O6 output only | 0 | | | | +| using O5 and O6 | 2 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 0 | 0 | 20800 | 0.00 | +| Unique Control Sets | 0 | | | | ++--------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 8 | 8 | 210 | 3.81 | +| IOB Master Pads | 4 | | | | +| IOB Slave Pads | 4 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 4 | IO | +| LUT4 | 4 | LUT | +| IBUF | 4 | IO | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/gen_run.xml b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..0bdb7a4 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/gen_run.xml @@ -0,0 +1,108 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/htr.txt b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/htr.txt new file mode 100644 index 0000000..44997ae --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log Ch8421_Yv3.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source Ch8421_Yv3.tcl -notrace diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/init_design.pb b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/init_design.pb new file mode 100644 index 0000000..b8ea8bc Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/init_design.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/opt_design.pb b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..74d48d9 Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/opt_design.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/place_design.pb b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/place_design.pb new file mode 100644 index 0000000..061f8ac Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/place_design.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/route_design.pb b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/route_design.pb new file mode 100644 index 0000000..78913a5 Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/route_design.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/route_report_bus_skew_0.rpt b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/route_report_bus_skew_0.rpt new file mode 100644 index 0000000..96555f6 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/route_report_bus_skew_0.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 10 10:33:23 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +| Design : Ch8421_Yv3 +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/usage_statistics_webtalk.xml b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..592e152 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,403 @@ + + +
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+ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/vivado.jou b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/vivado.jou new file mode 100644 index 0000000..a1d1c6f --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 10 10:33:41 2024 +# Process ID: 12568 +# Current directory: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1 +# Command line: vivado.exe -log Ch8421_Yv3.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Ch8421_Yv3.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Ch8421_Yv3.tcl -notrace diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/vivado.pb b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/vivado.pb new file mode 100644 index 0000000..df77956 Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/vivado.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/vivado_11696.backup.jou b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/vivado_11696.backup.jou new file mode 100644 index 0000000..7c040f9 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/vivado_11696.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 10 10:32:46 2024 +# Process ID: 11696 +# Current directory: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1 +# Command line: vivado.exe -log Ch8421_Yv3.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Ch8421_Yv3.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/Ch8421_Yv3.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source Ch8421_Yv3.tcl -notrace diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/write_bitstream.pb b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..0d962d8 Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/impl_1/write_bitstream.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/.Xil/Ch8421_Yv3_propImpl.xdc b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/.Xil/Ch8421_Yv3_propImpl.xdc new file mode 100644 index 0000000..af94e71 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/.Xil/Ch8421_Yv3_propImpl.xdc @@ -0,0 +1,17 @@ +set_property SRC_FILE_INFO {cfile:F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.srcs/constrs_1/new/Ch8421_Yv3.xdc rfile:../../../Ch8421_Yv3.srcs/constrs_1/new/Ch8421_Yv3.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P5 [get_ports {Bin[3]}] +set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P4 [get_ports {Bin[2]}] +set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P3 [get_ports {Bin[1]}] +set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P2 [get_ports {Bin[0]}] +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F6 [get_ports {Yout[3]}] +set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G4 [get_ports {Yout[2]}] +set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G3 [get_ports {Yout[1]}] +set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J4 [get_ports {Yout[0]}] diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3.dcp b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3.dcp new file mode 100644 index 0000000..293ef24 Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3.dcp differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3.tcl b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3.tcl new file mode 100644 index 0000000..422a87f --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3.tcl @@ -0,0 +1,56 @@ +# +# Synthesis run script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param synth.incrementalSynthesisCache C:/Users/Launchcore/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-15680-W10-20240912132/incrSyn +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 +create_project -in_memory -part xc7a35tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.cache/wt [current_project] +set_property parent.project_path F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo f:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.srcs/sources_1/new/Ch8421_Yv3.v +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.srcs/constrs_1/new/Ch8421_Yv3.xdc +set_property used_in_implementation false [get_files F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.srcs/constrs_1/new/Ch8421_Yv3.xdc] + +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top Ch8421_Yv3 -part xc7a35tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef Ch8421_Yv3.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file Ch8421_Yv3_utilization_synth.rpt -pb Ch8421_Yv3_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3.vds b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3.vds new file mode 100644 index 0000000..bb0345c --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3.vds @@ -0,0 +1,266 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 10 10:32:12 2024 +# Process ID: 10172 +# Current directory: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1 +# Command line: vivado.exe -log Ch8421_Yv3.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Ch8421_Yv3.tcl +# Log file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3.vds +# Journal file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source Ch8421_Yv3.tcl -notrace +Command: synth_design -top Ch8421_Yv3 -part xc7a35tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 14728 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 409.441 ; gain = 97.836 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'Ch8421_Yv3' [F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.srcs/sources_1/new/Ch8421_Yv3.v:23] +INFO: [Synth 8-6155] done synthesizing module 'Ch8421_Yv3' (1#1) [F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.srcs/sources_1/new/Ch8421_Yv3.v:23] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 464.355 ; gain = 152.750 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 464.355 ; gain = 152.750 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 464.355 ; gain = 152.750 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.srcs/constrs_1/new/Ch8421_Yv3.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.srcs/constrs_1/new/Ch8421_Yv3.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.srcs/constrs_1/new/Ch8421_Yv3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Ch8421_Yv3_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/Ch8421_Yv3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 714.117 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 714.117 ; gain = 402.512 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 714.117 ; gain = 402.512 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 714.117 ; gain = 402.512 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 714.117 ; gain = 402.512 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Muxes : + 2 Input 4 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module Ch8421_Yv3 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Muxes : + 2 Input 4 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 714.117 ; gain = 402.512 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 782.711 ; gain = 471.105 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 782.711 ; gain = 471.105 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 782.711 ; gain = 471.105 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 783.836 ; gain = 472.230 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 783.836 ; gain = 472.230 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 783.836 ; gain = 472.230 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 783.836 ; gain = 472.230 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 783.836 ; gain = 472.230 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 783.836 ; gain = 472.230 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT4 | 4| +|2 |IBUF | 4| +|3 |OBUF | 4| ++------+-----+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 12| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 783.836 ; gain = 472.230 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 783.855 ; gain = 222.488 +Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 783.855 ; gain = 472.250 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 801.379 ; gain = 502.652 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file Ch8421_Yv3_utilization_synth.rpt -pb Ch8421_Yv3_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 801.379 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Thu Oct 10 10:32:40 2024... diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3_utilization_synth.pb b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3_utilization_synth.pb new file mode 100644 index 0000000..0c28293 Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3_utilization_synth.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3_utilization_synth.rpt b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3_utilization_synth.rpt new file mode 100644 index 0000000..6699e77 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3_utilization_synth.rpt @@ -0,0 +1,170 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 10 10:32:40 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file Ch8421_Yv3_utilization_synth.rpt -pb Ch8421_Yv3_utilization_synth.pb +| Design : Ch8421_Yv3 +| Device : 7a35tcsg324-1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 2 | 0 | 20800 | <0.01 | +| LUT as Logic | 2 | 0 | 20800 | <0.01 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 8 | 0 | 210 | 3.81 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 4 | IO | +| LUT4 | 4 | LUT | +| IBUF | 4 | IO | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/gen_run.xml b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..b70c7fd --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/gen_run.xml @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/htr.txt b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/htr.txt new file mode 100644 index 0000000..a813377 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log Ch8421_Yv3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Ch8421_Yv3.tcl diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/vivado.jou b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/vivado.jou new file mode 100644 index 0000000..7b4b5fa --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 10 10:32:12 2024 +# Process ID: 10172 +# Current directory: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1 +# Command line: vivado.exe -log Ch8421_Yv3.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Ch8421_Yv3.tcl +# Log file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/Ch8421_Yv3.vds +# Journal file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source Ch8421_Yv3.tcl -notrace diff --git a/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/vivado.pb b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/vivado.pb new file mode 100644 index 0000000..823c797 Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.runs/synth_1/vivado.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/Ch8421_Yv3_sim.tcl b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/Ch8421_Yv3_sim.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/Ch8421_Yv3_sim.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/Ch8421_Yv3_sim_vlog.prj b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/Ch8421_Yv3_sim_vlog.prj new file mode 100644 index 0000000..a1e6dd6 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/Ch8421_Yv3_sim_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Ch8421_Yv3.srcs/sources_1/new/Ch8421_Yv3.v" \ +"../../../../Ch8421_Yv3.srcs/sim_1/new/Ch8421_Yv3_sim.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/glbl.v b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/webtalk.jou b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..b8da134 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 10 10:27:04 2024 +# Process ID: 13556 +# Current directory: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/webtalk_11660.backup.jou b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/webtalk_11660.backup.jou new file mode 100644 index 0000000..8799de2 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/webtalk_11660.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 10 10:26:09 2024 +# Process ID: 11660 +# Current directory: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xelab.pb b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..892f353 Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/Compile_Options.txt b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/Compile_Options.txt new file mode 100644 index 0000000..f02b9d6 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "c58c6cced222491c88b85f0093378b33" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "Ch8421_Yv3_sim_behav" "xil_defaultlib.Ch8421_Yv3_sim" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/TempBreakPointFile.txt b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/obj/xsim_1.c b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/obj/xsim_1.c new file mode 100644 index 0000000..447a742 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/obj/xsim_1.c @@ -0,0 +1,107 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_3(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[13] = {(funcp)execute_4, (funcp)execute_9, (funcp)execute_10, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 13; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/Ch8421_Yv3_sim_behav/xsim.reloc", (void **)funcTab, 13); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/Ch8421_Yv3_sim_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/Ch8421_Yv3_sim_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/Ch8421_Yv3_sim_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/Ch8421_Yv3_sim_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/Ch8421_Yv3_sim_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/webtalk/xsim_webtalk.tcl b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..f743258 --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Thu Oct 10 10:40:16 2024" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.1 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2188600" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "78ec1a93-fd1a-4b14-8c4b-87f04256706b" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "c58c6cced222491c88b85f0093378b33" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "13th Gen Intel(R) Core(TM) i7-13700H" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2918 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "3" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.01_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6476_KB" -context "xsim\\usage" +webtalk_transmit -clientid 4132081234 -regid "" -xml F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/webtalk/usage_statistics_ext_xsim.xml -html F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/webtalk/usage_statistics_ext_xsim.html -wdm F:/Schoolwork/DigitalLogic/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/xsim.mem b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/xsim.mem new file mode 100644 index 0000000..e6ea82c Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xsim.dir/Ch8421_Yv3_sim_behav/xsim.mem differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xvlog.pb b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..03a193c Binary files /dev/null and b/Ch8421_Yv3/Ch8421_Yv3.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Ch8421_Yv3/Ch8421_Yv3.srcs/constrs_1/new/Ch8421_Yv3.xdc b/Ch8421_Yv3/Ch8421_Yv3.srcs/constrs_1/new/Ch8421_Yv3.xdc new file mode 100644 index 0000000..341516e --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.srcs/constrs_1/new/Ch8421_Yv3.xdc @@ -0,0 +1,16 @@ +set_property IOSTANDARD LVCMOS33 [get_ports {Bin[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {Bin[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {Bin[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {Bin[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {Yout[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {Yout[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {Yout[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {Yout[0]}] +set_property PACKAGE_PIN P5 [get_ports {Bin[3]}] +set_property PACKAGE_PIN P4 [get_ports {Bin[2]}] +set_property PACKAGE_PIN P3 [get_ports {Bin[1]}] +set_property PACKAGE_PIN P2 [get_ports {Bin[0]}] +set_property PACKAGE_PIN F6 [get_ports {Yout[3]}] +set_property PACKAGE_PIN G4 [get_ports {Yout[2]}] +set_property PACKAGE_PIN G3 [get_ports {Yout[1]}] +set_property PACKAGE_PIN J4 [get_ports {Yout[0]}] diff --git a/Ch8421_Yv3/Ch8421_Yv3.srcs/sim_1/new/Ch8421_Yv3_sim.v b/Ch8421_Yv3/Ch8421_Yv3.srcs/sim_1/new/Ch8421_Yv3_sim.v new file mode 100644 index 0000000..665430c --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.srcs/sim_1/new/Ch8421_Yv3_sim.v @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/10 10:17:39 +// Design Name: +// Module Name: Ch8421_Yv3_sim +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Ch8421_Yv3_sim(); +reg [3:0] Bin; +wire [3:0] Yout; +Ch8421_Yv3 U1(.Bin(Bin), .Yout(Yout)); +initial begin + Bin <= 4'b0000;#100; + Bin <= 4'b0001;#100; + Bin <= 4'b0010;#100; + Bin <= 4'b0011;#100; + Bin <= 4'b0100;#100; + Bin <= 4'b0101;#100; + Bin <= 4'b0110;#100; + Bin <= 4'b0111;#100; + Bin <= 4'b1000;#100; + Bin <= 4'b1001;#100; + Bin <= 4'b1010;#100; + Bin <= 4'b1011;#100; + Bin <= 4'b1100;#100; + Bin <= 4'b1101;#100; + Bin <= 4'b1110;#100; + Bin <= 4'b1111;#100; + $stop; +end +endmodule diff --git a/Ch8421_Yv3/Ch8421_Yv3.srcs/sources_1/new/Ch8421_Yv3.v b/Ch8421_Yv3/Ch8421_Yv3.srcs/sources_1/new/Ch8421_Yv3.v new file mode 100644 index 0000000..9eafffa --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.srcs/sources_1/new/Ch8421_Yv3.v @@ -0,0 +1,31 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/10 10:12:57 +// Design Name: +// Module Name: Ch8421_Yv3 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Ch8421_Yv3(Bin, Yout); +input [3:0] Bin; +output [3:0] Yout; +reg [3:0] Yout; +always @ (Bin) + if (Bin <= 4'b1001) + Yout = Bin + 4'b0011; + else Yout = 0; +endmodule diff --git a/Ch8421_Yv3/Ch8421_Yv3.xpr b/Ch8421_Yv3/Ch8421_Yv3.xpr new file mode 100644 index 0000000..689a1ee --- /dev/null +++ b/Ch8421_Yv3/Ch8421_Yv3.xpr @@ -0,0 +1,154 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + diff --git a/Exp1-1/Exp1-1.cache/wt/webtalk_pa.xml b/Exp1-1/Exp1-1.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..970dddf --- /dev/null +++ b/Exp1-1/Exp1-1.cache/wt/webtalk_pa.xml @@ -0,0 +1,116 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp1-1/Exp1-1.hw/hw_1/hw.xml b/Exp1-1/Exp1-1.hw/hw_1/hw.xml new file mode 100644 index 0000000..560b225 --- /dev/null +++ b/Exp1-1/Exp1-1.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/Exp1-1/Exp1-1.ip_user_files/README.txt b/Exp1-1/Exp1-1.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp1-1/Exp1-1.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp1-1/Exp1-1.runs/.jobs/vrs_config_1.xml b/Exp1-1/Exp1-1.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..12bc238 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp1-1/Exp1-1.runs/.jobs/vrs_config_2.xml b/Exp1-1/Exp1-1.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..12bc238 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp1-1/Exp1-1.runs/.jobs/vrs_config_3.xml b/Exp1-1/Exp1-1.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..fb291d3 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp1-1/Exp1-1.runs/.jobs/vrs_config_4.xml b/Exp1-1/Exp1-1.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..bcccec3 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp1-1/Exp1-1.runs/impl_1/First.dcp b/Exp1-1/Exp1-1.runs/impl_1/First.dcp new file mode 100644 index 0000000..b7e9476 Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/First.dcp differ diff --git a/Exp1-1/Exp1-1.runs/impl_1/First.tcl b/Exp1-1/Exp1-1.runs/impl_1/First.tcl new file mode 100644 index 0000000..548d7f2 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/First.tcl @@ -0,0 +1,85 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + open_checkpoint First_routed.dcp + set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.cache/wt [current_project] + catch { write_mem_info -force First.mmi } + write_bitstream -force First.bit + catch {write_debug_probes -quiet -force First} + catch {file copy -force First.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/Exp1-1/Exp1-1.runs/impl_1/First.vdi b/Exp1-1/Exp1-1.runs/impl_1/First.vdi new file mode 100644 index 0000000..166f61b --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/First.vdi @@ -0,0 +1,493 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Tue Sep 24 00:22:33 2024 +# Process ID: 19852 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1 +# Command line: vivado.exe -log First.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source First.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source First.tcl -notrace +Command: open_checkpoint F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 241.242 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 1099.980 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 1099.980 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600 +open_checkpoint: Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1099.980 ; gain = 868.191 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1099.980 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1137.699 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1137.699 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +27 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file First_drc_opted.rpt -pb First_drc_opted.pb -rpx First_drc_opted.rpx +Command: report_drc -file First_drc_opted.rpt -pb First_drc_opted.pb -rpx First_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1137.699 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 18dfe7e25 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1137.699 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1137.699 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 18dfe7e25 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.309 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1942d72c6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.329 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1942d72c6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.331 . Memory (MB): peak = 1157.098 ; gain = 19.398 +Phase 1 Placer Initialization | Checksum: 1942d72c6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.333 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 1cfe9802f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.502 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1cfe9802f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.505 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 289bfdd74 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.513 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 2886e9116 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.516 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 2886e9116 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.517 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.570 . Memory (MB): peak = 1158.414 ; gain = 20.715 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.571 . Memory (MB): peak = 1158.414 ; gain = 20.715 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.571 . Memory (MB): peak = 1158.414 ; gain = 20.715 +Phase 3 Detail Placement | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.571 . Memory (MB): peak = 1158.414 ; gain = 20.715 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.573 . Memory (MB): peak = 1158.414 ; gain = 20.715 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.577 . Memory (MB): peak = 1158.414 ; gain = 20.715 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.577 . Memory (MB): peak = 1158.414 ; gain = 20.715 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.578 . Memory (MB): peak = 1158.414 ; gain = 20.715 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.578 . Memory (MB): peak = 1158.414 ; gain = 20.715 +Ending Placer Task | Checksum: 1bae7ddf2 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.580 . Memory (MB): peak = 1158.414 ; gain = 20.715 +INFO: [Common 17-83] Releasing license: Implementation +45 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1158.980 ; gain = 0.566 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file First_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1170.895 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file First_utilization_placed.rpt -pb First_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1170.895 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file First_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1170.895 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: ca68b55c ConstDB: 0 ShapeSum: f07f2896 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 1301fb540 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.113 ; gain = 120.219 +Post Restoration Checksum: NetGraph: 52fc159b NumContArr: dd239fa5 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 1301fb540 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1297.188 ; gain = 126.293 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 1301fb540 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1297.188 ; gain = 126.293 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 83588c97 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 + +Phase 3 Initial Routing + Number of Nodes with overlaps = 0 +Phase 3 Initial Routing | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 +Phase 4.1 Global Iteration 0 | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 +Phase 4 Rip-up And Reroute | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 +Phase 6 Post Hold Fix | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0083712 % + Global Horizontal Routing Utilization = 0.00130141 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1300.949 ; gain = 130.055 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 11ec72554 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1300.949 ; gain = 130.055 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1300.949 ; gain = 130.055 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +58 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1300.949 ; gain = 130.055 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1300.949 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file First_drc_routed.rpt -pb First_drc_routed.pb -rpx First_drc_routed.rpx +Command: report_drc -file First_drc_routed.rpt -pb First_drc_routed.pb -rpx First_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file First_methodology_drc_routed.rpt -pb First_methodology_drc_routed.pb -rpx First_methodology_drc_routed.rpx +Command: report_methodology -file First_methodology_drc_routed.rpt -pb First_methodology_drc_routed.pb -rpx First_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file First_power_routed.rpt -pb First_power_summary_routed.pb -rpx First_power_routed.rpx +Command: report_power -file First_power_routed.rpt -pb First_power_summary_routed.pb -rpx First_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +70 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file First_route_status.rpt -pb First_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file First_timing_summary_routed.rpt -pb First_timing_summary_routed.pb -rpx First_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file First_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file First_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Tue Sep 24 00:23:08 2024... +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Tue Sep 24 00:23:31 2024 +# Process ID: 15576 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1 +# Command line: vivado.exe -log First.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source First.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source First.tcl -notrace +Command: open_checkpoint First_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 241.449 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.062 . Memory (MB): peak = 1114.562 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.062 . Memory (MB): peak = 1114.562 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600 +open_checkpoint: Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1114.562 ; gain = 882.195 +Command: write_bitstream -force First.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./First.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +22 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1576.922 ; gain = 462.359 +INFO: [Common 17-206] Exiting Vivado at Tue Sep 24 00:24:02 2024... diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_19852.backup.vdi b/Exp1-1/Exp1-1.runs/impl_1/First_19852.backup.vdi new file mode 100644 index 0000000..3168df8 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/First_19852.backup.vdi @@ -0,0 +1,422 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Tue Sep 24 00:22:33 2024 +# Process ID: 19852 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1 +# Command line: vivado.exe -log First.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source First.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source First.tcl -notrace +Command: open_checkpoint F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 241.242 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 1099.980 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 1099.980 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600 +open_checkpoint: Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1099.980 ; gain = 868.191 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1099.980 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1137.699 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1137.699 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 251693d56 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +27 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1137.699 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file First_drc_opted.rpt -pb First_drc_opted.pb -rpx First_drc_opted.rpx +Command: report_drc -file First_drc_opted.rpt -pb First_drc_opted.pb -rpx First_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1137.699 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 18dfe7e25 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1137.699 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1137.699 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 18dfe7e25 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.309 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1942d72c6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.329 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1942d72c6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.331 . Memory (MB): peak = 1157.098 ; gain = 19.398 +Phase 1 Placer Initialization | Checksum: 1942d72c6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.333 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 1cfe9802f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.502 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1cfe9802f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.505 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 289bfdd74 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.513 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 2886e9116 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.516 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 2886e9116 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.517 . Memory (MB): peak = 1157.098 ; gain = 19.398 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.570 . Memory (MB): peak = 1158.414 ; gain = 20.715 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.571 . Memory (MB): peak = 1158.414 ; gain = 20.715 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.571 . Memory (MB): peak = 1158.414 ; gain = 20.715 +Phase 3 Detail Placement | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.571 . Memory (MB): peak = 1158.414 ; gain = 20.715 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.573 . Memory (MB): peak = 1158.414 ; gain = 20.715 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.577 . Memory (MB): peak = 1158.414 ; gain = 20.715 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.577 . Memory (MB): peak = 1158.414 ; gain = 20.715 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.578 . Memory (MB): peak = 1158.414 ; gain = 20.715 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1e3740440 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.578 . Memory (MB): peak = 1158.414 ; gain = 20.715 +Ending Placer Task | Checksum: 1bae7ddf2 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.580 . Memory (MB): peak = 1158.414 ; gain = 20.715 +INFO: [Common 17-83] Releasing license: Implementation +45 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1158.980 ; gain = 0.566 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file First_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1170.895 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file First_utilization_placed.rpt -pb First_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1170.895 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file First_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1170.895 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: ca68b55c ConstDB: 0 ShapeSum: f07f2896 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 1301fb540 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.113 ; gain = 120.219 +Post Restoration Checksum: NetGraph: 52fc159b NumContArr: dd239fa5 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 1301fb540 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1297.188 ; gain = 126.293 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 1301fb540 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1297.188 ; gain = 126.293 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 83588c97 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 + +Phase 3 Initial Routing + Number of Nodes with overlaps = 0 +Phase 3 Initial Routing | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 +Phase 4.1 Global Iteration 0 | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 +Phase 4 Rip-up And Reroute | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 +Phase 6 Post Hold Fix | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0083712 % + Global Horizontal Routing Utilization = 0.00130141 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1298.887 ; gain = 127.992 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 13b99d89f + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1300.949 ; gain = 130.055 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 11ec72554 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1300.949 ; gain = 130.055 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1300.949 ; gain = 130.055 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +58 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1300.949 ; gain = 130.055 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1300.949 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file First_drc_routed.rpt -pb First_drc_routed.pb -rpx First_drc_routed.rpx +Command: report_drc -file First_drc_routed.rpt -pb First_drc_routed.pb -rpx First_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file First_methodology_drc_routed.rpt -pb First_methodology_drc_routed.pb -rpx First_methodology_drc_routed.rpx +Command: report_methodology -file First_methodology_drc_routed.rpt -pb First_methodology_drc_routed.pb -rpx First_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file First_power_routed.rpt -pb First_power_summary_routed.pb -rpx First_power_routed.rpx +Command: report_power -file First_power_routed.rpt -pb First_power_summary_routed.pb -rpx First_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +70 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file First_route_status.rpt -pb First_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file First_timing_summary_routed.rpt -pb First_timing_summary_routed.pb -rpx First_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file First_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file First_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Tue Sep 24 00:23:08 2024... diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_clock_utilization_routed.rpt b/Exp1-1/Exp1-1.runs/impl_1/First_clock_utilization_routed.rpt new file mode 100644 index 0000000..52a20f8 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/First_clock_utilization_routed.rpt @@ -0,0 +1,92 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Tue Sep 24 00:23:08 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file First_clock_utilization_routed.rpt +| Design : First +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +------------------------------------------------------------------------------------ + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 0 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_control_sets_placed.rpt b/Exp1-1/Exp1-1.runs/impl_1/First_control_sets_placed.rpt new file mode 100644 index 0000000..c7557a6 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/First_control_sets_placed.rpt @@ -0,0 +1,61 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Tue Sep 24 00:22:55 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file First_control_sets_placed.rpt +| Design : First +| Device : xc7a35t +------------------------------------------------------------------------------------ + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 0 | +| Unused register locations in slices containing registers | 0 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++--------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++--------------+---------------+------------------+------------------+----------------+ + + diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_drc_opted.pb b/Exp1-1/Exp1-1.runs/impl_1/First_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/First_drc_opted.pb differ diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_drc_opted.rpt b/Exp1-1/Exp1-1.runs/impl_1/First_drc_opted.rpt new file mode 100644 index 0000000..caa17d1 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/First_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Tue Sep 24 00:22:54 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file First_drc_opted.rpt -pb First_drc_opted.pb -rpx First_drc_opted.rpx +| Design : First +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: checkpoint_First + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_drc_routed.pb b/Exp1-1/Exp1-1.runs/impl_1/First_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/First_drc_routed.pb differ diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_drc_routed.rpt b/Exp1-1/Exp1-1.runs/impl_1/First_drc_routed.rpt new file mode 100644 index 0000000..0d6e2f5 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/First_drc_routed.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Tue Sep 24 00:23:08 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file First_drc_routed.rpt -pb First_drc_routed.pb -rpx First_drc_routed.rpx +| Design : First +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +--------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: checkpoint_First + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_io_placed.rpt b/Exp1-1/Exp1-1.runs/impl_1/First_io_placed.rpt new file mode 100644 index 0000000..55fb6ea --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/First_io_placed.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Tue Sep 24 00:22:55 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_io -file First_io_placed.rpt +| Design : First +| Device : xc7a35t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2013-12-19 +| Package Pin Delay Version : VERS. 2.0 2013-12-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 5 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | z[1] | High Range | IO_L22N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J3 | z[2] | High Range | IO_L22P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | z[0] | High Range | IO_L23P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N4 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| P3 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P4 | b | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P5 | a | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R2 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_methodology_drc_routed.pb b/Exp1-1/Exp1-1.runs/impl_1/First_methodology_drc_routed.pb new file mode 100644 index 0000000..210b56b Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/First_methodology_drc_routed.pb differ diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_methodology_drc_routed.rpt b/Exp1-1/Exp1-1.runs/impl_1/First_methodology_drc_routed.rpt new file mode 100644 index 0000000..f67018a --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/First_methodology_drc_routed.rpt @@ -0,0 +1,34 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Tue Sep 24 00:23:08 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_methodology -file First_methodology_drc_routed.rpt -pb First_methodology_drc_routed.pb -rpx First_methodology_drc_routed.rpx +| Design : First +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +----------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: checkpoint_First + Design limits: + Max violations: + Violations found: 0 ++------+----------+-------------+------------+ +| Rule | Severity | Description | Violations | ++------+----------+-------------+------------+ ++------+----------+-------------+------------+ + +2. REPORT DETAILS +----------------- + diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_opt.dcp b/Exp1-1/Exp1-1.runs/impl_1/First_opt.dcp new file mode 100644 index 0000000..d6b22db Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/First_opt.dcp differ diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_placed.dcp b/Exp1-1/Exp1-1.runs/impl_1/First_placed.dcp new file mode 100644 index 0000000..35413cb Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/First_placed.dcp differ diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_power_routed.rpt b/Exp1-1/Exp1-1.runs/impl_1/First_power_routed.rpt new file mode 100644 index 0000000..b14aaed --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/First_power_routed.rpt @@ -0,0 +1,140 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Tue Sep 24 00:23:08 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_power -file First_power_routed.rpt -pb First_power_summary_routed.pb -rpx First_power_routed.rpx +| Design : First +| Device : xc7a35tcsg324-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 2.758 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 2.679 | +| Device Static (W) | 0.079 | +| Effective TJA (C/W) | 4.8 | +| Max Ambient (C) | 71.8 | +| Junction Temperature (C) | 38.2 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.007 | 3 | --- | --- | +| LUT as Logic | 0.007 | 2 | 20800 | <0.01 | +| Signals | 0.023 | 5 | --- | --- | +| I/O | 2.649 | 5 | 210 | 2.38 | +| Static Power | 0.079 | | | | +| Total | 2.758 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.054 | 0.038 | 0.016 | +| Vccaux | 1.800 | 0.110 | 0.097 | 0.013 | +| Vcco33 | 3.300 | 0.749 | 0.748 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.8 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++-------+-----------+ +| Name | Power (W) | ++-------+-----------+ +| First | 2.679 | ++-------+-----------+ + + diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_power_summary_routed.pb b/Exp1-1/Exp1-1.runs/impl_1/First_power_summary_routed.pb new file mode 100644 index 0000000..79dc161 Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/First_power_summary_routed.pb differ diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_route_status.pb b/Exp1-1/Exp1-1.runs/impl_1/First_route_status.pb new file mode 100644 index 0000000..0ca4a85 Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/First_route_status.pb differ diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_route_status.rpt b/Exp1-1/Exp1-1.runs/impl_1/First_route_status.rpt new file mode 100644 index 0000000..861acdd --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/First_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 10 : + # of nets not needing routing.......... : 5 : + # of internally routed nets........ : 5 : + # of routable nets..................... : 5 : + # of fully routed nets............. : 5 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_routed.dcp b/Exp1-1/Exp1-1.runs/impl_1/First_routed.dcp new file mode 100644 index 0000000..e0918ba Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/First_routed.dcp differ diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_timing_summary_routed.pb b/Exp1-1/Exp1-1.runs/impl_1/First_timing_summary_routed.pb new file mode 100644 index 0000000..4526e93 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/First_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_timing_summary_routed.rpt b/Exp1-1/Exp1-1.runs/impl_1/First_timing_summary_routed.rpt new file mode 100644 index 0000000..8f146db --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/First_timing_summary_routed.rpt @@ -0,0 +1,173 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Tue Sep 24 00:23:08 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file First_timing_summary_routed.rpt -pb First_timing_summary_routed.pb -rpx First_timing_summary_routed.rpx -warn_on_violation +| Design : First +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 0 register/latch pins with no clock. + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 0 ports with no output delay specified. + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_utilization_placed.pb b/Exp1-1/Exp1-1.runs/impl_1/First_utilization_placed.pb new file mode 100644 index 0000000..72816d6 Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/First_utilization_placed.pb differ diff --git a/Exp1-1/Exp1-1.runs/impl_1/First_utilization_placed.rpt b/Exp1-1/Exp1-1.runs/impl_1/First_utilization_placed.rpt new file mode 100644 index 0000000..46e0914 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/First_utilization_placed.rpt @@ -0,0 +1,194 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Tue Sep 24 00:22:55 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file First_utilization_placed.rpt -pb First_utilization_placed.pb +| Design : First +| Device : 7a35tcsg324-1 +| Design State : Fully Placed +------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 2 | 0 | 20800 | <0.01 | +| LUT as Logic | 2 | 0 | 20800 | <0.01 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++--------------------------+------+-------+-----------+-------+ +| Slice | 1 | 0 | 8150 | 0.01 | +| SLICEL | 1 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 2 | 0 | 20800 | <0.01 | +| using O5 output only | 0 | | | | +| using O6 output only | 1 | | | | +| using O5 and O6 | 1 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 0 | 0 | 20800 | 0.00 | +| Unique Control Sets | 0 | | | | ++--------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 5 | 5 | 210 | 2.38 | +| IOB Master Pads | 3 | | | | +| IOB Slave Pads | 2 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 3 | IO | +| LUT2 | 3 | LUT | +| IBUF | 2 | IO | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp1-1/Exp1-1.runs/impl_1/gen_run.xml b/Exp1-1/Exp1-1.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..c1dee00 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/gen_run.xml @@ -0,0 +1,91 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp1-1/Exp1-1.runs/impl_1/htr.txt b/Exp1-1/Exp1-1.runs/impl_1/htr.txt new file mode 100644 index 0000000..5d31023 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log First.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source First.tcl -notrace diff --git a/Exp1-1/Exp1-1.runs/impl_1/init_design.pb b/Exp1-1/Exp1-1.runs/impl_1/init_design.pb new file mode 100644 index 0000000..15f3100 Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/init_design.pb differ diff --git a/Exp1-1/Exp1-1.runs/impl_1/opt_design.pb b/Exp1-1/Exp1-1.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..790a1bd Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/opt_design.pb differ diff --git a/Exp1-1/Exp1-1.runs/impl_1/place_design.pb b/Exp1-1/Exp1-1.runs/impl_1/place_design.pb new file mode 100644 index 0000000..f68441a Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/place_design.pb differ diff --git a/Exp1-1/Exp1-1.runs/impl_1/route_design.pb b/Exp1-1/Exp1-1.runs/impl_1/route_design.pb new file mode 100644 index 0000000..a64e006 Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/route_design.pb differ diff --git a/Exp1-1/Exp1-1.runs/impl_1/route_report_bus_skew_0.rpt b/Exp1-1/Exp1-1.runs/impl_1/route_report_bus_skew_0.rpt new file mode 100644 index 0000000..e646fdc --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/route_report_bus_skew_0.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Tue Sep 24 00:23:08 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +| Design : First +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/Exp1-1/Exp1-1.runs/impl_1/usage_statistics_webtalk.xml b/Exp1-1/Exp1-1.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..9a6c089 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,425 @@ + + +
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+ diff --git a/Exp1-1/Exp1-1.runs/impl_1/vivado.jou b/Exp1-1/Exp1-1.runs/impl_1/vivado.jou new file mode 100644 index 0000000..775bb80 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Tue Sep 24 00:23:31 2024 +# Process ID: 15576 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1 +# Command line: vivado.exe -log First.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source First.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source First.tcl -notrace diff --git a/Exp1-1/Exp1-1.runs/impl_1/vivado.pb b/Exp1-1/Exp1-1.runs/impl_1/vivado.pb new file mode 100644 index 0000000..b79a5fd Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/vivado.pb differ diff --git a/Exp1-1/Exp1-1.runs/impl_1/vivado_19852.backup.jou b/Exp1-1/Exp1-1.runs/impl_1/vivado_19852.backup.jou new file mode 100644 index 0000000..2044e31 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/impl_1/vivado_19852.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Tue Sep 24 00:22:33 2024 +# Process ID: 19852 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1 +# Command line: vivado.exe -log First.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source First.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1/First.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source First.tcl -notrace diff --git a/Exp1-1/Exp1-1.runs/impl_1/write_bitstream.pb b/Exp1-1/Exp1-1.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..0ca9820 Binary files /dev/null and b/Exp1-1/Exp1-1.runs/impl_1/write_bitstream.pb differ diff --git a/Exp1-1/Exp1-1.runs/synth_1/.Xil/First_propImpl.xdc b/Exp1-1/Exp1-1.runs/synth_1/.Xil/First_propImpl.xdc new file mode 100644 index 0000000..8d90ebc --- /dev/null +++ b/Exp1-1/Exp1-1.runs/synth_1/.Xil/First_propImpl.xdc @@ -0,0 +1,11 @@ +set_property SRC_FILE_INFO {cfile:F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.srcs/constrs_1/new/EX1.xdc rfile:../../../Exp1-1.srcs/constrs_1/new/EX1.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J3 [get_ports {z[2]}] +set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J2 [get_ports {z[1]}] +set_property src_info {type:XDC file:1 line:3 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN K2 [get_ports {z[0]}] +set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P5 [get_ports a] +set_property src_info {type:XDC file:1 line:5 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P4 [get_ports b] diff --git a/Exp1-1/Exp1-1.runs/synth_1/First.dcp b/Exp1-1/Exp1-1.runs/synth_1/First.dcp new file mode 100644 index 0000000..27124a1 Binary files /dev/null and b/Exp1-1/Exp1-1.runs/synth_1/First.dcp differ diff --git a/Exp1-1/Exp1-1.runs/synth_1/First.tcl b/Exp1-1/Exp1-1.runs/synth_1/First.tcl new file mode 100644 index 0000000..abc7785 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/synth_1/First.tcl @@ -0,0 +1,56 @@ +# +# Synthesis run script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param synth.incrementalSynthesisCache C:/Users/Launchcore/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-19684-W10-20240912132/incrSyn +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 +create_project -in_memory -part xc7a35tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.cache/wt [current_project] +set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.srcs/sources_1/new/First.v +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.srcs/constrs_1/new/EX1.xdc +set_property used_in_implementation false [get_files F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.srcs/constrs_1/new/EX1.xdc] + +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top First -part xc7a35tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef First.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file First_utilization_synth.rpt -pb First_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/Exp1-1/Exp1-1.runs/synth_1/First.vds b/Exp1-1/Exp1-1.runs/synth_1/First.vds new file mode 100644 index 0000000..ccce2f9 --- /dev/null +++ b/Exp1-1/Exp1-1.runs/synth_1/First.vds @@ -0,0 +1,262 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Tue Sep 24 00:20:53 2024 +# Process ID: 13976 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/synth_1 +# Command line: vivado.exe -log First.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source First.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/synth_1/First.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source First.tcl -notrace +Command: synth_design -top First -part xc7a35tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 5984 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 409.785 ; gain = 97.684 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'First' [F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.srcs/sources_1/new/First.v:23] +INFO: [Synth 8-6155] done synthesizing module 'First' (1#1) [F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.srcs/sources_1/new/First.v:23] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 464.949 ; gain = 152.848 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 464.949 ; gain = 152.848 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 464.949 ; gain = 152.848 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.srcs/constrs_1/new/EX1.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.srcs/constrs_1/new/EX1.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.srcs/constrs_1/new/EX1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/First_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/First_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 714.668 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 714.668 ; gain = 402.566 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 714.668 ; gain = 402.566 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 714.668 ; gain = 402.566 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 714.668 ; gain = 402.566 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module First +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 714.668 ; gain = 402.566 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 785.391 ; gain = 473.289 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 785.391 ; gain = 473.289 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 785.391 ; gain = 473.289 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.520 ; gain = 474.418 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.520 ; gain = 474.418 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.520 ; gain = 474.418 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.520 ; gain = 474.418 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.520 ; gain = 474.418 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.520 ; gain = 474.418 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT2 | 3| +|2 |IBUF | 2| +|3 |OBUF | 3| ++------+-----+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 8| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.520 ; gain = 474.418 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 786.547 ; gain = 224.727 +Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.547 ; gain = 474.445 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 803.215 ; gain = 504.172 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/synth_1/First.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file First_utilization_synth.rpt -pb First_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 803.215 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Tue Sep 24 00:21:21 2024... diff --git a/Exp1-1/Exp1-1.runs/synth_1/First_utilization_synth.pb b/Exp1-1/Exp1-1.runs/synth_1/First_utilization_synth.pb new file mode 100644 index 0000000..72816d6 Binary files /dev/null and b/Exp1-1/Exp1-1.runs/synth_1/First_utilization_synth.pb differ diff --git a/Exp1-1/Exp1-1.runs/synth_1/First_utilization_synth.rpt b/Exp1-1/Exp1-1.runs/synth_1/First_utilization_synth.rpt new file mode 100644 index 0000000..2521d2a --- /dev/null +++ b/Exp1-1/Exp1-1.runs/synth_1/First_utilization_synth.rpt @@ -0,0 +1,170 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Tue Sep 24 00:21:21 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file First_utilization_synth.rpt -pb First_utilization_synth.pb +| Design : First +| Device : 7a35tcsg324-1 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 2 | 0 | 20800 | <0.01 | +| LUT as Logic | 2 | 0 | 20800 | <0.01 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 5 | 0 | 210 | 2.38 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 3 | IO | +| LUT2 | 3 | LUT | +| IBUF | 2 | IO | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp1-1/Exp1-1.runs/synth_1/gen_run.xml b/Exp1-1/Exp1-1.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..5158b0e --- /dev/null +++ b/Exp1-1/Exp1-1.runs/synth_1/gen_run.xml @@ -0,0 +1,41 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp1-1/Exp1-1.runs/synth_1/htr.txt b/Exp1-1/Exp1-1.runs/synth_1/htr.txt new file mode 100644 index 0000000..817efbf --- /dev/null +++ b/Exp1-1/Exp1-1.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log First.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source First.tcl diff --git a/Exp1-1/Exp1-1.runs/synth_1/vivado.jou b/Exp1-1/Exp1-1.runs/synth_1/vivado.jou new file mode 100644 index 0000000..879a80c --- /dev/null +++ b/Exp1-1/Exp1-1.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Tue Sep 24 00:20:53 2024 +# Process ID: 13976 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/synth_1 +# Command line: vivado.exe -log First.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source First.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/synth_1/First.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source First.tcl -notrace diff --git a/Exp1-1/Exp1-1.runs/synth_1/vivado.pb b/Exp1-1/Exp1-1.runs/synth_1/vivado.pb new file mode 100644 index 0000000..556a862 Binary files /dev/null and b/Exp1-1/Exp1-1.runs/synth_1/vivado.pb differ diff --git a/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/glbl.v b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/sim4First.tcl b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/sim4First.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/sim4First.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/sim4First_vlog.prj b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/sim4First_vlog.prj new file mode 100644 index 0000000..81d472e --- /dev/null +++ b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/sim4First_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp1-1.srcs/sources_1/new/First.v" \ +"../../../../Exp1-1.srcs/sim_1/new/sim4First.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/webtalk.jou b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..a47bb1b --- /dev/null +++ b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 10:27:37 2024 +# Process ID: 14508 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/webtalk_15700.backup.jou b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/webtalk_15700.backup.jou new file mode 100644 index 0000000..f39ec1f --- /dev/null +++ b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/webtalk_15700.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Tue Sep 24 00:24:46 2024 +# Process ID: 15700 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/webtalk_7916.backup.jou b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/webtalk_7916.backup.jou new file mode 100644 index 0000000..b22f7f8 --- /dev/null +++ b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/webtalk_7916.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Tue Sep 24 00:00:44 2024 +# Process ID: 7916 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xelab.pb b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..0f756a6 Binary files /dev/null and b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/Compile_Options.txt b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/Compile_Options.txt new file mode 100644 index 0000000..dc32b7b --- /dev/null +++ b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "bc260fd785a049d8892b723ab83bb369" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "sim4First_behav" "xil_defaultlib.sim4First" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/TempBreakPointFile.txt b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/obj/xsim_1.c b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/obj/xsim_1.c new file mode 100644 index 0000000..7be773e --- /dev/null +++ b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/obj/xsim_1.c @@ -0,0 +1,109 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_3(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_8(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[15] = {(funcp)execute_3, (funcp)execute_11, (funcp)execute_12, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 15; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/sim4First_behav/xsim.reloc", (void **)funcTab, 15); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/sim4First_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/sim4First_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/sim4First_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/sim4First_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/sim4First_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/webtalk/xsim_webtalk.tcl b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..ea62297 --- /dev/null +++ b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Thu Sep 26 11:42:31 2024" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.1 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2188600" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "78ec1a93-fd1a-4b14-8c4b-87f04256706b" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "bc260fd785a049d8892b723ab83bb369" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "13th Gen Intel(R) Core(TM) i7-13700H" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2918 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "1" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.01_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6436_KB" -context "xsim\\usage" +webtalk_transmit -clientid 815621011 -regid "" -xml F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/webtalk/usage_statistics_ext_xsim.xml -html F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/webtalk/usage_statistics_ext_xsim.html -wdm F:/Schoolwork/DigitalLogic/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/xsim.mem b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/xsim.mem new file mode 100644 index 0000000..44b5d74 Binary files /dev/null and b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xsim.dir/sim4First_behav/xsim.mem differ diff --git a/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xvlog.pb b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..b155e40 --- /dev/null +++ b/Exp1-1/Exp1-1.sim/sim_1/behav/xsim/xvlog.pb @@ -0,0 +1,4 @@ + + + +End Record \ No newline at end of file diff --git a/Exp1-1/Exp1-1.srcs/constrs_1/new/EX1.xdc b/Exp1-1/Exp1-1.srcs/constrs_1/new/EX1.xdc new file mode 100644 index 0000000..40811a2 --- /dev/null +++ b/Exp1-1/Exp1-1.srcs/constrs_1/new/EX1.xdc @@ -0,0 +1,10 @@ +set_property PACKAGE_PIN J3 [get_ports {z[2]}] +set_property PACKAGE_PIN J2 [get_ports {z[1]}] +set_property PACKAGE_PIN K2 [get_ports {z[0]}] +set_property PACKAGE_PIN P5 [get_ports a] +set_property PACKAGE_PIN P4 [get_ports b] +set_property IOSTANDARD LVCMOS33 [get_ports {z[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {z[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {z[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports b] +set_property IOSTANDARD LVCMOS33 [get_ports a] diff --git a/Exp1-1/Exp1-1.srcs/sim_1/new/sim4First.v b/Exp1-1/Exp1-1.srcs/sim_1/new/sim4First.v new file mode 100644 index 0000000..66d8470 --- /dev/null +++ b/Exp1-1/Exp1-1.srcs/sim_1/new/sim4First.v @@ -0,0 +1,34 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/09/23 23:58:54 +// Design Name: +// Module Name: sim4First +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module sim4First( ); +reg a; +reg b; +wire [2:0] z; +First uut( .a(a), .b(b), .z(z) ); +always begin +a = 0; b = 0; #100; +a = 0; b = 1; #100; +a = 1; b = 0; #100; +a = 1; b = 1; #100; +end +endmodule diff --git a/Exp1-1/Exp1-1.srcs/sources_1/new/First.v b/Exp1-1/Exp1-1.srcs/sources_1/new/First.v new file mode 100644 index 0000000..1cdf8ec --- /dev/null +++ b/Exp1-1/Exp1-1.srcs/sources_1/new/First.v @@ -0,0 +1,30 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/09/23 23:52:50 +// Design Name: +// Module Name: First +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module First(a,b,z); +input a,b; +output z; +wire [2:0] z; +assign z[0] = a&b; +assign z[1] = a|b; +assign z[2] = a^b; +endmodule diff --git a/Exp1-1/Exp1-1.xpr b/Exp1-1/Exp1-1.xpr new file mode 100644 index 0000000..7fbce75 --- /dev/null +++ b/Exp1-1/Exp1-1.xpr @@ -0,0 +1,151 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp1-2-1/Exp1-2-1.cache/wt/webtalk_pa.xml b/Exp1-2-1/Exp1-2-1.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..3b59ce7 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.cache/wt/webtalk_pa.xml @@ -0,0 +1,85 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp1-2-1/Exp1-2-1.hw/hw_1/hw.xml b/Exp1-2-1/Exp1-2-1.hw/hw_1/hw.xml new file mode 100644 index 0000000..23368fa --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/Exp1-2-1/Exp1-2-1.ip_user_files/README.txt b/Exp1-2-1/Exp1-2-1.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp1-2-1/Exp1-2-1.runs/.jobs/vrs_config_1.xml b/Exp1-2-1/Exp1-2-1.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..80da77e --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp1-2-1/Exp1-2-1.runs/.jobs/vrs_config_2.xml b/Exp1-2-1/Exp1-2-1.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..80da77e --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp1-2-1/Exp1-2-1.runs/.jobs/vrs_config_3.xml b/Exp1-2-1/Exp1-2-1.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..80da77e --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp1-2-1/Exp1-2-1.runs/.jobs/vrs_config_4.xml b/Exp1-2-1/Exp1-2-1.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..a1555ee --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp1-2-1/Exp1-2-1.runs/.jobs/vrs_config_5.xml b/Exp1-2-1/Exp1-2-1.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..afdb19a --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/gen_run.xml b/Exp1-2-1/Exp1-2-1.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..6f74a33 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/gen_run.xml @@ -0,0 +1,107 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/htr.txt b/Exp1-2-1/Exp1-2-1.runs/impl_1/htr.txt new file mode 100644 index 0000000..031e50d --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log mux21.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source mux21.tcl -notrace diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/init_design.pb b/Exp1-2-1/Exp1-2-1.runs/impl_1/init_design.pb new file mode 100644 index 0000000..c927aab Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/init_design.pb differ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.dcp b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.dcp new file mode 100644 index 0000000..f3689f1 Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.dcp differ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.tcl b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.tcl new file mode 100644 index 0000000..d13141c --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.tcl @@ -0,0 +1,83 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + open_checkpoint mux21_routed.dcp + set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.cache/wt [current_project] + catch { write_mem_info -force mux21.mmi } + write_bitstream -force mux21.bit + catch {write_debug_probes -quiet -force mux21} + catch {file copy -force mux21.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.vdi b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.vdi new file mode 100644 index 0000000..536fadc --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.vdi @@ -0,0 +1,492 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 10:49:17 2024 +# Process ID: 8764 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1 +# Command line: vivado.exe -log mux21.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux21.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source mux21.tcl -notrace +Command: open_checkpoint F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 241.340 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.087 . Memory (MB): peak = 1099.941 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.087 . Memory (MB): peak = 1099.941 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600 +open_checkpoint: Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1099.941 ; gain = 867.887 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.070 . Memory (MB): peak = 1099.941 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1122.379 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.042 . Memory (MB): peak = 1122.379 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +27 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file mux21_drc_opted.rpt -pb mux21_drc_opted.pb -rpx mux21_drc_opted.rpx +Command: report_drc -file mux21_drc_opted.rpt -pb mux21_drc_opted.pb -rpx mux21_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1134.961 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15f5e58ac + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1134.961 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1134.961 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15f5e58ac + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.457 . Memory (MB): peak = 1148.934 ; gain = 13.973 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1cbbb9651 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.491 . Memory (MB): peak = 1148.934 ; gain = 13.973 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1cbbb9651 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.493 . Memory (MB): peak = 1148.934 ; gain = 13.973 +Phase 1 Placer Initialization | Checksum: 1cbbb9651 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.496 . Memory (MB): peak = 1148.934 ; gain = 13.973 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 200fb1518 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.739 . Memory (MB): peak = 1149.906 ; gain = 14.945 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 200fb1518 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.742 . Memory (MB): peak = 1149.906 ; gain = 14.945 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 178e0eba0 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1149.906 ; gain = 14.945 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 200fb1518 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.756 . Memory (MB): peak = 1149.906 ; gain = 14.945 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 200fb1518 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.757 . Memory (MB): peak = 1149.906 ; gain = 14.945 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.841 . Memory (MB): peak = 1152.762 ; gain = 17.801 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.842 . Memory (MB): peak = 1152.762 ; gain = 17.801 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.842 . Memory (MB): peak = 1152.762 ; gain = 17.801 +Phase 3 Detail Placement | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.843 . Memory (MB): peak = 1152.762 ; gain = 17.801 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.844 . Memory (MB): peak = 1152.762 ; gain = 17.801 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.848 . Memory (MB): peak = 1152.762 ; gain = 17.801 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.849 . Memory (MB): peak = 1152.762 ; gain = 17.801 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.849 . Memory (MB): peak = 1152.762 ; gain = 17.801 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.849 . Memory (MB): peak = 1152.762 ; gain = 17.801 +Ending Placer Task | Checksum: 161de6f25 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.852 . Memory (MB): peak = 1152.762 ; gain = 17.801 +INFO: [Common 17-83] Releasing license: Implementation +45 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1153.375 ; gain = 0.613 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file mux21_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1164.840 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file mux21_utilization_placed.rpt -pb mux21_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1164.840 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file mux21_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1164.840 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: ee1ea316 ConstDB: 0 ShapeSum: 73bfcc0f RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: a560526d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1281.062 ; gain = 116.223 +Post Restoration Checksum: NetGraph: 60d7a000 NumContArr: 4488b26d Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: a560526d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1287.105 ; gain = 122.266 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: a560526d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1287.105 ; gain = 122.266 +Phase 2 Router Initialization | Checksum: a560526d + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 + +Phase 3 Initial Routing + Number of Nodes with overlaps = 0 +Phase 3 Initial Routing | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 +Phase 4.1 Global Iteration 0 | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 +Phase 4 Rip-up And Reroute | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 +Phase 6 Post Hold Fix | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.00462409 % + Global Horizontal Routing Utilization = 0.00104112 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 1.47059%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1291.004 ; gain = 126.164 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: e32dea32 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1291.004 ; gain = 126.164 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1291.004 ; gain = 126.164 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +58 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1291.004 ; gain = 126.164 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1291.004 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file mux21_drc_routed.rpt -pb mux21_drc_routed.pb -rpx mux21_drc_routed.rpx +Command: report_drc -file mux21_drc_routed.rpt -pb mux21_drc_routed.pb -rpx mux21_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file mux21_methodology_drc_routed.rpt -pb mux21_methodology_drc_routed.pb -rpx mux21_methodology_drc_routed.rpx +Command: report_methodology -file mux21_methodology_drc_routed.rpt -pb mux21_methodology_drc_routed.pb -rpx mux21_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file mux21_power_routed.rpt -pb mux21_power_summary_routed.pb -rpx mux21_power_routed.rpx +Command: report_power -file mux21_power_routed.rpt -pb mux21_power_summary_routed.pb -rpx mux21_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +70 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file mux21_route_status.rpt -pb mux21_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file mux21_timing_summary_routed.rpt -pb mux21_timing_summary_routed.pb -rpx mux21_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file mux21_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file mux21_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Thu Sep 26 10:50:00 2024... +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 10:52:58 2024 +# Process ID: 11856 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1 +# Command line: vivado.exe -log mux21.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux21.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source mux21.tcl -notrace +Command: open_checkpoint mux21_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 241.371 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.064 . Memory (MB): peak = 1109.320 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.064 . Memory (MB): peak = 1109.320 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600 +open_checkpoint: Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1109.320 ; gain = 877.555 +Command: write_bitstream -force mux21.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./mux21.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +22 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1575.359 ; gain = 466.039 +INFO: [Common 17-206] Exiting Vivado at Thu Sep 26 10:53:26 2024... diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_8764.backup.vdi b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_8764.backup.vdi new file mode 100644 index 0000000..73474c2 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_8764.backup.vdi @@ -0,0 +1,421 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 10:49:17 2024 +# Process ID: 8764 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1 +# Command line: vivado.exe -log mux21.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux21.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source mux21.tcl -notrace +Command: open_checkpoint F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 241.340 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.087 . Memory (MB): peak = 1099.941 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.087 . Memory (MB): peak = 1099.941 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600 +open_checkpoint: Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1099.941 ; gain = 867.887 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.070 . Memory (MB): peak = 1099.941 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1122.379 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.042 . Memory (MB): peak = 1122.379 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 24d33865b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +27 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1122.379 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file mux21_drc_opted.rpt -pb mux21_drc_opted.pb -rpx mux21_drc_opted.rpx +Command: report_drc -file mux21_drc_opted.rpt -pb mux21_drc_opted.pb -rpx mux21_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1134.961 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15f5e58ac + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1134.961 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1134.961 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15f5e58ac + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.457 . Memory (MB): peak = 1148.934 ; gain = 13.973 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1cbbb9651 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.491 . Memory (MB): peak = 1148.934 ; gain = 13.973 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1cbbb9651 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.493 . Memory (MB): peak = 1148.934 ; gain = 13.973 +Phase 1 Placer Initialization | Checksum: 1cbbb9651 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.496 . Memory (MB): peak = 1148.934 ; gain = 13.973 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 200fb1518 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.739 . Memory (MB): peak = 1149.906 ; gain = 14.945 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 200fb1518 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.742 . Memory (MB): peak = 1149.906 ; gain = 14.945 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 178e0eba0 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1149.906 ; gain = 14.945 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 200fb1518 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.756 . Memory (MB): peak = 1149.906 ; gain = 14.945 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 200fb1518 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.757 . Memory (MB): peak = 1149.906 ; gain = 14.945 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.841 . Memory (MB): peak = 1152.762 ; gain = 17.801 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.842 . Memory (MB): peak = 1152.762 ; gain = 17.801 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.842 . Memory (MB): peak = 1152.762 ; gain = 17.801 +Phase 3 Detail Placement | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.843 . Memory (MB): peak = 1152.762 ; gain = 17.801 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.844 . Memory (MB): peak = 1152.762 ; gain = 17.801 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.848 . Memory (MB): peak = 1152.762 ; gain = 17.801 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.849 . Memory (MB): peak = 1152.762 ; gain = 17.801 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.849 . Memory (MB): peak = 1152.762 ; gain = 17.801 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18120caf5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.849 . Memory (MB): peak = 1152.762 ; gain = 17.801 +Ending Placer Task | Checksum: 161de6f25 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.852 . Memory (MB): peak = 1152.762 ; gain = 17.801 +INFO: [Common 17-83] Releasing license: Implementation +45 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1153.375 ; gain = 0.613 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file mux21_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1164.840 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file mux21_utilization_placed.rpt -pb mux21_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1164.840 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file mux21_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1164.840 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: ee1ea316 ConstDB: 0 ShapeSum: 73bfcc0f RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: a560526d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1281.062 ; gain = 116.223 +Post Restoration Checksum: NetGraph: 60d7a000 NumContArr: 4488b26d Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: a560526d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1287.105 ; gain = 122.266 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: a560526d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1287.105 ; gain = 122.266 +Phase 2 Router Initialization | Checksum: a560526d + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 + +Phase 3 Initial Routing + Number of Nodes with overlaps = 0 +Phase 3 Initial Routing | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 +Phase 4.1 Global Iteration 0 | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 +Phase 4 Rip-up And Reroute | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 +Phase 6 Post Hold Fix | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.00462409 % + Global Horizontal Routing Utilization = 0.00104112 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 1.47059%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1288.945 ; gain = 124.105 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 1339affad + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1291.004 ; gain = 126.164 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: e32dea32 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1291.004 ; gain = 126.164 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1291.004 ; gain = 126.164 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +58 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 1291.004 ; gain = 126.164 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1291.004 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file mux21_drc_routed.rpt -pb mux21_drc_routed.pb -rpx mux21_drc_routed.rpx +Command: report_drc -file mux21_drc_routed.rpt -pb mux21_drc_routed.pb -rpx mux21_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file mux21_methodology_drc_routed.rpt -pb mux21_methodology_drc_routed.pb -rpx mux21_methodology_drc_routed.rpx +Command: report_methodology -file mux21_methodology_drc_routed.rpt -pb mux21_methodology_drc_routed.pb -rpx mux21_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file mux21_power_routed.rpt -pb mux21_power_summary_routed.pb -rpx mux21_power_routed.rpx +Command: report_power -file mux21_power_routed.rpt -pb mux21_power_summary_routed.pb -rpx mux21_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +70 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file mux21_route_status.rpt -pb mux21_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file mux21_timing_summary_routed.rpt -pb mux21_timing_summary_routed.pb -rpx mux21_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file mux21_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file mux21_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Thu Sep 26 10:50:00 2024... diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_clock_utilization_routed.rpt b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_clock_utilization_routed.rpt new file mode 100644 index 0000000..d0ca07d --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_clock_utilization_routed.rpt @@ -0,0 +1,92 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 10:50:00 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file mux21_clock_utilization_routed.rpt +| Design : mux21 +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +------------------------------------------------------------------------------------ + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 0 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_control_sets_placed.rpt b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_control_sets_placed.rpt new file mode 100644 index 0000000..efdc4eb --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_control_sets_placed.rpt @@ -0,0 +1,61 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 10:49:42 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file mux21_control_sets_placed.rpt +| Design : mux21 +| Device : xc7a35t +------------------------------------------------------------------------------------ + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 0 | +| Unused register locations in slices containing registers | 0 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++--------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++--------------+---------------+------------------+------------------+----------------+ + + diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_opted.pb b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_opted.pb differ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_opted.rpt b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_opted.rpt new file mode 100644 index 0000000..fa9bd9f --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 10:49:41 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file mux21_drc_opted.rpt -pb mux21_drc_opted.pb -rpx mux21_drc_opted.rpx +| Design : mux21 +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: checkpoint_mux21 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_routed.pb b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_routed.pb differ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_routed.rpt b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_routed.rpt new file mode 100644 index 0000000..226af70 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_drc_routed.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 10:49:59 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file mux21_drc_routed.rpt -pb mux21_drc_routed.pb -rpx mux21_drc_routed.rpx +| Design : mux21 +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +--------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: checkpoint_mux21 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_io_placed.rpt b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_io_placed.rpt new file mode 100644 index 0000000..1018ad0 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_io_placed.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 10:49:42 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_io -file mux21_io_placed.rpt +| Design : mux21 +| Device : xc7a35t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2013-12-19 +| Package Pin Delay Version : VERS. 2.0 2013-12-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 4 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | y | High Range | IO_L20P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N4 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| P3 | c | High Range | IO_L14N_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P4 | b | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P5 | a | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R2 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_methodology_drc_routed.pb b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_methodology_drc_routed.pb new file mode 100644 index 0000000..210b56b Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_methodology_drc_routed.pb differ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_methodology_drc_routed.rpt b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_methodology_drc_routed.rpt new file mode 100644 index 0000000..f341deb --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_methodology_drc_routed.rpt @@ -0,0 +1,34 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 10:49:59 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_methodology -file mux21_methodology_drc_routed.rpt -pb mux21_methodology_drc_routed.pb -rpx mux21_methodology_drc_routed.rpx +| Design : mux21 +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +----------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: checkpoint_mux21 + Design limits: + Max violations: + Violations found: 0 ++------+----------+-------------+------------+ +| Rule | Severity | Description | Violations | ++------+----------+-------------+------------+ ++------+----------+-------------+------------+ + +2. REPORT DETAILS +----------------- + diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_opt.dcp b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_opt.dcp new file mode 100644 index 0000000..5bf82c0 Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_opt.dcp differ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_placed.dcp b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_placed.dcp new file mode 100644 index 0000000..13928ae Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_placed.dcp differ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_power_routed.rpt b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_power_routed.rpt new file mode 100644 index 0000000..ab29740 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_power_routed.rpt @@ -0,0 +1,140 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 10:49:59 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_power -file mux21_power_routed.rpt -pb mux21_power_summary_routed.pb -rpx mux21_power_routed.rpx +| Design : mux21 +| Device : xc7a35tcsg324-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 1.108 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 1.034 | +| Device Static (W) | 0.074 | +| Effective TJA (C/W) | 4.8 | +| Max Ambient (C) | 79.7 | +| Junction Temperature (C) | 30.3 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.003 | 1 | --- | --- | +| LUT as Logic | 0.003 | 1 | 20800 | <0.01 | +| Signals | 0.018 | 4 | --- | --- | +| I/O | 1.014 | 4 | 210 | 1.90 | +| Static Power | 0.074 | | | | +| Total | 1.108 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.044 | 0.032 | 0.012 | +| Vccaux | 1.800 | 0.049 | 0.037 | 0.013 | +| Vcco33 | 3.300 | 0.285 | 0.284 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.8 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++-------+-----------+ +| Name | Power (W) | ++-------+-----------+ +| mux21 | 1.034 | ++-------+-----------+ + + diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_power_summary_routed.pb b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_power_summary_routed.pb new file mode 100644 index 0000000..2027300 Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_power_summary_routed.pb differ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_route_status.pb b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_route_status.pb new file mode 100644 index 0000000..a79137f Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_route_status.pb differ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_route_status.rpt b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_route_status.rpt new file mode 100644 index 0000000..1b49300 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 8 : + # of nets not needing routing.......... : 4 : + # of internally routed nets........ : 4 : + # of routable nets..................... : 4 : + # of fully routed nets............. : 4 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_routed.dcp b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_routed.dcp new file mode 100644 index 0000000..120647e Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_routed.dcp differ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_timing_summary_routed.pb b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_timing_summary_routed.pb new file mode 100644 index 0000000..4526e93 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_timing_summary_routed.rpt b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_timing_summary_routed.rpt new file mode 100644 index 0000000..f691a63 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_timing_summary_routed.rpt @@ -0,0 +1,173 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 10:49:59 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file mux21_timing_summary_routed.rpt -pb mux21_timing_summary_routed.pb -rpx mux21_timing_summary_routed.rpx -warn_on_violation +| Design : mux21 +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 0 register/latch pins with no clock. + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 0 ports with no output delay specified. + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_utilization_placed.pb b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_utilization_placed.pb new file mode 100644 index 0000000..8d33d8b Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_utilization_placed.pb differ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_utilization_placed.rpt b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_utilization_placed.rpt new file mode 100644 index 0000000..393bb6c --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21_utilization_placed.rpt @@ -0,0 +1,194 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 10:49:42 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file mux21_utilization_placed.rpt -pb mux21_utilization_placed.pb +| Design : mux21 +| Device : 7a35tcsg324-1 +| Design State : Fully Placed +------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 1 | 0 | 20800 | <0.01 | +| LUT as Logic | 1 | 0 | 20800 | <0.01 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++--------------------------+------+-------+-----------+-------+ +| Slice | 1 | 0 | 8150 | 0.01 | +| SLICEL | 1 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 1 | 0 | 20800 | <0.01 | +| using O5 output only | 0 | | | | +| using O6 output only | 1 | | | | +| using O5 and O6 | 0 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 0 | 0 | 20800 | 0.00 | +| Unique Control Sets | 0 | | | | ++--------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 4 | 4 | 210 | 1.90 | +| IOB Master Pads | 2 | | | | +| IOB Slave Pads | 2 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| IBUF | 3 | IO | +| OBUF | 1 | IO | +| LUT3 | 1 | LUT | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/opt_design.pb b/Exp1-2-1/Exp1-2-1.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..a2da6ca Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/opt_design.pb differ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/place_design.pb b/Exp1-2-1/Exp1-2-1.runs/impl_1/place_design.pb new file mode 100644 index 0000000..256823e Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/place_design.pb differ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/route_design.pb b/Exp1-2-1/Exp1-2-1.runs/impl_1/route_design.pb new file mode 100644 index 0000000..ef67884 Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/route_design.pb differ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/route_report_bus_skew_0.rpt b/Exp1-2-1/Exp1-2-1.runs/impl_1/route_report_bus_skew_0.rpt new file mode 100644 index 0000000..669b833 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/route_report_bus_skew_0.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 10:50:00 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +| Design : mux21 +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/usage_statistics_webtalk.xml b/Exp1-2-1/Exp1-2-1.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..70e5378 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,420 @@ + + +
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+ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/vivado.jou b/Exp1-2-1/Exp1-2-1.runs/impl_1/vivado.jou new file mode 100644 index 0000000..5ee2216 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 10:52:58 2024 +# Process ID: 11856 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1 +# Command line: vivado.exe -log mux21.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux21.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source mux21.tcl -notrace diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/vivado.pb b/Exp1-2-1/Exp1-2-1.runs/impl_1/vivado.pb new file mode 100644 index 0000000..83e0b79 Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/vivado.pb differ diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/vivado_8764.backup.jou b/Exp1-2-1/Exp1-2-1.runs/impl_1/vivado_8764.backup.jou new file mode 100644 index 0000000..8d3bf77 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/impl_1/vivado_8764.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 10:49:17 2024 +# Process ID: 8764 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1 +# Command line: vivado.exe -log mux21.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux21.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1/mux21.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source mux21.tcl -notrace diff --git a/Exp1-2-1/Exp1-2-1.runs/impl_1/write_bitstream.pb b/Exp1-2-1/Exp1-2-1.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..588e4e5 Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/impl_1/write_bitstream.pb differ diff --git a/Exp1-2-1/Exp1-2-1.runs/synth_1/.Xil/mux21_propImpl.xdc b/Exp1-2-1/Exp1-2-1.runs/synth_1/.Xil/mux21_propImpl.xdc new file mode 100644 index 0000000..51209ee --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/synth_1/.Xil/mux21_propImpl.xdc @@ -0,0 +1,9 @@ +set_property SRC_FILE_INFO {cfile:F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.srcs/constrs_1/new/mux21.xdc rfile:../../../Exp1-2-1.srcs/constrs_1/new/mux21.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P5 [get_ports a] +set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P4 [get_ports b] +set_property src_info {type:XDC file:1 line:3 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P3 [get_ports c] +set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G4 [get_ports y] diff --git a/Exp1-2-1/Exp1-2-1.runs/synth_1/gen_run.xml b/Exp1-2-1/Exp1-2-1.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..41338f7 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/synth_1/gen_run.xml @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp1-2-1/Exp1-2-1.runs/synth_1/htr.txt b/Exp1-2-1/Exp1-2-1.runs/synth_1/htr.txt new file mode 100644 index 0000000..aa68124 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log mux21.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source mux21.tcl diff --git a/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21.dcp b/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21.dcp new file mode 100644 index 0000000..39c2335 Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21.dcp differ diff --git a/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21.tcl b/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21.tcl new file mode 100644 index 0000000..2fa1fd4 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21.tcl @@ -0,0 +1,53 @@ +# +# Synthesis run script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +create_project -in_memory -part xc7a35tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.cache/wt [current_project] +set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.srcs/sources_1/new/mux21.v +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.srcs/constrs_1/new/mux21.xdc +set_property used_in_implementation false [get_files F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.srcs/constrs_1/new/mux21.xdc] + +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top mux21 -part xc7a35tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef mux21.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file mux21_utilization_synth.rpt -pb mux21_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21.vds b/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21.vds new file mode 100644 index 0000000..9260300 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21.vds @@ -0,0 +1,262 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 10:48:14 2024 +# Process ID: 2964 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/synth_1 +# Command line: vivado.exe -log mux21.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source mux21.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source mux21.tcl -notrace +Command: synth_design -top mux21 -part xc7a35tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 8668 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 410.164 ; gain = 98.109 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'mux21' [F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.srcs/sources_1/new/mux21.v:23] +INFO: [Synth 8-6155] done synthesizing module 'mux21' (1#1) [F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.srcs/sources_1/new/mux21.v:23] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 465.605 ; gain = 153.551 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 465.605 ; gain = 153.551 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 465.605 ; gain = 153.551 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.srcs/constrs_1/new/mux21.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.srcs/constrs_1/new/mux21.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.srcs/constrs_1/new/mux21.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/mux21_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/mux21_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 703.020 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 703.020 ; gain = 390.965 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 703.020 ; gain = 390.965 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 703.020 ; gain = 390.965 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 703.020 ; gain = 390.965 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module mux21 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 703.020 ; gain = 390.965 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 784.781 ; gain = 472.727 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 784.781 ; gain = 472.727 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 784.781 ; gain = 472.727 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 785.910 ; gain = 473.855 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 785.910 ; gain = 473.855 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 785.910 ; gain = 473.855 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 785.910 ; gain = 473.855 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 785.910 ; gain = 473.855 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 785.910 ; gain = 473.855 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT3 | 1| +|2 |IBUF | 3| +|3 |OBUF | 1| ++------+-----+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 5| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 785.910 ; gain = 473.855 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 785.957 ; gain = 236.488 +Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 785.957 ; gain = 473.902 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 807.996 ; gain = 508.305 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file mux21_utilization_synth.rpt -pb mux21_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 807.996 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Thu Sep 26 10:48:41 2024... diff --git a/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21_utilization_synth.pb b/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21_utilization_synth.pb new file mode 100644 index 0000000..8d33d8b Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21_utilization_synth.pb differ diff --git a/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21_utilization_synth.rpt b/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21_utilization_synth.rpt new file mode 100644 index 0000000..3b05045 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21_utilization_synth.rpt @@ -0,0 +1,170 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 10:48:41 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file mux21_utilization_synth.rpt -pb mux21_utilization_synth.pb +| Design : mux21 +| Device : 7a35tcsg324-1 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 1 | 0 | 20800 | <0.01 | +| LUT as Logic | 1 | 0 | 20800 | <0.01 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 4 | 0 | 210 | 1.90 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| IBUF | 3 | IO | +| OBUF | 1 | IO | +| LUT3 | 1 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp1-2-1/Exp1-2-1.runs/synth_1/vivado.jou b/Exp1-2-1/Exp1-2-1.runs/synth_1/vivado.jou new file mode 100644 index 0000000..f8475c9 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 10:48:14 2024 +# Process ID: 2964 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/synth_1 +# Command line: vivado.exe -log mux21.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source mux21.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/synth_1/mux21.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source mux21.tcl -notrace diff --git a/Exp1-2-1/Exp1-2-1.runs/synth_1/vivado.pb b/Exp1-2-1/Exp1-2-1.runs/synth_1/vivado.pb new file mode 100644 index 0000000..ada8dba Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.runs/synth_1/vivado.pb differ diff --git a/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/glbl.v b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/sim4mux21.tcl b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/sim4mux21.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/sim4mux21.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/sim4mux21_vlog.prj b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/sim4mux21_vlog.prj new file mode 100644 index 0000000..34468cb --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/sim4mux21_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp1-2-1.srcs/sources_1/new/mux21.v" \ +"../../../../Exp1-2-1.srcs/sim_1/new/sim4mux21.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk.jou b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..0a6838c --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 10:56:58 2024 +# Process ID: 5488 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk_13116.backup.jou b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk_13116.backup.jou new file mode 100644 index 0000000..8073e78 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk_13116.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Tue Sep 24 15:19:49 2024 +# Process ID: 13116 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk_4988.backup.jou b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk_4988.backup.jou new file mode 100644 index 0000000..3b1a175 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk_4988.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 10:45:10 2024 +# Process ID: 4988 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk_7884.backup.jou b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk_7884.backup.jou new file mode 100644 index 0000000..3995bd0 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk_7884.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Tue Sep 24 15:18:53 2024 +# Process ID: 7884 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xelab.pb b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..2967b93 Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/Compile_Options.txt b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/Compile_Options.txt new file mode 100644 index 0000000..9650ac7 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "9db7e8c1c3bb47b79120eaa611645771" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "sim4mux21_behav" "xil_defaultlib.sim4mux21" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/TempBreakPointFile.txt b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/obj/xsim_1.c b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/obj/xsim_1.c new file mode 100644 index 0000000..cd3264e --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/obj/xsim_1.c @@ -0,0 +1,108 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_3(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_8(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[14] = {(funcp)execute_3, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_8, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 14; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/sim4mux21_behav/xsim.reloc", (void **)funcTab, 14); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/sim4mux21_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/sim4mux21_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/sim4mux21_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/sim4mux21_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/sim4mux21_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/webtalk/xsim_webtalk.tcl b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..353ad60 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Thu Sep 26 11:01:05 2024" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.1 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2188600" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "78ec1a93-fd1a-4b14-8c4b-87f04256706b" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "9db7e8c1c3bb47b79120eaa611645771" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "14" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "13th Gen Intel(R) Core(TM) i7-13700H" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2918 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "1" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.01_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6432_KB" -context "xsim\\usage" +webtalk_transmit -clientid 2384477533 -regid "" -xml F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/webtalk/usage_statistics_ext_xsim.xml -html F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/webtalk/usage_statistics_ext_xsim.html -wdm F:/Schoolwork/DigitalLogic/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/xsim.mem b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/xsim.mem new file mode 100644 index 0000000..e0f3aa4 Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xsim.dir/sim4mux21_behav/xsim.mem differ diff --git a/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xvlog.pb b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..afbdc0b Binary files /dev/null and b/Exp1-2-1/Exp1-2-1.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Exp1-2-1/Exp1-2-1.srcs/constrs_1/new/mux21.xdc b/Exp1-2-1/Exp1-2-1.srcs/constrs_1/new/mux21.xdc new file mode 100644 index 0000000..ca88ee6 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.srcs/constrs_1/new/mux21.xdc @@ -0,0 +1,8 @@ +set_property PACKAGE_PIN P5 [get_ports a] +set_property PACKAGE_PIN P4 [get_ports b] +set_property PACKAGE_PIN P3 [get_ports c] +set_property PACKAGE_PIN G4 [get_ports y] +set_property IOSTANDARD LVCMOS33 [get_ports a] +set_property IOSTANDARD LVCMOS33 [get_ports b] +set_property IOSTANDARD LVCMOS33 [get_ports c] +set_property IOSTANDARD LVCMOS33 [get_ports y] diff --git a/Exp1-2-1/Exp1-2-1.srcs/sim_1/new/sim4mux21.v b/Exp1-2-1/Exp1-2-1.srcs/sim_1/new/sim4mux21.v new file mode 100644 index 0000000..8d86545 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.srcs/sim_1/new/sim4mux21.v @@ -0,0 +1,37 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/09/24 15:10:13 +// Design Name: +// Module Name: sim4mux21 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module sim4mux21(); +reg a, b, c; +wire y; +mux21 uut(.a(a), .b(b), .c(c), .y(y)); + always begin + a = 0; b = 0; c = 0; #100; + a = 0; b = 0; c = 1; #100; + a = 0; b = 1; c = 0; #100; + a = 0; b = 1; c = 1; #100; + a = 1; b = 0; c = 0; #100; + a = 1; b = 0; c = 1; #100; + a = 1; b = 1; c = 0; #100; + a = 1; b = 1; c = 1; #100; + end +endmodule diff --git a/Exp1-2-1/Exp1-2-1.srcs/sources_1/new/mux21.v b/Exp1-2-1/Exp1-2-1.srcs/sources_1/new/mux21.v new file mode 100644 index 0000000..06b11e4 --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.srcs/sources_1/new/mux21.v @@ -0,0 +1,27 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/09/24 15:07:05 +// Design Name: +// Module Name: mux21 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module mux21(a, b, c, y); +input a, b, c; +output y; +assign y = c ? b : a; +endmodule diff --git a/Exp1-2-1/Exp1-2-1.xpr b/Exp1-2-1/Exp1-2-1.xpr new file mode 100644 index 0000000..894982c --- /dev/null +++ b/Exp1-2-1/Exp1-2-1.xpr @@ -0,0 +1,151 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp1-2-2/Exp1-2-2.cache/wt/webtalk_pa.xml b/Exp1-2-2/Exp1-2-2.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..a0f695f --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.cache/wt/webtalk_pa.xml @@ -0,0 +1,126 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp1-2-2/Exp1-2-2.hw/hw_1/hw.xml b/Exp1-2-2/Exp1-2-2.hw/hw_1/hw.xml new file mode 100644 index 0000000..0e65615 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/Exp1-2-2/Exp1-2-2.ip_user_files/README.txt b/Exp1-2-2/Exp1-2-2.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp1-2-2/Exp1-2-2.runs/.jobs/vrs_config_1.xml b/Exp1-2-2/Exp1-2-2.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..1a99c4e --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp1-2-2/Exp1-2-2.runs/.jobs/vrs_config_2.xml b/Exp1-2-2/Exp1-2-2.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..f1d277d --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp1-2-2/Exp1-2-2.runs/.jobs/vrs_config_3.xml b/Exp1-2-2/Exp1-2-2.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..ef658fc --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/gen_run.xml b/Exp1-2-2/Exp1-2-2.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..8667281 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/gen_run.xml @@ -0,0 +1,97 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/htr.txt b/Exp1-2-2/Exp1-2-2.runs/impl_1/htr.txt new file mode 100644 index 0000000..256dd78 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log mux41.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source mux41.tcl -notrace diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/init_design.pb b/Exp1-2-2/Exp1-2-2.runs/impl_1/init_design.pb new file mode 100644 index 0000000..097fb1b Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/impl_1/init_design.pb differ diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.tcl b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.tcl new file mode 100644 index 0000000..0102e6c --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.tcl @@ -0,0 +1,84 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + set_param xicom.use_bs_reader 1 + open_checkpoint mux41_routed.dcp + set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.cache/wt [current_project] + catch { write_mem_info -force mux41.mmi } + write_bitstream -force mux41.bit + catch {write_debug_probes -quiet -force mux41} + catch {file copy -force mux41.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi new file mode 100644 index 0000000..5c6f04e --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi @@ -0,0 +1,486 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 11:15:35 2024 +# Process ID: 5212 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1 +# Command line: vivado.exe -log mux41.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux41.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source mux41.tcl -notrace +Command: link_design -top mux41 -part xc7a35tcsg324-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 607.348 ; gain = 303.273 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 609.430 ; gain = 2.082 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1130.844 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1130.844 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1130.844 ; gain = 523.496 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file mux41_drc_opted.rpt -pb mux41_drc_opted.pb -rpx mux41_drc_opted.rpx +Command: report_drc -file mux41_drc_opted.rpt -pb mux41_drc_opted.pb -rpx mux41_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1133.133 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12f477d06 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1133.133 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1133.133 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12f477d06 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.362 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 15695016a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.370 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 15695016a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.371 . Memory (MB): peak = 1157.184 ; gain = 24.051 +Phase 1 Placer Initialization | Checksum: 15695016a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.372 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 224a517c0 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.529 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 224a517c0 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.531 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c91896ab + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.539 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 15116b443 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.543 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 15116b443 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.543 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.717 . Memory (MB): peak = 1157.637 ; gain = 24.504 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.717 . Memory (MB): peak = 1157.637 ; gain = 24.504 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.718 . Memory (MB): peak = 1157.637 ; gain = 24.504 +Phase 3 Detail Placement | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.718 . Memory (MB): peak = 1157.637 ; gain = 24.504 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.719 . Memory (MB): peak = 1157.637 ; gain = 24.504 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1157.637 ; gain = 24.504 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1157.637 ; gain = 24.504 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1157.637 ; gain = 24.504 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.723 . Memory (MB): peak = 1157.637 ; gain = 24.504 +Ending Placer Task | Checksum: c54a07d5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.724 . Memory (MB): peak = 1157.637 ; gain = 24.504 +INFO: [Common 17-83] Releasing license: Implementation +41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1159.215 ; gain = 1.578 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file mux41_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1170.410 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file mux41_utilization_placed.rpt -pb mux41_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1170.410 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file mux41_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1170.410 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 153ecc1f ConstDB: 0 ShapeSum: b00b3bb6 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: c648ffa8 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1285.832 ; gain = 115.422 +Post Restoration Checksum: NetGraph: 2d5288c5 NumContArr: 98f676e3 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: c648ffa8 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.891 ; gain = 121.480 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: c648ffa8 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.891 ; gain = 121.480 +Phase 2 Router Initialization | Checksum: c648ffa8 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1293.652 ; gain = 123.242 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 973162bc + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.652 ; gain = 123.242 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277 +Phase 4 Rip-up And Reroute | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277 +Phase 6 Post Hold Fix | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.00398629 % + Global Horizontal Routing Utilization = 0.00221239 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1295.703 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file mux41_drc_routed.rpt -pb mux41_drc_routed.pb -rpx mux41_drc_routed.rpx +Command: report_drc -file mux41_drc_routed.rpt -pb mux41_drc_routed.pb -rpx mux41_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file mux41_methodology_drc_routed.rpt -pb mux41_methodology_drc_routed.pb -rpx mux41_methodology_drc_routed.rpx +Command: report_methodology -file mux41_methodology_drc_routed.rpt -pb mux41_methodology_drc_routed.pb -rpx mux41_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file mux41_power_routed.rpt -pb mux41_power_summary_routed.pb -rpx mux41_power_routed.rpx +Command: report_power -file mux41_power_routed.rpt -pb mux41_power_summary_routed.pb -rpx mux41_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file mux41_route_status.rpt -pb mux41_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file mux41_timing_summary_routed.rpt -pb mux41_timing_summary_routed.pb -rpx mux41_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file mux41_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file mux41_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Thu Sep 26 11:16:12 2024... +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 11:16:29 2024 +# Process ID: 4044 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1 +# Command line: vivado.exe -log mux41.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux41.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source mux41.tcl -notrace +Command: open_checkpoint mux41_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 241.633 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1117.176 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1117.176 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600 +open_checkpoint: Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1117.176 ; gain = 884.664 +Command: write_bitstream -force mux41.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./mux41.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +22 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1581.559 ; gain = 464.383 +INFO: [Common 17-206] Exiting Vivado at Thu Sep 26 11:16:58 2024... diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_5212.backup.vdi b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_5212.backup.vdi new file mode 100644 index 0000000..271aff0 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_5212.backup.vdi @@ -0,0 +1,415 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 11:15:35 2024 +# Process ID: 5212 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1 +# Command line: vivado.exe -log mux41.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux41.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source mux41.tcl -notrace +Command: link_design -top mux41 -part xc7a35tcsg324-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 607.348 ; gain = 303.273 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 609.430 ; gain = 2.082 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1130.844 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1130.844 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1e3e1106b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1130.844 ; gain = 523.496 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1130.844 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file mux41_drc_opted.rpt -pb mux41_drc_opted.pb -rpx mux41_drc_opted.rpx +Command: report_drc -file mux41_drc_opted.rpt -pb mux41_drc_opted.pb -rpx mux41_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1133.133 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12f477d06 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1133.133 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1133.133 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12f477d06 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.362 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 15695016a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.370 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 15695016a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.371 . Memory (MB): peak = 1157.184 ; gain = 24.051 +Phase 1 Placer Initialization | Checksum: 15695016a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.372 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 224a517c0 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.529 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 224a517c0 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.531 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c91896ab + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.539 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 15116b443 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.543 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 15116b443 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.543 . Memory (MB): peak = 1157.184 ; gain = 24.051 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.717 . Memory (MB): peak = 1157.637 ; gain = 24.504 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.717 . Memory (MB): peak = 1157.637 ; gain = 24.504 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.718 . Memory (MB): peak = 1157.637 ; gain = 24.504 +Phase 3 Detail Placement | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.718 . Memory (MB): peak = 1157.637 ; gain = 24.504 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.719 . Memory (MB): peak = 1157.637 ; gain = 24.504 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1157.637 ; gain = 24.504 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1157.637 ; gain = 24.504 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1157.637 ; gain = 24.504 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ac5be8b3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.723 . Memory (MB): peak = 1157.637 ; gain = 24.504 +Ending Placer Task | Checksum: c54a07d5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.724 . Memory (MB): peak = 1157.637 ; gain = 24.504 +INFO: [Common 17-83] Releasing license: Implementation +41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1159.215 ; gain = 1.578 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file mux41_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1170.410 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file mux41_utilization_placed.rpt -pb mux41_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1170.410 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file mux41_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1170.410 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 153ecc1f ConstDB: 0 ShapeSum: b00b3bb6 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: c648ffa8 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1285.832 ; gain = 115.422 +Post Restoration Checksum: NetGraph: 2d5288c5 NumContArr: 98f676e3 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: c648ffa8 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.891 ; gain = 121.480 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: c648ffa8 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.891 ; gain = 121.480 +Phase 2 Router Initialization | Checksum: c648ffa8 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1293.652 ; gain = 123.242 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 973162bc + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.652 ; gain = 123.242 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277 +Phase 4 Rip-up And Reroute | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277 +Phase 6 Post Hold Fix | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.00398629 % + Global Horizontal Routing Utilization = 0.00221239 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: d4df4150 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1295.703 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file mux41_drc_routed.rpt -pb mux41_drc_routed.pb -rpx mux41_drc_routed.rpx +Command: report_drc -file mux41_drc_routed.rpt -pb mux41_drc_routed.pb -rpx mux41_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file mux41_methodology_drc_routed.rpt -pb mux41_methodology_drc_routed.pb -rpx mux41_methodology_drc_routed.rpx +Command: report_methodology -file mux41_methodology_drc_routed.rpt -pb mux41_methodology_drc_routed.pb -rpx mux41_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file mux41_power_routed.rpt -pb mux41_power_summary_routed.pb -rpx mux41_power_routed.rpx +Command: report_power -file mux41_power_routed.rpt -pb mux41_power_summary_routed.pb -rpx mux41_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file mux41_route_status.rpt -pb mux41_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file mux41_timing_summary_routed.rpt -pb mux41_timing_summary_routed.pb -rpx mux41_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file mux41_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file mux41_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Thu Sep 26 11:16:12 2024... diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_clock_utilization_routed.rpt b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_clock_utilization_routed.rpt new file mode 100644 index 0000000..2b1d9a3 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_clock_utilization_routed.rpt @@ -0,0 +1,92 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 11:16:12 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file mux41_clock_utilization_routed.rpt +| Design : mux41 +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +------------------------------------------------------------------------------------ + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 0 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_control_sets_placed.rpt b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_control_sets_placed.rpt new file mode 100644 index 0000000..77f4eb0 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_control_sets_placed.rpt @@ -0,0 +1,61 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 11:15:58 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file mux41_control_sets_placed.rpt +| Design : mux41 +| Device : xc7a35t +------------------------------------------------------------------------------------ + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 0 | +| Unused register locations in slices containing registers | 0 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++--------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++--------------+---------------+------------------+------------------+----------------+ + + diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_opted.pb b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_opted.pb differ diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_opted.rpt b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_opted.rpt new file mode 100644 index 0000000..ca8b945 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 11:15:57 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file mux41_drc_opted.rpt -pb mux41_drc_opted.pb -rpx mux41_drc_opted.rpx +| Design : mux41 +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_routed.pb b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_routed.pb differ diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_routed.rpt b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_routed.rpt new file mode 100644 index 0000000..cca44f0 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_routed.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 11:16:11 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file mux41_drc_routed.rpt -pb mux41_drc_routed.pb -rpx mux41_drc_routed.rpx +| Design : mux41 +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +--------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_io_placed.rpt b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_io_placed.rpt new file mode 100644 index 0000000..e7f352a --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_io_placed.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 11:15:58 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_io -file mux41_io_placed.rpt +| Design : mux41 +| Device : xc7a35t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2013-12-19 +| Package Pin Delay Version : VERS. 2.0 2013-12-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 7 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | Y | High Range | IO_L19N_T3_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | S[0] | High Range | IO_L16P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N4 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | I[3] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P3 | I[2] | High Range | IO_L14N_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P4 | I[1] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P5 | I[0] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R2 | S[1] | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_methodology_drc_routed.pb b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_methodology_drc_routed.pb new file mode 100644 index 0000000..210b56b Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_methodology_drc_routed.pb differ diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_methodology_drc_routed.rpt b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_methodology_drc_routed.rpt new file mode 100644 index 0000000..3f99a94 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_methodology_drc_routed.rpt @@ -0,0 +1,34 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 11:16:12 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_methodology -file mux41_methodology_drc_routed.rpt -pb mux41_methodology_drc_routed.pb -rpx mux41_methodology_drc_routed.rpx +| Design : mux41 +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +----------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 0 ++------+----------+-------------+------------+ +| Rule | Severity | Description | Violations | ++------+----------+-------------+------------+ ++------+----------+-------------+------------+ + +2. REPORT DETAILS +----------------- + diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_opt.dcp b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_opt.dcp new file mode 100644 index 0000000..1bc004a Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_opt.dcp differ diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_placed.dcp b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_placed.dcp new file mode 100644 index 0000000..5c9b7c0 Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_placed.dcp differ diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_power_routed.rpt b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_power_routed.rpt new file mode 100644 index 0000000..2f85862 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_power_routed.rpt @@ -0,0 +1,140 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 11:16:12 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_power -file mux41_power_routed.rpt -pb mux41_power_summary_routed.pb -rpx mux41_power_routed.rpx +| Design : mux41 +| Device : xc7a35tcsg324-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 1.373 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 1.299 | +| Device Static (W) | 0.075 | +| Effective TJA (C/W) | 4.8 | +| Max Ambient (C) | 78.4 | +| Junction Temperature (C) | 31.6 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.004 | 1 | --- | --- | +| LUT as Logic | 0.004 | 1 | 20800 | <0.01 | +| Signals | 0.030 | 7 | --- | --- | +| I/O | 1.265 | 7 | 210 | 3.33 | +| Static Power | 0.075 | | | | +| Total | 1.373 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.070 | 0.058 | 0.012 | +| Vccaux | 1.800 | 0.058 | 0.045 | 0.013 | +| Vcco33 | 3.300 | 0.352 | 0.351 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.8 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++-------+-----------+ +| Name | Power (W) | ++-------+-----------+ +| mux41 | 1.299 | ++-------+-----------+ + + diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_power_summary_routed.pb b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_power_summary_routed.pb new file mode 100644 index 0000000..ffa4848 Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_power_summary_routed.pb differ diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_route_status.pb b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_route_status.pb new file mode 100644 index 0000000..a2327d0 Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_route_status.pb differ diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_route_status.rpt b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_route_status.rpt new file mode 100644 index 0000000..83c5a0b --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 14 : + # of nets not needing routing.......... : 7 : + # of internally routed nets........ : 7 : + # of routable nets..................... : 7 : + # of fully routed nets............. : 7 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_routed.dcp b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_routed.dcp new file mode 100644 index 0000000..d4c7416 Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_routed.dcp differ diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_timing_summary_routed.pb b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_timing_summary_routed.pb new file mode 100644 index 0000000..4526e93 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_timing_summary_routed.rpt b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_timing_summary_routed.rpt new file mode 100644 index 0000000..e8cf44b --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_timing_summary_routed.rpt @@ -0,0 +1,173 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 11:16:12 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file mux41_timing_summary_routed.rpt -pb mux41_timing_summary_routed.pb -rpx mux41_timing_summary_routed.rpx -warn_on_violation +| Design : mux41 +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 0 register/latch pins with no clock. + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 0 ports with no output delay specified. + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_utilization_placed.pb b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_utilization_placed.pb new file mode 100644 index 0000000..1bcf4b4 Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_utilization_placed.pb differ diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_utilization_placed.rpt b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_utilization_placed.rpt new file mode 100644 index 0000000..6a972c7 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_utilization_placed.rpt @@ -0,0 +1,194 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 11:15:58 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file mux41_utilization_placed.rpt -pb mux41_utilization_placed.pb +| Design : mux41 +| Device : 7a35tcsg324-1 +| Design State : Fully Placed +------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 1 | 0 | 20800 | <0.01 | +| LUT as Logic | 1 | 0 | 20800 | <0.01 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++--------------------------+------+-------+-----------+-------+ +| Slice | 1 | 0 | 8150 | 0.01 | +| SLICEL | 1 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 1 | 0 | 20800 | <0.01 | +| using O5 output only | 0 | | | | +| using O6 output only | 1 | | | | +| using O5 and O6 | 0 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 0 | 0 | 20800 | 0.00 | +| Unique Control Sets | 0 | | | | ++--------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 7 | 7 | 210 | 3.33 | +| IOB Master Pads | 3 | | | | +| IOB Slave Pads | 4 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| IBUF | 6 | IO | +| OBUF | 1 | IO | +| LUT6 | 1 | LUT | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/opt_design.pb b/Exp1-2-2/Exp1-2-2.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..a85b2d2 Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/impl_1/opt_design.pb differ diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/place_design.pb b/Exp1-2-2/Exp1-2-2.runs/impl_1/place_design.pb new file mode 100644 index 0000000..6414c80 Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/impl_1/place_design.pb differ diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/route_design.pb b/Exp1-2-2/Exp1-2-2.runs/impl_1/route_design.pb new file mode 100644 index 0000000..e963e6e Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/impl_1/route_design.pb differ diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/route_report_bus_skew_0.rpt b/Exp1-2-2/Exp1-2-2.runs/impl_1/route_report_bus_skew_0.rpt new file mode 100644 index 0000000..d821732 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/route_report_bus_skew_0.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 11:16:12 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +| Design : mux41 +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/usage_statistics_webtalk.xml b/Exp1-2-2/Exp1-2-2.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..0786626 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,459 @@ + + +
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+ diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/vivado.jou b/Exp1-2-2/Exp1-2-2.runs/impl_1/vivado.jou new file mode 100644 index 0000000..dcc038a --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 11:16:29 2024 +# Process ID: 4044 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1 +# Command line: vivado.exe -log mux41.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux41.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source mux41.tcl -notrace diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/vivado.pb b/Exp1-2-2/Exp1-2-2.runs/impl_1/vivado.pb new file mode 100644 index 0000000..0218236 Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/impl_1/vivado.pb differ diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/vivado_5212.backup.jou b/Exp1-2-2/Exp1-2-2.runs/impl_1/vivado_5212.backup.jou new file mode 100644 index 0000000..564a955 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/impl_1/vivado_5212.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 11:15:35 2024 +# Process ID: 5212 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1 +# Command line: vivado.exe -log mux41.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux41.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source mux41.tcl -notrace diff --git a/Exp1-2-2/Exp1-2-2.runs/impl_1/write_bitstream.pb b/Exp1-2-2/Exp1-2-2.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..bd3866d Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/impl_1/write_bitstream.pb differ diff --git a/Exp1-2-2/Exp1-2-2.runs/synth_1/.Xil/mux41_propImpl.xdc b/Exp1-2-2/Exp1-2-2.runs/synth_1/.Xil/mux41_propImpl.xdc new file mode 100644 index 0000000..9ce419d --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/synth_1/.Xil/mux41_propImpl.xdc @@ -0,0 +1,15 @@ +set_property SRC_FILE_INFO {cfile:F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc rfile:../../../Exp1-2-2.srcs/constrs_1/new/mux41.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P5 [get_ports {I[0]}] +set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P4 [get_ports {I[1]}] +set_property src_info {type:XDC file:1 line:3 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P3 [get_ports {I[2]}] +set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P2 [get_ports {I[3]}] +set_property src_info {type:XDC file:1 line:5 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R2 [get_ports {S[1]}] +set_property src_info {type:XDC file:1 line:6 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN M4 [get_ports {S[0]}] +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F6 [get_ports Y] diff --git a/Exp1-2-2/Exp1-2-2.runs/synth_1/gen_run.xml b/Exp1-2-2/Exp1-2-2.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..42ddda0 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/synth_1/gen_run.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp1-2-2/Exp1-2-2.runs/synth_1/htr.txt b/Exp1-2-2/Exp1-2-2.runs/synth_1/htr.txt new file mode 100644 index 0000000..9eea096 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log mux41.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source mux41.tcl diff --git a/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.dcp b/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.dcp new file mode 100644 index 0000000..d70578a Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.dcp differ diff --git a/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.tcl b/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.tcl new file mode 100644 index 0000000..78078bf --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.tcl @@ -0,0 +1,57 @@ +# +# Synthesis run script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param xicom.use_bs_reader 1 +create_project -in_memory -part xc7a35tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.cache/wt [current_project] +set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib { + F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux21.v + F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41.v +} +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc +set_property used_in_implementation false [get_files F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc] + +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top mux41 -part xc7a35tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef mux41.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file mux41_utilization_synth.rpt -pb mux41_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.vds b/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.vds new file mode 100644 index 0000000..cb336d9 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.vds @@ -0,0 +1,264 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 11:15:01 2024 +# Process ID: 2832 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1 +# Command line: vivado.exe -log mux41.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source mux41.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source mux41.tcl -notrace +Command: synth_design -top mux41 -part xc7a35tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 1156 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 409.477 ; gain = 96.402 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'mux41' [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41.v:23] +INFO: [Synth 8-6157] synthesizing module 'mux21' [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux21.v:23] +INFO: [Synth 8-6155] done synthesizing module 'mux21' (1#1) [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux21.v:23] +INFO: [Synth 8-6155] done synthesizing module 'mux41' (2#1) [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41.v:23] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 464.418 ; gain = 151.344 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 464.418 ; gain = 151.344 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 464.418 ; gain = 151.344 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/mux41_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/mux41_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 715.266 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 715.266 ; gain = 402.191 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 715.266 ; gain = 402.191 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 715.266 ; gain = 402.191 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 715.266 ; gain = 402.191 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 3 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module mux21 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 715.266 ; gain = 402.191 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 785.012 ; gain = 471.938 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 785.012 ; gain = 471.938 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 785.012 ; gain = 471.938 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.141 ; gain = 473.066 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.141 ; gain = 473.066 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.141 ; gain = 473.066 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.141 ; gain = 473.066 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.141 ; gain = 473.066 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.141 ; gain = 473.066 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT6 | 1| +|2 |IBUF | 6| +|3 |OBUF | 1| ++------+-----+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 8| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.141 ; gain = 473.066 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 786.168 ; gain = 222.246 +Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 786.168 ; gain = 473.094 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +16 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 804.129 ; gain = 503.848 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file mux41_utilization_synth.rpt -pb mux41_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 804.129 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Thu Sep 26 11:15:29 2024... diff --git a/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41_utilization_synth.pb b/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41_utilization_synth.pb new file mode 100644 index 0000000..1bcf4b4 Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41_utilization_synth.pb differ diff --git a/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41_utilization_synth.rpt b/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41_utilization_synth.rpt new file mode 100644 index 0000000..ae69bda --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41_utilization_synth.rpt @@ -0,0 +1,170 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Sep 26 11:15:29 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file mux41_utilization_synth.rpt -pb mux41_utilization_synth.pb +| Design : mux41 +| Device : 7a35tcsg324-1 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 1 | 0 | 20800 | <0.01 | +| LUT as Logic | 1 | 0 | 20800 | <0.01 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 7 | 0 | 210 | 3.33 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| IBUF | 6 | IO | +| OBUF | 1 | IO | +| LUT6 | 1 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp1-2-2/Exp1-2-2.runs/synth_1/vivado.jou b/Exp1-2-2/Exp1-2-2.runs/synth_1/vivado.jou new file mode 100644 index 0000000..49ab45e --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 11:15:01 2024 +# Process ID: 2832 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1 +# Command line: vivado.exe -log mux41.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source mux41.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1/mux41.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source mux41.tcl -notrace diff --git a/Exp1-2-2/Exp1-2-2.runs/synth_1/vivado.pb b/Exp1-2-2/Exp1-2-2.runs/synth_1/vivado.pb new file mode 100644 index 0000000..bd530f5 Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.runs/synth_1/vivado.pb differ diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/glbl.v b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/mux41_vlog.prj b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/mux41_vlog.prj new file mode 100644 index 0000000..573bbfb --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/mux41_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp1-2-2.srcs/sources_1/new/mux21.v" \ +"../../../../Exp1-2-2.srcs/sources_1/new/mux41.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/sim4mux41.tcl b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/sim4mux41.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/sim4mux41.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/sim4mux41_alt.tcl b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/sim4mux41_alt.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/sim4mux41_alt.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/sim4mux41_alt_vlog.prj b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/sim4mux41_alt_vlog.prj new file mode 100644 index 0000000..4cf3490 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/sim4mux41_alt_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp1-2-2.srcs/sources_1/new/mux41_alt.v" \ +"../../../../Exp1-2-2.srcs/sim_1/new/sim4mux41_alt.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/sim4mux41_vlog.prj b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/sim4mux41_vlog.prj new file mode 100644 index 0000000..5479821 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/sim4mux41_vlog.prj @@ -0,0 +1,11 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp1-2-2.srcs/sources_1/new/mux21.v" \ +"../../../../Exp1-2-2.srcs/sources_1/new/mux41.v" \ +"../../../../Exp1-2-2.srcs/sim_1/new/sim4mux41.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk.jou b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..2580d08 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 10 22:23:22 2024 +# Process ID: 14468 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk_13444.backup.jou b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk_13444.backup.jou new file mode 100644 index 0000000..fcfdf29 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk_13444.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 22:34:36 2024 +# Process ID: 13444 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk_2032.backup.jou b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk_2032.backup.jou new file mode 100644 index 0000000..53b8f49 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk_2032.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 11:10:37 2024 +# Process ID: 2032 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk_9156.backup.jou b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk_9156.backup.jou new file mode 100644 index 0000000..558eb8a --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk_9156.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 11:10:05 2024 +# Process ID: 9156 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk_9968.backup.jou b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk_9968.backup.jou new file mode 100644 index 0000000..a87232a --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk_9968.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Sep 26 11:52:52 2024 +# Process ID: 9968 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xelab.pb b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..30f93ca Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/Compile_Options.txt b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/Compile_Options.txt new file mode 100644 index 0000000..b36d3fe --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "fbe5a834d1f2498f94e9d82c49c1070a" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "sim4mux41_alt_behav" "xil_defaultlib.sim4mux41_alt" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/TempBreakPointFile.txt b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/obj/xsim_1.c b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/obj/xsim_1.c new file mode 100644 index 0000000..e8d8ae4 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/obj/xsim_1.c @@ -0,0 +1,108 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_3(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[14] = {(funcp)execute_4, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 14; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/sim4mux41_alt_behav/xsim.reloc", (void **)funcTab, 14); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/sim4mux41_alt_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/sim4mux41_alt_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/sim4mux41_alt_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/sim4mux41_alt_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/sim4mux41_alt_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/xsim.mem b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/xsim.mem new file mode 100644 index 0000000..5e63e9b Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_alt_behav/xsim.mem differ diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/Compile_Options.txt b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/Compile_Options.txt new file mode 100644 index 0000000..13d4367 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "fbe5a834d1f2498f94e9d82c49c1070a" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "sim4mux41_behav" "xil_defaultlib.sim4mux41" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/TempBreakPointFile.txt b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/obj/xsim_1.c b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/obj/xsim_1.c new file mode 100644 index 0000000..3038a4f --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/obj/xsim_1.c @@ -0,0 +1,107 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_6(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_11(char*, char *); +extern void execute_8(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[13] = {(funcp)execute_6, (funcp)execute_14, (funcp)execute_15, (funcp)execute_11, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 13; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/sim4mux41_behav/xsim.reloc", (void **)funcTab, 13); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/sim4mux41_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/sim4mux41_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/sim4mux41_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/sim4mux41_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/sim4mux41_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/xsim.mem b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/xsim.mem new file mode 100644 index 0000000..8d3d4e0 Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xsim.dir/sim4mux41_behav/xsim.mem differ diff --git a/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xvlog.pb b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..d23bf4e Binary files /dev/null and b/Exp1-2-2/Exp1-2-2.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc b/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc new file mode 100644 index 0000000..565602b --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc @@ -0,0 +1,14 @@ +set_property PACKAGE_PIN P5 [get_ports {I[0]}] +set_property PACKAGE_PIN P4 [get_ports {I[1]}] +set_property PACKAGE_PIN P3 [get_ports {I[2]}] +set_property PACKAGE_PIN P2 [get_ports {I[3]}] +set_property PACKAGE_PIN R2 [get_ports {S[1]}] +set_property PACKAGE_PIN M4 [get_ports {S[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {I[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {I[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {I[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {I[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {S[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {S[0]}] +set_property PACKAGE_PIN F6 [get_ports Y] +set_property IOSTANDARD LVCMOS33 [get_ports Y] diff --git a/Exp1-2-2/Exp1-2-2.srcs/sim_1/new/sim4mux41.v b/Exp1-2-2/Exp1-2-2.srcs/sim_1/new/sim4mux41.v new file mode 100644 index 0000000..4def20b --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.srcs/sim_1/new/sim4mux41.v @@ -0,0 +1,38 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/09/25 20:35:36 +// Design Name: +// Module Name: sim4mux41 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module sim4mux41(); +reg [3:0] I; +reg [1:0] S; +wire Y; +integer i, s; +mux41 uut (.I(I), .S(S), .Y(Y)); +initial begin + for (i = 0; i < 16; i = i + 1) begin + for (s = 0; s < 4; s = s + 1) begin + I = i; + S = s; + #10; + end + end +end +endmodule diff --git a/Exp1-2-2/Exp1-2-2.srcs/sim_1/new/sim4mux41_alt.v b/Exp1-2-2/Exp1-2-2.srcs/sim_1/new/sim4mux41_alt.v new file mode 100644 index 0000000..2592318 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.srcs/sim_1/new/sim4mux41_alt.v @@ -0,0 +1,35 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/09/26 11:52:05 +// Design Name: +// Module Name: sim4mux41_alt +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module sim4mux41_alt(); +reg [3:0] I; +reg [1:0] S; +wire Y; +mux41_alt test_alt (.I(I), .S(S), .Y(Y)); +initial begin + I = 4'b0000; S=2'b00; //initialize + I = 4'b0001; S=2'b00; #100; // A + I = 4'b0010; S=2'b01; #100; // B + I = 4'b0100; S=2'b10; #100; // C + I = 4'b1000; S=2'b11; #100; // D +end +endmodule diff --git a/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux21.v b/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux21.v new file mode 100644 index 0000000..ebe71d3 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux21.v @@ -0,0 +1,25 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/09/24 15:51:41 +// Design Name: +// Module Name: mux21 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module mux21( input a,input b,input c,output y); +assign y = c ? b : a; +endmodule diff --git a/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41.v b/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41.v new file mode 100644 index 0000000..c594b5d --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41.v @@ -0,0 +1,28 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/09/24 15:50:25 +// Design Name: +// Module Name: mux41 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module mux41(input [3:0] I, input [1:0] S, output Y ); +wire m,n; +mux21 M1(.a(I[0]) , .b(I[1]) , .c(S[0]) , .y(m) ); +mux21 M2(.a(I[2]) , .b(I[3]) , .c(S[0]) , .y(n) ); +mux21 M3(.a(m) , .b(n) , .c(S[1]) , .y(Y) ); +endmodule \ No newline at end of file diff --git a/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41_alt.v b/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41_alt.v new file mode 100644 index 0000000..519401c --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.srcs/sources_1/new/mux41_alt.v @@ -0,0 +1,37 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/09/26 11:43:00 +// Design Name: +// Module Name: mux41_alt +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module mux41_alt(I,S,Y); +input [3:0] I; +input [1:0] S; +output Y; +reg Y; +always begin + case (S) + 2'b00: Y = I[4'b0001]; + 2'b01: Y = I[4'b0010]; + 2'b10: Y = I[4'b0100]; + 2'b11: Y = I[4'b1000]; + default: Y = 0; + endcase +end +endmodule diff --git a/Exp1-2-2/Exp1-2-2.xpr b/Exp1-2-2/Exp1-2-2.xpr new file mode 100644 index 0000000..9b0de83 --- /dev/null +++ b/Exp1-2-2/Exp1-2-2.xpr @@ -0,0 +1,172 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp1-2-3/Exp1-2-3.cache/wt/webtalk_pa.xml b/Exp1-2-3/Exp1-2-3.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..64d7749 --- /dev/null +++ b/Exp1-2-3/Exp1-2-3.cache/wt/webtalk_pa.xml @@ -0,0 +1,80 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp1-2-3/Exp1-2-3.ip_user_files/README.txt b/Exp1-2-3/Exp1-2-3.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp1-2-3/Exp1-2-3.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/LU_sim_vlog.prj b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/LU_sim_vlog.prj new file mode 100644 index 0000000..9eafe3e --- /dev/null +++ b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/LU_sim_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp1-2-3.srcs/sources_1/new/LU.v" \ +"../../../../Exp1-2-3.srcs/sim_1/new/LU_sim.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/glbl.v b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/sim_LU.tcl b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/sim_LU.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/sim_LU.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/sim_LU_vlog.prj b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/sim_LU_vlog.prj new file mode 100644 index 0000000..9eafe3e --- /dev/null +++ b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/sim_LU_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp1-2-3.srcs/sources_1/new/LU.v" \ +"../../../../Exp1-2-3.srcs/sim_1/new/LU_sim.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/webtalk.jou b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..2f39174 --- /dev/null +++ b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 24 00:04:57 2024 +# Process ID: 15972 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/webtalk_18216.backup.jou b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/webtalk_18216.backup.jou new file mode 100644 index 0000000..6d373eb --- /dev/null +++ b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/webtalk_18216.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 24 00:03:53 2024 +# Process ID: 18216 +# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xelab.pb b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..50fd313 Binary files /dev/null and b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/Compile_Options.txt b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/Compile_Options.txt new file mode 100644 index 0000000..6ce2b3d --- /dev/null +++ b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "530f3e30324548dd8d8037ace6e40f69" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "sim_LU_behav" "xil_defaultlib.sim_LU" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/TempBreakPointFile.txt b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/obj/xsim_1.c b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/obj/xsim_1.c new file mode 100644 index 0000000..dc9b0bf --- /dev/null +++ b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/obj/xsim_1.c @@ -0,0 +1,109 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_3(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[15] = {(funcp)execute_4, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 15; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/sim_LU_behav/xsim.reloc", (void **)funcTab, 15); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/sim_LU_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/sim_LU_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/sim_LU_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/sim_LU_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/sim_LU_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/xsim_webtalk.tcl b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..8f8845f --- /dev/null +++ b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Thu Oct 24 00:16:14 2024" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.1 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2188600" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "78ec1a93-fd1a-4b14-8c4b-87f04256706b" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "530f3e30324548dd8d8037ace6e40f69" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "13th Gen Intel(R) Core(TM) i7-13700H" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2918 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.00_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "8508_KB" -context "xsim\\usage" +webtalk_transmit -clientid 2261735523 -regid "" -xml F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/usage_statistics_ext_xsim.xml -html F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/usage_statistics_ext_xsim.html -wdm F:/Schoolwork/DigitalLogic/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/xsim.mem b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/xsim.mem new file mode 100644 index 0000000..9f8055b Binary files /dev/null and b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xsim.dir/sim_LU_behav/xsim.mem differ diff --git a/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xvlog.pb b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..bbd59da Binary files /dev/null and b/Exp1-2-3/Exp1-2-3.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Exp1-2-3/Exp1-2-3.srcs/sim_1/new/LU_sim.v b/Exp1-2-3/Exp1-2-3.srcs/sim_1/new/LU_sim.v new file mode 100644 index 0000000..1f9806b --- /dev/null +++ b/Exp1-2-3/Exp1-2-3.srcs/sim_1/new/LU_sim.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/09/26 10:31:31 +// Design Name: +// Module Name: LU_sim +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module sim_LU(); +reg a,b; +reg [1:0]s; +LU u3(.a(a),.b(b),.s(s),.Y(Y)); +initial begin + a=0;b=0;s=2'b00;#50; + a=0;b=0;s=2'b01;#50; + a=0;b=0;s=2'b10;#50; + a=0;b=0;s=2'b11;#50; + a=0;b=1;s=2'b00;#50; + a=0;b=1;s=2'b01;#50; + a=0;b=1;s=2'b10;#50; + a=0;b=1;s=2'b11;#50; + a=1;b=0;s=2'b00;#50; + a=1;b=0;s=2'b01;#50; + a=1;b=0;s=2'b10;#50; + a=1;b=0;s=2'b11;#50; + a=1;b=1;s=2'b00;#50; + a=1;b=1;s=2'b01;#50; + a=1;b=1;s=2'b10;#50; + a=1;b=1;s=2'b11;#50; + end +endmodule diff --git a/Exp1-2-3/Exp1-2-3.srcs/sources_1/new/LU.v b/Exp1-2-3/Exp1-2-3.srcs/sources_1/new/LU.v new file mode 100644 index 0000000..2ed8953 --- /dev/null +++ b/Exp1-2-3/Exp1-2-3.srcs/sources_1/new/LU.v @@ -0,0 +1,37 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/09/25 20:04:39 +// Design Name: +// Module Name: LU +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module LU(a, b, s, Y); +input a, b; +input [1:0] s; +output Y; +reg Y; +always @(*) begin + case (s) + 2'b00: Y = a & b; + 2'b01: Y = a | b; + 2'b10: Y = a ^ b; + 2'b11: Y = 0; + default: Y = 0; + endcase +end +endmodule diff --git a/Exp1-2-3/Exp1-2-3.xpr b/Exp1-2-3/Exp1-2-3.xpr new file mode 100644 index 0000000..ca0cbe1 --- /dev/null +++ b/Exp1-2-3/Exp1-2-3.xpr @@ -0,0 +1,142 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp2/Exp2.cache/wt/webtalk_pa.xml b/Exp2/Exp2.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..25b3344 --- /dev/null +++ b/Exp2/Exp2.cache/wt/webtalk_pa.xml @@ -0,0 +1,116 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp2/Exp2.hw/hw_1/hw.xml b/Exp2/Exp2.hw/hw_1/hw.xml new file mode 100644 index 0000000..fd8522e --- /dev/null +++ b/Exp2/Exp2.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/Exp2/Exp2.ip_user_files/README.txt b/Exp2/Exp2.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp2/Exp2.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp2/Exp2.runs/.jobs/vrs_config_1.xml b/Exp2/Exp2.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..7e4f296 --- /dev/null +++ b/Exp2/Exp2.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp2/Exp2.runs/.jobs/vrs_config_10.xml b/Exp2/Exp2.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..7316732 --- /dev/null +++ b/Exp2/Exp2.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp2/Exp2.runs/.jobs/vrs_config_11.xml b/Exp2/Exp2.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000..de9e9a1 --- /dev/null +++ b/Exp2/Exp2.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp2/Exp2.runs/.jobs/vrs_config_2.xml b/Exp2/Exp2.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..7e4f296 --- /dev/null +++ b/Exp2/Exp2.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp2/Exp2.runs/.jobs/vrs_config_3.xml b/Exp2/Exp2.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..7316732 --- /dev/null +++ b/Exp2/Exp2.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp2/Exp2.runs/.jobs/vrs_config_4.xml b/Exp2/Exp2.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..de9e9a1 --- /dev/null +++ b/Exp2/Exp2.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp2/Exp2.runs/.jobs/vrs_config_5.xml b/Exp2/Exp2.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..6759fd5 --- /dev/null +++ b/Exp2/Exp2.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp2/Exp2.runs/.jobs/vrs_config_6.xml b/Exp2/Exp2.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..6759fd5 --- /dev/null +++ b/Exp2/Exp2.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp2/Exp2.runs/.jobs/vrs_config_7.xml b/Exp2/Exp2.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..7e4f296 --- /dev/null +++ b/Exp2/Exp2.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp2/Exp2.runs/.jobs/vrs_config_8.xml b/Exp2/Exp2.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..7e4f296 --- /dev/null +++ b/Exp2/Exp2.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp2/Exp2.runs/.jobs/vrs_config_9.xml b/Exp2/Exp2.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..7e4f296 --- /dev/null +++ b/Exp2/Exp2.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine.dcp b/Exp2/Exp2.runs/impl_1/VotingMachine.dcp new file mode 100644 index 0000000..9044ebd Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/VotingMachine.dcp differ diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine.tcl b/Exp2/Exp2.runs/impl_1/VotingMachine.tcl new file mode 100644 index 0000000..201a5a7 --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/VotingMachine.tcl @@ -0,0 +1,86 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + set_param synth.incrementalSynthesisCache C:/Users/Launchcore/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-8484-W10-20240912132/incrSyn + open_checkpoint VotingMachine_routed.dcp + set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp2/Exp2.cache/wt [current_project] + catch { write_mem_info -force VotingMachine.mmi } + write_bitstream -force VotingMachine.bit + catch {write_debug_probes -quiet -force VotingMachine} + catch {file copy -force VotingMachine.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine.vdi b/Exp2/Exp2.runs/impl_1/VotingMachine.vdi new file mode 100644 index 0000000..806e8c0 --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/VotingMachine.vdi @@ -0,0 +1,494 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Oct 30 22:15:57 2024 +# Process ID: 13852 +# Current directory: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1 +# Command line: vivado.exe -log VotingMachine.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VotingMachine.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source VotingMachine.tcl -notrace +Command: open_checkpoint F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 241.406 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.068 . Memory (MB): peak = 1100.066 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.068 . Memory (MB): peak = 1100.066 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600 +open_checkpoint: Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1100.066 ; gain = 867.906 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.422 . Memory (MB): peak = 1100.066 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1182.688 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1182.688 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +27 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file VotingMachine_drc_opted.rpt -pb VotingMachine_drc_opted.pb -rpx VotingMachine_drc_opted.rpx +Command: report_drc -file VotingMachine_drc_opted.rpt -pb VotingMachine_drc_opted.pb -rpx VotingMachine_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1182.688 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 119f72407 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1182.688 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1182.688 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 119f72407 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.711 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 19ef8c04c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.749 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 19ef8c04c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.752 . Memory (MB): peak = 1183.602 ; gain = 0.914 +Phase 1 Placer Initialization | Checksum: 19ef8c04c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.755 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 1f3b94ae4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.979 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1f3b94ae4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.983 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1753737e1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1663eac7d + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1663eac7d + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 +Phase 3 Detail Placement | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 +Ending Placer Task | Checksum: 18e353fcf + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 +INFO: [Common 17-83] Releasing license: Implementation +45 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1183.602 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file VotingMachine_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.058 . Memory (MB): peak = 1186.914 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file VotingMachine_utilization_placed.rpt -pb VotingMachine_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1186.914 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file VotingMachine_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1186.914 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: d8824398 ConstDB: 0 ShapeSum: b5b2fc37 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 129681f39 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1304.242 ; gain = 117.328 +Post Restoration Checksum: NetGraph: 9ea064da NumContArr: 8ac7ba5f Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 129681f39 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1310.238 ; gain = 123.324 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 129681f39 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1310.238 ; gain = 123.324 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: e63e38b1 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1311.988 ; gain = 125.074 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 15d346a17 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1311.988 ; gain = 125.074 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 1068dce0d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1312.016 ; gain = 125.102 +Phase 4 Rip-up And Reroute | Checksum: 1068dce0d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1312.016 ; gain = 125.102 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 1068dce0d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1312.016 ; gain = 125.102 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 1068dce0d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1312.016 ; gain = 125.102 +Phase 6 Post Hold Fix | Checksum: 1068dce0d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1312.016 ; gain = 125.102 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0338037 % + Global Horizontal Routing Utilization = 0.00403436 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 32.4324%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 11.7647%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 1068dce0d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1312.016 ; gain = 125.102 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 1068dce0d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1314.301 ; gain = 127.387 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 18747fc02 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1314.301 ; gain = 127.387 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1314.301 ; gain = 127.387 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +58 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1314.301 ; gain = 127.387 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1314.301 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file VotingMachine_drc_routed.rpt -pb VotingMachine_drc_routed.pb -rpx VotingMachine_drc_routed.rpx +Command: report_drc -file VotingMachine_drc_routed.rpt -pb VotingMachine_drc_routed.pb -rpx VotingMachine_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file VotingMachine_methodology_drc_routed.rpt -pb VotingMachine_methodology_drc_routed.pb -rpx VotingMachine_methodology_drc_routed.rpx +Command: report_methodology -file VotingMachine_methodology_drc_routed.rpt -pb VotingMachine_methodology_drc_routed.pb -rpx VotingMachine_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file VotingMachine_power_routed.rpt -pb VotingMachine_power_summary_routed.pb -rpx VotingMachine_power_routed.rpx +Command: report_power -file VotingMachine_power_routed.rpt -pb VotingMachine_power_summary_routed.pb -rpx VotingMachine_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +70 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file VotingMachine_route_status.rpt -pb VotingMachine_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VotingMachine_timing_summary_routed.rpt -pb VotingMachine_timing_summary_routed.pb -rpx VotingMachine_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file VotingMachine_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file VotingMachine_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Wed Oct 30 22:16:44 2024... +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Oct 30 22:17:04 2024 +# Process ID: 8724 +# Current directory: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1 +# Command line: vivado.exe -log VotingMachine.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VotingMachine.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source VotingMachine.tcl -notrace +Command: open_checkpoint VotingMachine_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 241.285 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1128.934 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1128.934 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600 +open_checkpoint: Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1128.934 ; gain = 896.707 +Command: write_bitstream -force VotingMachine.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./VotingMachine.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +22 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1598.027 ; gain = 469.094 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 30 22:17:36 2024... diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_13852.backup.vdi b/Exp2/Exp2.runs/impl_1/VotingMachine_13852.backup.vdi new file mode 100644 index 0000000..084579e --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/VotingMachine_13852.backup.vdi @@ -0,0 +1,423 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Oct 30 22:15:57 2024 +# Process ID: 13852 +# Current directory: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1 +# Command line: vivado.exe -log VotingMachine.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VotingMachine.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source VotingMachine.tcl -notrace +Command: open_checkpoint F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 241.406 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.068 . Memory (MB): peak = 1100.066 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.068 . Memory (MB): peak = 1100.066 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600 +open_checkpoint: Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1100.066 ; gain = 867.906 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.422 . Memory (MB): peak = 1100.066 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1182.688 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1182.688 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1e7435215 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +27 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1182.688 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file VotingMachine_drc_opted.rpt -pb VotingMachine_drc_opted.pb -rpx VotingMachine_drc_opted.rpx +Command: report_drc -file VotingMachine_drc_opted.rpt -pb VotingMachine_drc_opted.pb -rpx VotingMachine_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1182.688 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 119f72407 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1182.688 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1182.688 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 119f72407 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.711 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 19ef8c04c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.749 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 19ef8c04c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.752 . Memory (MB): peak = 1183.602 ; gain = 0.914 +Phase 1 Placer Initialization | Checksum: 19ef8c04c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.755 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 1f3b94ae4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.979 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1f3b94ae4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.983 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1753737e1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1663eac7d + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1663eac7d + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 +Phase 3 Detail Placement | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b2d265a1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 +Ending Placer Task | Checksum: 18e353fcf + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1183.602 ; gain = 0.914 +INFO: [Common 17-83] Releasing license: Implementation +45 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1183.602 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file VotingMachine_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.058 . Memory (MB): peak = 1186.914 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file VotingMachine_utilization_placed.rpt -pb VotingMachine_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1186.914 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file VotingMachine_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1186.914 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: d8824398 ConstDB: 0 ShapeSum: b5b2fc37 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 129681f39 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1304.242 ; gain = 117.328 +Post Restoration Checksum: NetGraph: 9ea064da NumContArr: 8ac7ba5f Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 129681f39 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1310.238 ; gain = 123.324 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 129681f39 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1310.238 ; gain = 123.324 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: e63e38b1 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1311.988 ; gain = 125.074 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 15d346a17 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1311.988 ; gain = 125.074 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 1068dce0d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1312.016 ; gain = 125.102 +Phase 4 Rip-up And Reroute | Checksum: 1068dce0d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1312.016 ; gain = 125.102 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 1068dce0d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1312.016 ; gain = 125.102 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 1068dce0d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1312.016 ; gain = 125.102 +Phase 6 Post Hold Fix | Checksum: 1068dce0d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1312.016 ; gain = 125.102 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0338037 % + Global Horizontal Routing Utilization = 0.00403436 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 32.4324%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 11.7647%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 1068dce0d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1312.016 ; gain = 125.102 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 1068dce0d + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1314.301 ; gain = 127.387 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 18747fc02 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1314.301 ; gain = 127.387 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1314.301 ; gain = 127.387 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +58 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1314.301 ; gain = 127.387 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1314.301 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file VotingMachine_drc_routed.rpt -pb VotingMachine_drc_routed.pb -rpx VotingMachine_drc_routed.rpx +Command: report_drc -file VotingMachine_drc_routed.rpt -pb VotingMachine_drc_routed.pb -rpx VotingMachine_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file VotingMachine_methodology_drc_routed.rpt -pb VotingMachine_methodology_drc_routed.pb -rpx VotingMachine_methodology_drc_routed.rpx +Command: report_methodology -file VotingMachine_methodology_drc_routed.rpt -pb VotingMachine_methodology_drc_routed.pb -rpx VotingMachine_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file VotingMachine_power_routed.rpt -pb VotingMachine_power_summary_routed.pb -rpx VotingMachine_power_routed.rpx +Command: report_power -file VotingMachine_power_routed.rpt -pb VotingMachine_power_summary_routed.pb -rpx VotingMachine_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +70 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file VotingMachine_route_status.rpt -pb VotingMachine_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file VotingMachine_timing_summary_routed.rpt -pb VotingMachine_timing_summary_routed.pb -rpx VotingMachine_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file VotingMachine_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file VotingMachine_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Wed Oct 30 22:16:44 2024... diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_clock_utilization_routed.rpt b/Exp2/Exp2.runs/impl_1/VotingMachine_clock_utilization_routed.rpt new file mode 100644 index 0000000..8ff46f9 --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/VotingMachine_clock_utilization_routed.rpt @@ -0,0 +1,92 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Oct 30 22:16:44 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file VotingMachine_clock_utilization_routed.rpt +| Design : VotingMachine +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 0 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_control_sets_placed.rpt b/Exp2/Exp2.runs/impl_1/VotingMachine_control_sets_placed.rpt new file mode 100644 index 0000000..6799571 --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/VotingMachine_control_sets_placed.rpt @@ -0,0 +1,61 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Oct 30 22:16:25 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file VotingMachine_control_sets_placed.rpt +| Design : VotingMachine +| Device : xc7a35t +------------------------------------------------------------------------------------------ + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 0 | +| Unused register locations in slices containing registers | 0 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++--------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++--------------+---------------+------------------+------------------+----------------+ + + diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_drc_opted.pb b/Exp2/Exp2.runs/impl_1/VotingMachine_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/VotingMachine_drc_opted.pb differ diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_drc_opted.rpt b/Exp2/Exp2.runs/impl_1/VotingMachine_drc_opted.rpt new file mode 100644 index 0000000..a2c811a --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/VotingMachine_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Oct 30 22:16:23 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file VotingMachine_drc_opted.rpt -pb VotingMachine_drc_opted.pb -rpx VotingMachine_drc_opted.rpx +| Design : VotingMachine +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: checkpoint_VotingMachine + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_drc_routed.pb b/Exp2/Exp2.runs/impl_1/VotingMachine_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/VotingMachine_drc_routed.pb differ diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_drc_routed.rpt b/Exp2/Exp2.runs/impl_1/VotingMachine_drc_routed.rpt new file mode 100644 index 0000000..200262d --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/VotingMachine_drc_routed.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Oct 30 22:16:42 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file VotingMachine_drc_routed.rpt -pb VotingMachine_drc_routed.pb -rpx VotingMachine_drc_routed.rpx +| Design : VotingMachine +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: checkpoint_VotingMachine + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_io_placed.rpt b/Exp2/Exp2.runs/impl_1/VotingMachine_io_placed.rpt new file mode 100644 index 0000000..9249fcb --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/VotingMachine_io_placed.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Oct 30 22:16:25 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_io -file VotingMachine_io_placed.rpt +| Design : VotingMachine +| Device : xc7a35t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2013-12-19 +| Package Pin Delay Version : VERS. 2.0 2013-12-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 27 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | seg1[2] | High Range | IO_L9N_T1_DQS_AD7N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | seg1[4] | High Range | IO_L8N_T1_AD14N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A4 | seg1[5] | High Range | IO_L8P_T1_AD14P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | seg1[3] | High Range | IO_L9P_T1_DQS_AD7P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B2 | seg1[0] | High Range | IO_L10N_T1_AD15N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B3 | seg1[1] | High Range | IO_L10P_T1_AD15P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B4 | seg1[6] | High Range | IO_L7N_T1_AD6N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | seg_cs1[1] | High Range | IO_L16N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C2 | seg_cs1[2] | High Range | IO_L16P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | seg2[0] | High Range | IO_L14N_T2_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D3 | seg2[4] | High Range | IO_L12N_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D4 | seg2[6] | High Range | IO_L11N_T1_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | seg_cs2[1] | High Range | IO_L18N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E2 | seg2[1] | High Range | IO_L14P_T2_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E3 | seg2[5] | High Range | IO_L12P_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | seg_cs2[2] | High Range | IO_L18P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | seg2[2] | High Range | IO_L13N_T2_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F4 | seg2[3] | High Range | IO_L13P_T2_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | seg_cs2[3] | High Range | IO_L17N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G2 | seg_cs1[3] | High Range | IO_L15N_T2_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | seg_cs2[0] | High Range | IO_L19P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | seg_cs1[0] | High Range | IO_L17P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N4 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | votes[1] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P3 | votes[2] | High Range | IO_L14N_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P4 | votes[3] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P5 | votes[4] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R2 | votes[0] | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_methodology_drc_routed.pb b/Exp2/Exp2.runs/impl_1/VotingMachine_methodology_drc_routed.pb new file mode 100644 index 0000000..210b56b Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/VotingMachine_methodology_drc_routed.pb differ diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_methodology_drc_routed.rpt b/Exp2/Exp2.runs/impl_1/VotingMachine_methodology_drc_routed.rpt new file mode 100644 index 0000000..81889b5 --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/VotingMachine_methodology_drc_routed.rpt @@ -0,0 +1,34 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Oct 30 22:16:42 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_methodology -file VotingMachine_methodology_drc_routed.rpt -pb VotingMachine_methodology_drc_routed.pb -rpx VotingMachine_methodology_drc_routed.rpx +| Design : VotingMachine +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: checkpoint_VotingMachine + Design limits: + Max violations: + Violations found: 0 ++------+----------+-------------+------------+ +| Rule | Severity | Description | Violations | ++------+----------+-------------+------------+ ++------+----------+-------------+------------+ + +2. REPORT DETAILS +----------------- + diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_opt.dcp b/Exp2/Exp2.runs/impl_1/VotingMachine_opt.dcp new file mode 100644 index 0000000..9f84755 Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/VotingMachine_opt.dcp differ diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_placed.dcp b/Exp2/Exp2.runs/impl_1/VotingMachine_placed.dcp new file mode 100644 index 0000000..19679cf Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/VotingMachine_placed.dcp differ diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_power_routed.rpt b/Exp2/Exp2.runs/impl_1/VotingMachine_power_routed.rpt new file mode 100644 index 0000000..133cbeb --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/VotingMachine_power_routed.rpt @@ -0,0 +1,143 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Oct 30 22:16:43 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_power -file VotingMachine_power_routed.rpt -pb VotingMachine_power_summary_routed.pb -rpx VotingMachine_power_routed.rpx +| Design : VotingMachine +| Device : xc7a35tcsg324-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 9.584 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 9.456 | +| Device Static (W) | 0.128 | +| Effective TJA (C/W) | 4.8 | +| Max Ambient (C) | 39.2 | +| Junction Temperature (C) | 70.8 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.026 | 9 | --- | --- | +| LUT as Logic | 0.026 | 4 | 20800 | 0.02 | +| Others | 0.000 | 2 | --- | --- | +| Signals | 0.136 | 12 | --- | --- | +| I/O | 9.294 | 27 | 210 | 12.86 | +| Static Power | 0.128 | | | | +| Total | 9.584 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.238 | 0.182 | 0.056 | +| Vccaux | 1.800 | 0.357 | 0.340 | 0.018 | +| Vcco33 | 3.300 | 2.626 | 2.625 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.8 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++---------------+-----------+ +| Name | Power (W) | ++---------------+-----------+ +| VotingMachine | 9.456 | +| u1 | 0.015 | +| u2 | 0.119 | ++---------------+-----------+ + + diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_power_summary_routed.pb b/Exp2/Exp2.runs/impl_1/VotingMachine_power_summary_routed.pb new file mode 100644 index 0000000..0f58efe Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/VotingMachine_power_summary_routed.pb differ diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_route_status.pb b/Exp2/Exp2.runs/impl_1/VotingMachine_route_status.pb new file mode 100644 index 0000000..d6af516 Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/VotingMachine_route_status.pb differ diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_route_status.rpt b/Exp2/Exp2.runs/impl_1/VotingMachine_route_status.rpt new file mode 100644 index 0000000..575a093 --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/VotingMachine_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 41 : + # of nets not needing routing.......... : 27 : + # of internally routed nets........ : 27 : + # of routable nets..................... : 14 : + # of fully routed nets............. : 14 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_routed.dcp b/Exp2/Exp2.runs/impl_1/VotingMachine_routed.dcp new file mode 100644 index 0000000..ae77882 Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/VotingMachine_routed.dcp differ diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_timing_summary_routed.pb b/Exp2/Exp2.runs/impl_1/VotingMachine_timing_summary_routed.pb new file mode 100644 index 0000000..4526e93 --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/VotingMachine_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_timing_summary_routed.rpt b/Exp2/Exp2.runs/impl_1/VotingMachine_timing_summary_routed.rpt new file mode 100644 index 0000000..8ccc49e --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/VotingMachine_timing_summary_routed.rpt @@ -0,0 +1,173 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Oct 30 22:16:43 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file VotingMachine_timing_summary_routed.rpt -pb VotingMachine_timing_summary_routed.pb -rpx VotingMachine_timing_summary_routed.rpx -warn_on_violation +| Design : VotingMachine +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 0 register/latch pins with no clock. + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 0 ports with no output delay specified. + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_utilization_placed.pb b/Exp2/Exp2.runs/impl_1/VotingMachine_utilization_placed.pb new file mode 100644 index 0000000..ee4b124 Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/VotingMachine_utilization_placed.pb differ diff --git a/Exp2/Exp2.runs/impl_1/VotingMachine_utilization_placed.rpt b/Exp2/Exp2.runs/impl_1/VotingMachine_utilization_placed.rpt new file mode 100644 index 0000000..1954bc3 --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/VotingMachine_utilization_placed.rpt @@ -0,0 +1,194 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Oct 30 22:16:25 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file VotingMachine_utilization_placed.rpt -pb VotingMachine_utilization_placed.pb +| Design : VotingMachine +| Device : 7a35tcsg324-1 +| Design State : Fully Placed +----------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 4 | 0 | 20800 | 0.02 | +| LUT as Logic | 4 | 0 | 20800 | 0.02 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++--------------------------+------+-------+-----------+-------+ +| Slice | 1 | 0 | 8150 | 0.01 | +| SLICEL | 1 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 4 | 0 | 20800 | 0.02 | +| using O5 output only | 0 | | | | +| using O6 output only | 1 | | | | +| using O5 and O6 | 3 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 0 | 0 | 20800 | 0.00 | +| Unique Control Sets | 0 | | | | ++--------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 27 | 27 | 210 | 12.86 | +| IOB Master Pads | 12 | | | | +| IOB Slave Pads | 15 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 22 | IO | +| LUT5 | 7 | LUT | +| IBUF | 5 | IO | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp2/Exp2.runs/impl_1/gen_run.xml b/Exp2/Exp2.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..219e661 --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/gen_run.xml @@ -0,0 +1,121 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp2/Exp2.runs/impl_1/htr.txt b/Exp2/Exp2.runs/impl_1/htr.txt new file mode 100644 index 0000000..4ea9bc3 --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log VotingMachine.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source VotingMachine.tcl -notrace diff --git a/Exp2/Exp2.runs/impl_1/init_design.pb b/Exp2/Exp2.runs/impl_1/init_design.pb new file mode 100644 index 0000000..a073676 Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/init_design.pb differ diff --git a/Exp2/Exp2.runs/impl_1/opt_design.pb b/Exp2/Exp2.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..c443e67 Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/opt_design.pb differ diff --git a/Exp2/Exp2.runs/impl_1/place_design.pb b/Exp2/Exp2.runs/impl_1/place_design.pb new file mode 100644 index 0000000..1755fbb Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/place_design.pb differ diff --git a/Exp2/Exp2.runs/impl_1/route_design.pb b/Exp2/Exp2.runs/impl_1/route_design.pb new file mode 100644 index 0000000..e132261 Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/route_design.pb differ diff --git a/Exp2/Exp2.runs/impl_1/route_report_bus_skew_0.rpt b/Exp2/Exp2.runs/impl_1/route_report_bus_skew_0.rpt new file mode 100644 index 0000000..b18513b --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/route_report_bus_skew_0.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Oct 30 22:16:44 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +| Design : VotingMachine +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/Exp2/Exp2.runs/impl_1/usage_statistics_webtalk.xml b/Exp2/Exp2.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..757addf --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,461 @@ + + +
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+ diff --git a/Exp2/Exp2.runs/impl_1/vivado.jou b/Exp2/Exp2.runs/impl_1/vivado.jou new file mode 100644 index 0000000..d27e073 --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Oct 30 22:17:04 2024 +# Process ID: 8724 +# Current directory: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1 +# Command line: vivado.exe -log VotingMachine.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VotingMachine.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source VotingMachine.tcl -notrace diff --git a/Exp2/Exp2.runs/impl_1/vivado.pb b/Exp2/Exp2.runs/impl_1/vivado.pb new file mode 100644 index 0000000..725dc16 Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/vivado.pb differ diff --git a/Exp2/Exp2.runs/impl_1/vivado_13852.backup.jou b/Exp2/Exp2.runs/impl_1/vivado_13852.backup.jou new file mode 100644 index 0000000..5360fb0 --- /dev/null +++ b/Exp2/Exp2.runs/impl_1/vivado_13852.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Oct 30 22:15:57 2024 +# Process ID: 13852 +# Current directory: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1 +# Command line: vivado.exe -log VotingMachine.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source VotingMachine.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1/VotingMachine.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source VotingMachine.tcl -notrace diff --git a/Exp2/Exp2.runs/impl_1/write_bitstream.pb b/Exp2/Exp2.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..a019ad0 Binary files /dev/null and b/Exp2/Exp2.runs/impl_1/write_bitstream.pb differ diff --git a/Exp2/Exp2.runs/synth_1/.Xil/VotingMachine_propImpl.xdc b/Exp2/Exp2.runs/synth_1/.Xil/VotingMachine_propImpl.xdc new file mode 100644 index 0000000..471103a --- /dev/null +++ b/Exp2/Exp2.runs/synth_1/.Xil/VotingMachine_propImpl.xdc @@ -0,0 +1,45 @@ +set_property SRC_FILE_INFO {cfile:F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/constrs_1/new/VotingMachine.xdc rfile:../../../Exp2.srcs/constrs_1/new/VotingMachine.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B4 [get_ports {seg1[6]}] +set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN A4 [get_ports {seg1[5]}] +set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN A3 [get_ports {seg1[4]}] +set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B1 [get_ports {seg1[3]}] +set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN A1 [get_ports {seg1[2]}] +set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B3 [get_ports {seg1[1]}] +set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B2 [get_ports {seg1[0]}] +set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D4 [get_ports {seg2[6]}] +set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E3 [get_ports {seg2[5]}] +set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D3 [get_ports {seg2[4]}] +set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F4 [get_ports {seg2[3]}] +set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F3 [get_ports {seg2[2]}] +set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E2 [get_ports {seg2[1]}] +set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D2 [get_ports {seg2[0]}] +set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G2 [get_ports {seg_cs1[3]}] +set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN C2 [get_ports {seg_cs1[2]}] +set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN C1 [get_ports {seg_cs1[1]}] +set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN H1 [get_ports {seg_cs1[0]}] +set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G1 [get_ports {seg_cs2[3]}] +set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F1 [get_ports {seg_cs2[2]}] +set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E1 [get_ports {seg_cs2[1]}] +set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G6 [get_ports {seg_cs2[0]}] diff --git a/Exp2/Exp2.runs/synth_1/VotingMachine.dcp b/Exp2/Exp2.runs/synth_1/VotingMachine.dcp new file mode 100644 index 0000000..4527da1 Binary files /dev/null and b/Exp2/Exp2.runs/synth_1/VotingMachine.dcp differ diff --git a/Exp2/Exp2.runs/synth_1/VotingMachine.tcl b/Exp2/Exp2.runs/synth_1/VotingMachine.tcl new file mode 100644 index 0000000..01cf4df --- /dev/null +++ b/Exp2/Exp2.runs/synth_1/VotingMachine.tcl @@ -0,0 +1,60 @@ +# +# Synthesis run script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param synth.incrementalSynthesisCache C:/Users/Launchcore/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-8484-W10-20240912132/incrSyn +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 +create_project -in_memory -part xc7a35tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp2/Exp2.cache/wt [current_project] +set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp2/Exp2.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp2/Exp2.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib { + F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/sources_1/new/CoreModule.v + F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/sources_1/new/SegDisplayCtrl.v + F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/sources_1/new/VotingMachine.v +} +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/constrs_1/new/VotingMachine.xdc +set_property used_in_implementation false [get_files F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/constrs_1/new/VotingMachine.xdc] + +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top VotingMachine -part xc7a35tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef VotingMachine.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file VotingMachine_utilization_synth.rpt -pb VotingMachine_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/Exp2/Exp2.runs/synth_1/VotingMachine.vds b/Exp2/Exp2.runs/synth_1/VotingMachine.vds new file mode 100644 index 0000000..6f63054 --- /dev/null +++ b/Exp2/Exp2.runs/synth_1/VotingMachine.vds @@ -0,0 +1,296 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Oct 30 22:07:18 2024 +# Process ID: 5816 +# Current directory: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/synth_1 +# Command line: vivado.exe -log VotingMachine.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source VotingMachine.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/synth_1/VotingMachine.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source VotingMachine.tcl -notrace +Command: synth_design -top VotingMachine -part xc7a35tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 8088 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 409.586 ; gain = 97.223 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'VotingMachine' [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/sources_1/new/VotingMachine.v:23] +INFO: [Synth 8-6157] synthesizing module 'CoreModule' [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/sources_1/new/CoreModule.v:23] +INFO: [Synth 8-6155] done synthesizing module 'CoreModule' (1#1) [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/sources_1/new/CoreModule.v:23] +INFO: [Synth 8-6157] synthesizing module 'SegDisplayCtrl' [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/sources_1/new/SegDisplayCtrl.v:23] +INFO: [Synth 8-6155] done synthesizing module 'SegDisplayCtrl' (2#1) [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/sources_1/new/SegDisplayCtrl.v:23] +INFO: [Synth 8-6155] done synthesizing module 'VotingMachine' (3#1) [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/sources_1/new/VotingMachine.v:23] +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[3] driven by constant 0 +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[2] driven by constant 0 +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[1] driven by constant 0 +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[0] driven by constant 1 +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[3] driven by constant 0 +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[2] driven by constant 0 +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[1] driven by constant 0 +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[0] driven by constant 1 +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 465.242 ; gain = 152.879 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 465.242 ; gain = 152.879 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 465.242 ; gain = 152.879 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/constrs_1/new/VotingMachine.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/constrs_1/new/VotingMachine.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/constrs_1/new/VotingMachine.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/VotingMachine_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/VotingMachine_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 739.375 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 739.375 ; gain = 427.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 739.375 ; gain = 427.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 739.375 ; gain = 427.012 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 739.375 ; gain = 427.012 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 5 Input 3 Bit Adders := 1 ++---Muxes : + 7 Input 7 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module CoreModule +Detailed RTL Component Info : ++---Adders : + 5 Input 3 Bit Adders := 1 +Module SegDisplayCtrl +Detailed RTL Component Info : ++---Muxes : + 7 Input 7 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3917] design VotingMachine has port seg2[6] driven by constant 1 +WARNING: [Synth 8-3917] design VotingMachine has port seg2[4] driven by constant 0 +WARNING: [Synth 8-3917] design VotingMachine has port seg2[3] driven by constant 0 +WARNING: [Synth 8-3917] design VotingMachine has port seg2[2] driven by constant 1 +WARNING: [Synth 8-3917] design VotingMachine has port seg2[1] driven by constant 1 +WARNING: [Synth 8-3917] design VotingMachine has port seg2[0] driven by constant 1 +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[3] driven by constant 0 +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[2] driven by constant 0 +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[1] driven by constant 0 +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[0] driven by constant 1 +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[3] driven by constant 0 +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[2] driven by constant 0 +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[1] driven by constant 0 +WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[0] driven by constant 1 +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 739.375 ; gain = 427.012 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 783.949 ; gain = 471.586 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 783.949 ; gain = 471.586 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 784.660 ; gain = 472.297 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.789 ; gain = 473.426 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.789 ; gain = 473.426 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.789 ; gain = 473.426 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.789 ; gain = 473.426 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.789 ; gain = 473.426 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.789 ; gain = 473.426 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT5 | 7| +|2 |IBUF | 5| +|3 |OBUF | 22| ++------+-----+------+ + +Report Instance Areas: ++------+---------+---------------+------+ +| |Instance |Module |Cells | ++------+---------+---------------+------+ +|1 |top | | 34| +|2 | u1 |CoreModule | 1| +|3 | u2 |SegDisplayCtrl | 6| ++------+---------+---------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.789 ; gain = 473.426 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 14 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 785.824 ; gain = 199.328 +Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.824 ; gain = 473.461 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +18 Infos, 22 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 803.844 ; gain = 504.035 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/synth_1/VotingMachine.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file VotingMachine_utilization_synth.rpt -pb VotingMachine_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 803.844 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 30 22:07:51 2024... diff --git a/Exp2/Exp2.runs/synth_1/VotingMachine_utilization_synth.pb b/Exp2/Exp2.runs/synth_1/VotingMachine_utilization_synth.pb new file mode 100644 index 0000000..ee4b124 Binary files /dev/null and b/Exp2/Exp2.runs/synth_1/VotingMachine_utilization_synth.pb differ diff --git a/Exp2/Exp2.runs/synth_1/VotingMachine_utilization_synth.rpt b/Exp2/Exp2.runs/synth_1/VotingMachine_utilization_synth.rpt new file mode 100644 index 0000000..b1ab618 --- /dev/null +++ b/Exp2/Exp2.runs/synth_1/VotingMachine_utilization_synth.rpt @@ -0,0 +1,170 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Oct 30 22:07:51 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file VotingMachine_utilization_synth.rpt -pb VotingMachine_utilization_synth.pb +| Design : VotingMachine +| Device : 7a35tcsg324-1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 4 | 0 | 20800 | 0.02 | +| LUT as Logic | 4 | 0 | 20800 | 0.02 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 27 | 0 | 210 | 12.86 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 22 | IO | +| LUT5 | 7 | LUT | +| IBUF | 5 | IO | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp2/Exp2.runs/synth_1/gen_run.xml b/Exp2/Exp2.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..cb37d7f --- /dev/null +++ b/Exp2/Exp2.runs/synth_1/gen_run.xml @@ -0,0 +1,58 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp2/Exp2.runs/synth_1/htr.txt b/Exp2/Exp2.runs/synth_1/htr.txt new file mode 100644 index 0000000..3b8d4ed --- /dev/null +++ b/Exp2/Exp2.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log VotingMachine.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source VotingMachine.tcl diff --git a/Exp2/Exp2.runs/synth_1/vivado.jou b/Exp2/Exp2.runs/synth_1/vivado.jou new file mode 100644 index 0000000..dd7191d --- /dev/null +++ b/Exp2/Exp2.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Oct 30 22:07:18 2024 +# Process ID: 5816 +# Current directory: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/synth_1 +# Command line: vivado.exe -log VotingMachine.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source VotingMachine.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/synth_1/VotingMachine.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source VotingMachine.tcl -notrace diff --git a/Exp2/Exp2.runs/synth_1/vivado.pb b/Exp2/Exp2.runs/synth_1/vivado.pb new file mode 100644 index 0000000..b6a0d10 Binary files /dev/null and b/Exp2/Exp2.runs/synth_1/vivado.pb differ diff --git a/Exp2/Exp2.sim/sim_1/behav/xsim/glbl.v b/Exp2/Exp2.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp2/Exp2.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp2/Exp2.sim/sim_1/behav/xsim/tb_VotingMachine.tcl b/Exp2/Exp2.sim/sim_1/behav/xsim/tb_VotingMachine.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp2/Exp2.sim/sim_1/behav/xsim/tb_VotingMachine.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp2/Exp2.sim/sim_1/behav/xsim/tb_VotingMachine_vlog.prj b/Exp2/Exp2.sim/sim_1/behav/xsim/tb_VotingMachine_vlog.prj new file mode 100644 index 0000000..e39ce56 --- /dev/null +++ b/Exp2/Exp2.sim/sim_1/behav/xsim/tb_VotingMachine_vlog.prj @@ -0,0 +1,12 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp2.srcs/sources_1/new/CoreModule.v" \ +"../../../../Exp2.srcs/sources_1/new/SegDisplayCtrl.v" \ +"../../../../Exp2.srcs/sources_1/new/VotingMachine.v" \ +"../../../../Exp2.srcs/sim_1/new/tb_VotingMachine.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.jou b/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..4535eab --- /dev/null +++ b/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Oct 30 22:26:44 2024 +# Process ID: 13980 +# Current directory: F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk_12932.backup.jou b/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk_12932.backup.jou new file mode 100644 index 0000000..c56aa78 --- /dev/null +++ b/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk_12932.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 24 10:11:15 2024 +# Process ID: 12932 +# Current directory: F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk_12964.backup.jou b/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk_12964.backup.jou new file mode 100644 index 0000000..78bf442 --- /dev/null +++ b/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk_12964.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 24 10:12:35 2024 +# Process ID: 12964 +# Current directory: F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk_6268.backup.jou b/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk_6268.backup.jou new file mode 100644 index 0000000..16c8168 --- /dev/null +++ b/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk_6268.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Oct 30 21:31:19 2024 +# Process ID: 6268 +# Current directory: F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp2/Exp2.sim/sim_1/behav/xsim/xelab.pb b/Exp2/Exp2.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..46c753a Binary files /dev/null and b/Exp2/Exp2.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/Compile_Options.txt b/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/Compile_Options.txt new file mode 100644 index 0000000..6368ebb --- /dev/null +++ b/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "ac543a5d75b1465a852508210f7bdca4" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_VotingMachine_behav" "xil_defaultlib.tb_VotingMachine" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/TempBreakPointFile.txt b/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/obj/xsim_1.c b/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/obj/xsim_1.c new file mode 100644 index 0000000..1fd2052 --- /dev/null +++ b/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/obj/xsim_1.c @@ -0,0 +1,112 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_8(char*, char *); +extern void execute_17(char*, char *); +extern void execute_7(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_4(char*, char *); +extern void execute_6(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[18] = {(funcp)execute_8, (funcp)execute_17, (funcp)execute_7, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_4, (funcp)execute_6, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 18; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/tb_VotingMachine_behav/xsim.reloc", (void **)funcTab, 18); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/tb_VotingMachine_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_VotingMachine_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/tb_VotingMachine_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/tb_VotingMachine_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/tb_VotingMachine_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/xsim.mem b/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/xsim.mem new file mode 100644 index 0000000..8d5a09d Binary files /dev/null and b/Exp2/Exp2.sim/sim_1/behav/xsim/xsim.dir/tb_VotingMachine_behav/xsim.mem differ diff --git a/Exp2/Exp2.sim/sim_1/behav/xsim/xvlog.pb b/Exp2/Exp2.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..22280a8 Binary files /dev/null and b/Exp2/Exp2.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Exp2/Exp2.srcs/constrs_1/new/VotingMachine.xdc b/Exp2/Exp2.srcs/constrs_1/new/VotingMachine.xdc new file mode 100644 index 0000000..ef66277 --- /dev/null +++ b/Exp2/Exp2.srcs/constrs_1/new/VotingMachine.xdc @@ -0,0 +1,56 @@ +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[0]}] +set_property PACKAGE_PIN B4 [get_ports {seg1[6]}] +set_property PACKAGE_PIN A4 [get_ports {seg1[5]}] +set_property PACKAGE_PIN A3 [get_ports {seg1[4]}] +set_property PACKAGE_PIN B1 [get_ports {seg1[3]}] +set_property PACKAGE_PIN A1 [get_ports {seg1[2]}] +set_property PACKAGE_PIN B3 [get_ports {seg1[1]}] +set_property PACKAGE_PIN B2 [get_ports {seg1[0]}] +set_property PACKAGE_PIN D4 [get_ports {seg2[6]}] +set_property PACKAGE_PIN E3 [get_ports {seg2[5]}] +set_property PACKAGE_PIN D3 [get_ports {seg2[4]}] +set_property PACKAGE_PIN F4 [get_ports {seg2[3]}] +set_property PACKAGE_PIN F3 [get_ports {seg2[2]}] +set_property PACKAGE_PIN E2 [get_ports {seg2[1]}] +set_property PACKAGE_PIN D2 [get_ports {seg2[0]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[0]}] +set_property PACKAGE_PIN G2 [get_ports {seg_cs1[3]}] +set_property PACKAGE_PIN C2 [get_ports {seg_cs1[2]}] +set_property PACKAGE_PIN C1 [get_ports {seg_cs1[1]}] +set_property PACKAGE_PIN H1 [get_ports {seg_cs1[0]}] +set_property PACKAGE_PIN G1 [get_ports {seg_cs2[3]}] +set_property PACKAGE_PIN F1 [get_ports {seg_cs2[2]}] +set_property PACKAGE_PIN E1 [get_ports {seg_cs2[1]}] +set_property PACKAGE_PIN G6 [get_ports {seg_cs2[0]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {votes[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {votes[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {votes[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {votes[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {votes[0]}] +set_property PACKAGE_PIN P5 [get_ports {votes[4]}] +set_property PACKAGE_PIN P4 [get_ports {votes[3]}] +set_property PACKAGE_PIN P3 [get_ports {votes[2]}] +set_property PACKAGE_PIN P2 [get_ports {votes[1]}] +set_property PACKAGE_PIN R2 [get_ports {votes[0]}] diff --git a/Exp2/Exp2.srcs/sim_1/new/tb_VotingMachine.v b/Exp2/Exp2.srcs/sim_1/new/tb_VotingMachine.v new file mode 100644 index 0000000..cf38a49 --- /dev/null +++ b/Exp2/Exp2.srcs/sim_1/new/tb_VotingMachine.v @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/24 10:08:30 +// Design Name: +// Module Name: tb_VotingMachine +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_VotingMachine(); + reg [4:0] votes; + wire [6:0] seg1; + wire [6:0] seg2; + VotingMachine dut ( + .votes(votes), + .seg1(seg1), + .seg2(seg2) + ); + initial begin + votes = 5'b00000; #10; + votes = 5'b10000; #10; + votes = 5'b11000; #10; + votes = 5'b11100; #10; + votes = 5'b11110; #10; + votes = 5'b11111; #10; + $stop; + end +endmodule diff --git a/Exp2/Exp2.srcs/sources_1/new/CoreModule.v b/Exp2/Exp2.srcs/sources_1/new/CoreModule.v new file mode 100644 index 0000000..186cfcd --- /dev/null +++ b/Exp2/Exp2.srcs/sources_1/new/CoreModule.v @@ -0,0 +1,35 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/18 21:46:41 +// Design Name: +// Module Name: CoreModule +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module CoreModule( + input wire [4:0] votes, + output reg [2:0] count, + output reg pass +); +integer i; +always @(*) begin + count = 0; + for (i = 0; i < 5; i = i + 1) + count = count + votes[i]; + pass = (count >= 3); +end +endmodule diff --git a/Exp2/Exp2.srcs/sources_1/new/SegDisplayCtrl.v b/Exp2/Exp2.srcs/sources_1/new/SegDisplayCtrl.v new file mode 100644 index 0000000..c43bbbe --- /dev/null +++ b/Exp2/Exp2.srcs/sources_1/new/SegDisplayCtrl.v @@ -0,0 +1,44 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/18 21:48:13 +// Design Name: +// Module Name: SegDisplayCtrl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module SegDisplayCtrl( + input wire [2:0] count, + input wire pass, + output reg [6:0] seg1, + output reg [6:0] seg2 +); +always @(*) begin + case (count) + 3'b000: seg1 = 7'b1111110; // 0 + 3'b001: seg1 = 7'b0110000; // 1 + 3'b010: seg1 = 7'b1101101; // 2 + 3'b011: seg1 = 7'b1111001; // 3 + 3'b100: seg1 = 7'b0110011; // 4 + 3'b101: seg1 = 7'b1011011; // 5 + default: seg1 = 7'b0000000; + endcase + if (pass) + seg2 = 7'b1100111; // P + else + seg2 = 7'b1000111; // F +end +endmodule diff --git a/Exp2/Exp2.srcs/sources_1/new/VotingMachine.v b/Exp2/Exp2.srcs/sources_1/new/VotingMachine.v new file mode 100644 index 0000000..f9d64c5 --- /dev/null +++ b/Exp2/Exp2.srcs/sources_1/new/VotingMachine.v @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/18 21:44:02 +// Design Name: +// Module Name: VotingMachine +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module VotingMachine( + input wire [4:0] votes, + output wire [6:0] seg1, + output wire [6:0] seg2, + output reg [3:0] seg_cs1, + output reg [3:0] seg_cs2 +); + wire [2:0] count; + wire pass; +CoreModule u1 ( + .votes(votes), + .count(count), + .pass(pass) +); +SegDisplayCtrl u2 ( + .count(count), + .pass(pass), + .seg1(seg1), + .seg2(seg2) +); +always @(*) begin + seg_cs1 = 4'b0001; + seg_cs2 = 4'b0001; +end +endmodule diff --git a/Exp2/Exp2.xpr b/Exp2/Exp2.xpr new file mode 100644 index 0000000..abd046e --- /dev/null +++ b/Exp2/Exp2.xpr @@ -0,0 +1,165 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp3-1/Exp3-1.cache/wt/webtalk_pa.xml b/Exp3-1/Exp3-1.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..aac4b7c --- /dev/null +++ b/Exp3-1/Exp3-1.cache/wt/webtalk_pa.xml @@ -0,0 +1,92 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp3-1/Exp3-1.hw/hw_1/hw.xml b/Exp3-1/Exp3-1.hw/hw_1/hw.xml new file mode 100644 index 0000000..c0b0da1 --- /dev/null +++ b/Exp3-1/Exp3-1.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/Exp3-1/Exp3-1.ip_user_files/README.txt b/Exp3-1/Exp3-1.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp3-1/Exp3-1.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_1.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..9f2ea09 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_10.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..9f2ea09 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_11.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000..b9e3bd7 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_12.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_12.xml new file mode 100644 index 0000000..c00d8de --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_13.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_13.xml new file mode 100644 index 0000000..f02d3c4 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_14.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_14.xml new file mode 100644 index 0000000..f02d3c4 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_14.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_15.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_15.xml new file mode 100644 index 0000000..9f2ea09 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_15.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_16.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_16.xml new file mode 100644 index 0000000..b9e3bd7 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_16.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_17.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_17.xml new file mode 100644 index 0000000..9f2ea09 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_17.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_18.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_18.xml new file mode 100644 index 0000000..b9e3bd7 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_18.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_19.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_19.xml new file mode 100644 index 0000000..c00d8de --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_19.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_2.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..9f2ea09 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_20.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_20.xml new file mode 100644 index 0000000..865b91f --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_20.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_21.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_21.xml new file mode 100644 index 0000000..f02d3c4 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_21.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_3.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..9f2ea09 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_4.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..b9e3bd7 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_5.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..c00d8de --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_6.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..c00d8de --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_7.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..9f2ea09 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_8.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..b9e3bd7 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/.jobs/vrs_config_9.xml b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..c00d8de --- /dev/null +++ b/Exp3-1/Exp3-1.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder.tcl b/Exp3-1/Exp3-1.runs/impl_1/encoder.tcl new file mode 100644 index 0000000..ec5345a --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/encoder.tcl @@ -0,0 +1,173 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param synth.incrementalSynthesisCache C:/Users/Launchcore/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-27428-W10-20240912132/incrSyn + set_param xicom.use_bs_reader 1 + create_project -in_memory -part xc7a35tcsg324-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.cache/wt [current_project] + set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.xpr [current_project] + set_property ip_output_repo F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1/encoder.dcp + read_xdc F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc + link_design -top encoder -part xc7a35tcsg324-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force encoder_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file encoder_drc_opted.rpt -pb encoder_drc_opted.pb -rpx encoder_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force encoder_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file encoder_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file encoder_utilization_placed.rpt -pb encoder_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file encoder_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force encoder_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file encoder_drc_routed.rpt -pb encoder_drc_routed.pb -rpx encoder_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file encoder_methodology_drc_routed.rpt -pb encoder_methodology_drc_routed.pb -rpx encoder_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file encoder_power_routed.rpt -pb encoder_power_summary_routed.pb -rpx encoder_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file encoder_route_status.rpt -pb encoder_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file encoder_timing_summary_routed.rpt -pb encoder_timing_summary_routed.pb -rpx encoder_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file encoder_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file encoder_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force encoder_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force encoder.mmi } + write_bitstream -force encoder.bit + catch {write_debug_probes -quiet -force encoder} + catch {file copy -force encoder.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder.vdi b/Exp3-1/Exp3-1.runs/impl_1/encoder.vdi new file mode 100644 index 0000000..cd75b54 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/encoder.vdi @@ -0,0 +1,446 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 6 20:20:10 2024 +# Process ID: 22776 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1 +# Command line: vivado.exe -log encoder.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source encoder.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1/encoder.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source encoder.tcl -notrace +Command: link_design -top encoder -part xc7a35tcsg324-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 607.992 ; gain = 302.949 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.334 . Memory (MB): peak = 621.980 ; gain = 13.988 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1e6d09373 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1164.871 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1e6d09373 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1164.871 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1e6d09373 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1164.871 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1e6d09373 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1164.871 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1e6d09373 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1164.871 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1e6d09373 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1164.871 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1164.871 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1e6d09373 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1164.871 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1e6d09373 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1164.871 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1164.871 ; gain = 556.879 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1164.871 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1/encoder_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file encoder_drc_opted.rpt -pb encoder_drc_opted.pb -rpx encoder_drc_opted.rpx +Command: report_drc -file encoder_drc_opted.rpt -pb encoder_drc_opted.pb -rpx encoder_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1/encoder_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1164.871 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fde6e16f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1164.871 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1164.871 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fde6e16f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.276 . Memory (MB): peak = 1179.258 ; gain = 14.387 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 19dbb6743 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.295 . Memory (MB): peak = 1179.258 ; gain = 14.387 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 19dbb6743 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.297 . Memory (MB): peak = 1179.258 ; gain = 14.387 +Phase 1 Placer Initialization | Checksum: 19dbb6743 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.299 . Memory (MB): peak = 1179.258 ; gain = 14.387 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 10498cc91 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.443 . Memory (MB): peak = 1179.258 ; gain = 14.387 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 10498cc91 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.445 . Memory (MB): peak = 1179.258 ; gain = 14.387 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1025d39bf + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.453 . Memory (MB): peak = 1179.258 ; gain = 14.387 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1857b0b6a + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.456 . Memory (MB): peak = 1179.258 ; gain = 14.387 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1857b0b6a + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.456 . Memory (MB): peak = 1179.258 ; gain = 14.387 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1d78115f6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.503 . Memory (MB): peak = 1179.258 ; gain = 14.387 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1d78115f6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.504 . Memory (MB): peak = 1179.258 ; gain = 14.387 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1d78115f6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.505 . Memory (MB): peak = 1179.258 ; gain = 14.387 +Phase 3 Detail Placement | Checksum: 1d78115f6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.505 . Memory (MB): peak = 1179.258 ; gain = 14.387 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1d78115f6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.506 . Memory (MB): peak = 1179.258 ; gain = 14.387 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1d78115f6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.510 . Memory (MB): peak = 1179.258 ; gain = 14.387 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1d78115f6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.510 . Memory (MB): peak = 1179.258 ; gain = 14.387 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1d78115f6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.510 . Memory (MB): peak = 1179.258 ; gain = 14.387 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1d78115f6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.511 . Memory (MB): peak = 1179.258 ; gain = 14.387 +Ending Placer Task | Checksum: 109cbce74 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.513 . Memory (MB): peak = 1179.258 ; gain = 14.387 +INFO: [Common 17-83] Releasing license: Implementation +41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1179.258 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1/encoder_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file encoder_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1185.059 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file encoder_utilization_placed.rpt -pb encoder_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1185.059 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file encoder_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1185.059 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 3ca1c370 ConstDB: 0 ShapeSum: cd2a0b04 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 176b82bd2 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1300.598 ; gain = 115.539 +Post Restoration Checksum: NetGraph: 858ec5e6 NumContArr: f12965ec Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 176b82bd2 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1306.605 ; gain = 121.547 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 176b82bd2 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1306.605 ; gain = 121.547 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: cc427ec7 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1308.340 ; gain = 123.281 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: d13f7764 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1308.340 ; gain = 123.281 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 165e9df40 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1308.363 ; gain = 123.305 +Phase 4 Rip-up And Reroute | Checksum: 165e9df40 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1308.363 ; gain = 123.305 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 165e9df40 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1308.363 ; gain = 123.305 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 165e9df40 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1308.363 ; gain = 123.305 +Phase 6 Post Hold Fix | Checksum: 165e9df40 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1308.363 ; gain = 123.305 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0373914 % + Global Horizontal Routing Utilization = 0.00884956 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 33.3333%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 16.1765%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 165e9df40 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1308.363 ; gain = 123.305 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 165e9df40 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1310.371 ; gain = 125.312 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: d581b89a + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1310.371 ; gain = 125.312 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1310.371 ; gain = 125.312 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 1310.371 ; gain = 125.312 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1310.371 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1/encoder_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file encoder_drc_routed.rpt -pb encoder_drc_routed.pb -rpx encoder_drc_routed.rpx +Command: report_drc -file encoder_drc_routed.rpt -pb encoder_drc_routed.pb -rpx encoder_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1/encoder_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file encoder_methodology_drc_routed.rpt -pb encoder_methodology_drc_routed.pb -rpx encoder_methodology_drc_routed.rpx +Command: report_methodology -file encoder_methodology_drc_routed.rpt -pb encoder_methodology_drc_routed.pb -rpx encoder_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1/encoder_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file encoder_power_routed.rpt -pb encoder_power_summary_routed.pb -rpx encoder_power_routed.rpx +Command: report_power -file encoder_power_routed.rpt -pb encoder_power_summary_routed.pb -rpx encoder_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file encoder_route_status.rpt -pb encoder_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file encoder_timing_summary_routed.rpt -pb encoder_timing_summary_routed.pb -rpx encoder_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file encoder_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file encoder_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force encoder.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +WARNING: [DRC PDRC-153] Gated clock check: Net seg2_OBUF[0] is a gated clock net sourced by a combinational pin seg2_OBUF[0]_inst_i_1/O, cell seg2_OBUF[0]_inst_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./encoder.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +84 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1763.418 ; gain = 419.305 +INFO: [Common 17-206] Exiting Vivado at Wed Nov 6 20:20:47 2024... diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_clock_utilization_routed.rpt b/Exp3-1/Exp3-1.runs/impl_1/encoder_clock_utilization_routed.rpt new file mode 100644 index 0000000..509bc2b --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/encoder_clock_utilization_routed.rpt @@ -0,0 +1,92 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Nov 6 20:20:40 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file encoder_clock_utilization_routed.rpt +| Design : encoder +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 0 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_control_sets_placed.rpt b/Exp3-1/Exp3-1.runs/impl_1/encoder_control_sets_placed.rpt new file mode 100644 index 0000000..59fc9bc --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/encoder_control_sets_placed.rpt @@ -0,0 +1,65 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Nov 6 20:20:29 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file encoder_control_sets_placed.rpt +| Design : encoder +| Device : xc7a35t +------------------------------------------------------------------------------------ + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 1 | +| Unused register locations in slices containing registers | 5 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ +| 11 | 1 | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 11 | 3 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++---------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++---------------+---------------+------------------+------------------+----------------+ +| seg2_OBUF[0] | | | 3 | 11 | ++---------------+---------------+------------------+------------------+----------------+ + + diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_drc_opted.pb b/Exp3-1/Exp3-1.runs/impl_1/encoder_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp3-1/Exp3-1.runs/impl_1/encoder_drc_opted.pb differ diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_drc_opted.rpt b/Exp3-1/Exp3-1.runs/impl_1/encoder_drc_opted.rpt new file mode 100644 index 0000000..cf26d50 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/encoder_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Nov 6 20:20:28 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file encoder_drc_opted.rpt -pb encoder_drc_opted.pb -rpx encoder_drc_opted.rpx +| Design : encoder +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_drc_routed.pb b/Exp3-1/Exp3-1.runs/impl_1/encoder_drc_routed.pb new file mode 100644 index 0000000..5aa0de0 Binary files /dev/null and b/Exp3-1/Exp3-1.runs/impl_1/encoder_drc_routed.pb differ diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_drc_routed.rpt b/Exp3-1/Exp3-1.runs/impl_1/encoder_drc_routed.rpt new file mode 100644 index 0000000..0649ed3 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/encoder_drc_routed.rpt @@ -0,0 +1,55 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Nov 6 20:20:39 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file encoder_drc_routed.rpt -pb encoder_drc_routed.pb -rpx encoder_drc_routed.rpx +| Design : encoder +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 2 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| PDRC-153 | Warning | Gated clock check | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +PDRC-153#1 Warning +Gated clock check +Net seg2_OBUF[0] is a gated clock net sourced by a combinational pin seg2_OBUF[0]_inst_i_1/O, cell seg2_OBUF[0]_inst_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + + diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_io_placed.rpt b/Exp3-1/Exp3-1.runs/impl_1/encoder_io_placed.rpt new file mode 100644 index 0000000..7c44215 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/encoder_io_placed.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Nov 6 20:20:29 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_io -file encoder_io_placed.rpt +| Design : encoder +| Device : xc7a35t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2013-12-19 +| Package Pin Delay Version : VERS. 2.0 2013-12-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 40 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | seg1[2] | High Range | IO_L9N_T1_DQS_AD7N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | seg1[4] | High Range | IO_L8N_T1_AD14N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A4 | seg1[5] | High Range | IO_L8P_T1_AD14P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | seg1[3] | High Range | IO_L9P_T1_DQS_AD7P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B2 | seg1[0] | High Range | IO_L10N_T1_AD15N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B3 | seg1[1] | High Range | IO_L10P_T1_AD15P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B4 | seg1[6] | High Range | IO_L7N_T1_AD6N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | seg_cs1[1] | High Range | IO_L16N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C2 | seg_cs1[2] | High Range | IO_L16P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | seg2[1] | High Range | IO_L14N_T2_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D3 | seg2[5] | High Range | IO_L12N_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D4 | seg2[7] | High Range | IO_L11N_T1_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | seg_cs2[1] | High Range | IO_L18N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E2 | seg2[2] | High Range | IO_L14P_T2_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E3 | seg2[6] | High Range | IO_L12P_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | seg_cs2[2] | High Range | IO_L18P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | seg2[3] | High Range | IO_L13N_T2_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F4 | seg2[4] | High Range | IO_L13P_T2_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | i_sig[7] | High Range | IO_L19N_T3_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | seg_cs2[3] | High Range | IO_L17N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G2 | seg_cs1[3] | High Range | IO_L15N_T2_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G3 | i_sig[5] | High Range | IO_L20N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G4 | i_sig[6] | High Range | IO_L20P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | seg_cs2[0] | High Range | IO_L19P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | seg_cs1[0] | High Range | IO_L17P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| H2 | seg2[0] | High Range | IO_L15P_T2_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | i_sig[3] | High Range | IO_L21N_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | i_sig[1] | High Range | IO_L22N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J3 | i_sig[2] | High Range | IO_L22P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J4 | i_sig[4] | High Range | IO_L21P_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | i_sig[0] | High Range | IO_L23P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | i[2] | High Range | IO_L16P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N4 | i[1] | High Range | IO_L16N_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | i[4] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P3 | i[5] | High Range | IO_L14N_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P4 | i[6] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P5 | i[7] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | i[0] | High Range | IO_L17P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| R2 | i[3] | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | en | High Range | IO_L8N_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_methodology_drc_routed.pb b/Exp3-1/Exp3-1.runs/impl_1/encoder_methodology_drc_routed.pb new file mode 100644 index 0000000..9c1940f Binary files /dev/null and b/Exp3-1/Exp3-1.runs/impl_1/encoder_methodology_drc_routed.pb differ diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_methodology_drc_routed.rpt b/Exp3-1/Exp3-1.runs/impl_1/encoder_methodology_drc_routed.rpt new file mode 100644 index 0000000..4338c7d --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/encoder_methodology_drc_routed.rpt @@ -0,0 +1,90 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Nov 6 20:20:40 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_methodology -file encoder_methodology_drc_routed.rpt -pb encoder_methodology_drc_routed.pb -rpx encoder_methodology_drc_routed.rpx +| Design : encoder +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +----------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 11 ++-----------+----------+-------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-------------------+------------+ +| TIMING-20 | Warning | Non-clocked latch | 11 | ++-----------+----------+-------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-20#1 Warning +Non-clocked latch +The latch Y_reg[0] cannot be properly analyzed as its control pin Y_reg[0]/G is not reached by a timing clock +Related violations: + +TIMING-20#2 Warning +Non-clocked latch +The latch Y_reg[1] cannot be properly analyzed as its control pin Y_reg[1]/G is not reached by a timing clock +Related violations: + +TIMING-20#3 Warning +Non-clocked latch +The latch Y_reg[2] cannot be properly analyzed as its control pin Y_reg[2]/G is not reached by a timing clock +Related violations: + +TIMING-20#4 Warning +Non-clocked latch +The latch i_sig_reg[0] cannot be properly analyzed as its control pin i_sig_reg[0]/G is not reached by a timing clock +Related violations: + +TIMING-20#5 Warning +Non-clocked latch +The latch i_sig_reg[1] cannot be properly analyzed as its control pin i_sig_reg[1]/G is not reached by a timing clock +Related violations: + +TIMING-20#6 Warning +Non-clocked latch +The latch i_sig_reg[2] cannot be properly analyzed as its control pin i_sig_reg[2]/G is not reached by a timing clock +Related violations: + +TIMING-20#7 Warning +Non-clocked latch +The latch i_sig_reg[3] cannot be properly analyzed as its control pin i_sig_reg[3]/G is not reached by a timing clock +Related violations: + +TIMING-20#8 Warning +Non-clocked latch +The latch i_sig_reg[4] cannot be properly analyzed as its control pin i_sig_reg[4]/G is not reached by a timing clock +Related violations: + +TIMING-20#9 Warning +Non-clocked latch +The latch i_sig_reg[5] cannot be properly analyzed as its control pin i_sig_reg[5]/G is not reached by a timing clock +Related violations: + +TIMING-20#10 Warning +Non-clocked latch +The latch i_sig_reg[6] cannot be properly analyzed as its control pin i_sig_reg[6]/G is not reached by a timing clock +Related violations: + +TIMING-20#11 Warning +Non-clocked latch +The latch i_sig_reg[7] cannot be properly analyzed as its control pin i_sig_reg[7]/G is not reached by a timing clock +Related violations: + + diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_opt.dcp b/Exp3-1/Exp3-1.runs/impl_1/encoder_opt.dcp new file mode 100644 index 0000000..03c6b86 Binary files /dev/null and b/Exp3-1/Exp3-1.runs/impl_1/encoder_opt.dcp differ diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_placed.dcp b/Exp3-1/Exp3-1.runs/impl_1/encoder_placed.dcp new file mode 100644 index 0000000..f1d4c34 Binary files /dev/null and b/Exp3-1/Exp3-1.runs/impl_1/encoder_placed.dcp differ diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_power_routed.rpt b/Exp3-1/Exp3-1.runs/impl_1/encoder_power_routed.rpt new file mode 100644 index 0000000..bad6dbd --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/encoder_power_routed.rpt @@ -0,0 +1,143 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Nov 6 20:20:40 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_power -file encoder_power_routed.rpt -pb encoder_power_summary_routed.pb -rpx encoder_power_routed.rpx +| Design : encoder +| Device : xc7a35tcsg324-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 9.143 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 9.020 | +| Device Static (W) | 0.123 | +| Effective TJA (C/W) | 4.8 | +| Max Ambient (C) | 41.3 | +| Junction Temperature (C) | 68.7 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.041 | 38 | --- | --- | +| LUT as Logic | 0.041 | 15 | 20800 | 0.07 | +| Others | 0.000 | 4 | --- | --- | +| Register | 0.000 | 11 | 41600 | 0.03 | +| Signals | 0.116 | 40 | --- | --- | +| I/O | 8.863 | 40 | 210 | 19.05 | +| Static Power | 0.123 | | | | +| Total | 9.143 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.245 | 0.193 | 0.051 | +| Vccaux | 1.800 | 0.341 | 0.323 | 0.017 | +| Vcco33 | 3.300 | 2.499 | 2.498 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.8 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++---------+-----------+ +| Name | Power (W) | ++---------+-----------+ +| encoder | 9.020 | +| unit | 0.017 | ++---------+-----------+ + + diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_power_summary_routed.pb b/Exp3-1/Exp3-1.runs/impl_1/encoder_power_summary_routed.pb new file mode 100644 index 0000000..71ebb88 Binary files /dev/null and b/Exp3-1/Exp3-1.runs/impl_1/encoder_power_summary_routed.pb differ diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_route_status.pb b/Exp3-1/Exp3-1.runs/impl_1/encoder_route_status.pb new file mode 100644 index 0000000..ac85a6c Binary files /dev/null and b/Exp3-1/Exp3-1.runs/impl_1/encoder_route_status.pb differ diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_route_status.rpt b/Exp3-1/Exp3-1.runs/impl_1/encoder_route_status.rpt new file mode 100644 index 0000000..d0b432f --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/encoder_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 85 : + # of nets not needing routing.......... : 43 : + # of internally routed nets........ : 43 : + # of routable nets..................... : 42 : + # of fully routed nets............. : 42 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_routed.dcp b/Exp3-1/Exp3-1.runs/impl_1/encoder_routed.dcp new file mode 100644 index 0000000..179fb5d Binary files /dev/null and b/Exp3-1/Exp3-1.runs/impl_1/encoder_routed.dcp differ diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_timing_summary_routed.pb b/Exp3-1/Exp3-1.runs/impl_1/encoder_timing_summary_routed.pb new file mode 100644 index 0000000..4526e93 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/encoder_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_timing_summary_routed.rpt b/Exp3-1/Exp3-1.runs/impl_1/encoder_timing_summary_routed.rpt new file mode 100644 index 0000000..180ab4d --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/encoder_timing_summary_routed.rpt @@ -0,0 +1,189 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Nov 6 20:20:40 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file encoder_timing_summary_routed.rpt -pb encoder_timing_summary_routed.pb -rpx encoder_timing_summary_routed.rpx -warn_on_violation +| Design : encoder +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 11 register/latch pins with no clock driven by root clock pin: en (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[0] (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[1] (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[2] (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[3] (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[4] (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[5] (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[6] (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[7] (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 11 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 7 input ports with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 15 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_utilization_placed.pb b/Exp3-1/Exp3-1.runs/impl_1/encoder_utilization_placed.pb new file mode 100644 index 0000000..4939752 Binary files /dev/null and b/Exp3-1/Exp3-1.runs/impl_1/encoder_utilization_placed.pb differ diff --git a/Exp3-1/Exp3-1.runs/impl_1/encoder_utilization_placed.rpt b/Exp3-1/Exp3-1.runs/impl_1/encoder_utilization_placed.rpt new file mode 100644 index 0000000..4888dc9 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/encoder_utilization_placed.rpt @@ -0,0 +1,203 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Nov 6 20:20:29 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file encoder_utilization_placed.rpt -pb encoder_utilization_placed.pb +| Design : encoder +| Device : 7a35tcsg324-1 +| Design State : Fully Placed +----------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 15 | 0 | 20800 | 0.07 | +| LUT as Logic | 15 | 0 | 20800 | 0.07 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 11 | 0 | 41600 | 0.03 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 11 | 0 | 41600 | 0.03 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 11 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 6 | 0 | 8150 | 0.07 | +| SLICEL | 2 | 0 | | | +| SLICEM | 4 | 0 | | | +| LUT as Logic | 15 | 0 | 20800 | 0.07 | +| using O5 output only | 0 | | | | +| using O6 output only | 7 | | | | +| using O5 and O6 | 8 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 8 | 0 | 20800 | 0.04 | +| fully used LUT-FF pairs | 0 | | | | +| LUT-FF pairs with one unused LUT output | 4 | | | | +| LUT-FF pairs with one unused Flip Flop | 8 | | | | +| Unique Control Sets | 1 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 40 | 40 | 210 | 19.05 | +| IOB Master Pads | 19 | | | | +| IOB Slave Pads | 21 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 31 | IO | +| LDCE | 11 | Flop & Latch | +| IBUF | 9 | IO | +| LUT3 | 7 | LUT | +| LUT1 | 7 | LUT | +| LUT6 | 3 | LUT | +| LUT4 | 3 | LUT | +| LUT5 | 2 | LUT | +| LUT2 | 1 | LUT | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp3-1/Exp3-1.runs/impl_1/gen_run.xml b/Exp3-1/Exp3-1.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..2b60460 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/gen_run.xml @@ -0,0 +1,113 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp3-1/Exp3-1.runs/impl_1/htr.txt b/Exp3-1/Exp3-1.runs/impl_1/htr.txt new file mode 100644 index 0000000..85e2ed7 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log encoder.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source encoder.tcl -notrace diff --git a/Exp3-1/Exp3-1.runs/impl_1/init_design.pb b/Exp3-1/Exp3-1.runs/impl_1/init_design.pb new file mode 100644 index 0000000..e3dfb66 Binary files /dev/null and b/Exp3-1/Exp3-1.runs/impl_1/init_design.pb differ diff --git a/Exp3-1/Exp3-1.runs/impl_1/opt_design.pb b/Exp3-1/Exp3-1.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..d34c5f2 Binary files /dev/null and b/Exp3-1/Exp3-1.runs/impl_1/opt_design.pb differ diff --git a/Exp3-1/Exp3-1.runs/impl_1/place_design.pb b/Exp3-1/Exp3-1.runs/impl_1/place_design.pb new file mode 100644 index 0000000..7712ed5 Binary files /dev/null and b/Exp3-1/Exp3-1.runs/impl_1/place_design.pb differ diff --git a/Exp3-1/Exp3-1.runs/impl_1/route_design.pb b/Exp3-1/Exp3-1.runs/impl_1/route_design.pb new file mode 100644 index 0000000..e3ce6a5 Binary files /dev/null and b/Exp3-1/Exp3-1.runs/impl_1/route_design.pb differ diff --git a/Exp3-1/Exp3-1.runs/impl_1/route_report_bus_skew_0.rpt b/Exp3-1/Exp3-1.runs/impl_1/route_report_bus_skew_0.rpt new file mode 100644 index 0000000..d741d3b --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/route_report_bus_skew_0.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Nov 6 20:20:40 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +| Design : encoder +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/Exp3-1/Exp3-1.runs/impl_1/usage_statistics_webtalk.xml b/Exp3-1/Exp3-1.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..33e91eb --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,619 @@ + + +
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+ diff --git a/Exp3-1/Exp3-1.runs/impl_1/vivado.jou b/Exp3-1/Exp3-1.runs/impl_1/vivado.jou new file mode 100644 index 0000000..8b76206 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 6 20:20:10 2024 +# Process ID: 22776 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1 +# Command line: vivado.exe -log encoder.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source encoder.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1/encoder.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source encoder.tcl -notrace diff --git a/Exp3-1/Exp3-1.runs/impl_1/vivado.pb b/Exp3-1/Exp3-1.runs/impl_1/vivado.pb new file mode 100644 index 0000000..ba21679 Binary files /dev/null and b/Exp3-1/Exp3-1.runs/impl_1/vivado.pb differ diff --git a/Exp3-1/Exp3-1.runs/impl_1/write_bitstream.pb b/Exp3-1/Exp3-1.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..05c61b2 Binary files /dev/null and b/Exp3-1/Exp3-1.runs/impl_1/write_bitstream.pb differ diff --git a/Exp3-1/Exp3-1.runs/synth_1/.Xil/encoder_propImpl.xdc b/Exp3-1/Exp3-1.runs/synth_1/.Xil/encoder_propImpl.xdc new file mode 100644 index 0000000..98434f4 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/synth_1/.Xil/encoder_propImpl.xdc @@ -0,0 +1,81 @@ +set_property SRC_FILE_INFO {cfile:F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc rfile:../../../Exp3-1.srcs/constrs_1/new/encoder.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B4 [get_ports {seg1[6]}] +set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN A4 [get_ports {seg1[5]}] +set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN A3 [get_ports {seg1[4]}] +set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B1 [get_ports {seg1[3]}] +set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN A1 [get_ports {seg1[2]}] +set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B3 [get_ports {seg1[1]}] +set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B2 [get_ports {seg1[0]}] +set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D4 [get_ports {seg2[7]}] +set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E3 [get_ports {seg2[6]}] +set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D3 [get_ports {seg2[5]}] +set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F4 [get_ports {seg2[4]}] +set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F3 [get_ports {seg2[3]}] +set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E2 [get_ports {seg2[2]}] +set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D2 [get_ports {seg2[1]}] +set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN H2 [get_ports {seg2[0]}] +set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G2 [get_ports {seg_cs1[3]}] +set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN C2 [get_ports {seg_cs1[2]}] +set_property src_info {type:XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN C1 [get_ports {seg_cs1[1]}] +set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN H1 [get_ports {seg_cs1[0]}] +set_property src_info {type:XDC file:1 line:59 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G1 [get_ports {seg_cs2[3]}] +set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F1 [get_ports {seg_cs2[2]}] +set_property src_info {type:XDC file:1 line:61 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E1 [get_ports {seg_cs2[1]}] +set_property src_info {type:XDC file:1 line:62 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G6 [get_ports {seg_cs2[0]}] +set_property src_info {type:XDC file:1 line:63 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P5 [get_ports {i[7]}] +set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P4 [get_ports {i[6]}] +set_property src_info {type:XDC file:1 line:65 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P3 [get_ports {i[5]}] +set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R2 [get_ports {i[3]}] +set_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P2 [get_ports {i[4]}] +set_property src_info {type:XDC file:1 line:68 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN M4 [get_ports {i[2]}] +set_property src_info {type:XDC file:1 line:69 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN N4 [get_ports {i[1]}] +set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R1 [get_ports {i[0]}] +set_property src_info {type:XDC file:1 line:71 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F6 [get_ports {i_sig[7]}] +set_property src_info {type:XDC file:1 line:72 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G4 [get_ports {i_sig[6]}] +set_property src_info {type:XDC file:1 line:73 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G3 [get_ports {i_sig[5]}] +set_property src_info {type:XDC file:1 line:74 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J4 [get_ports {i_sig[4]}] +set_property src_info {type:XDC file:1 line:75 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN H4 [get_ports {i_sig[3]}] +set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J3 [get_ports {i_sig[2]}] +set_property src_info {type:XDC file:1 line:77 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J2 [get_ports {i_sig[1]}] +set_property src_info {type:XDC file:1 line:78 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN K2 [get_ports {i_sig[0]}] +set_property src_info {type:XDC file:1 line:80 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U3 [get_ports en] diff --git a/Exp3-1/Exp3-1.runs/synth_1/encoder.dcp b/Exp3-1/Exp3-1.runs/synth_1/encoder.dcp new file mode 100644 index 0000000..7893ac2 Binary files /dev/null and b/Exp3-1/Exp3-1.runs/synth_1/encoder.dcp differ diff --git a/Exp3-1/Exp3-1.runs/synth_1/encoder.tcl b/Exp3-1/Exp3-1.runs/synth_1/encoder.tcl new file mode 100644 index 0000000..a6eb08e --- /dev/null +++ b/Exp3-1/Exp3-1.runs/synth_1/encoder.tcl @@ -0,0 +1,60 @@ +# +# Synthesis run script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param synth.incrementalSynthesisCache C:/Users/Launchcore/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-27428-W10-20240912132/incrSyn +set_param xicom.use_bs_reader 1 +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 +create_project -in_memory -part xc7a35tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.cache/wt [current_project] +set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib { + F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/SegDisplayCtrl.v + F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v +} +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc +set_property used_in_implementation false [get_files F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc] + +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top encoder -part xc7a35tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef encoder.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file encoder_utilization_synth.rpt -pb encoder_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/Exp3-1/Exp3-1.runs/synth_1/encoder.vds b/Exp3-1/Exp3-1.runs/synth_1/encoder.vds new file mode 100644 index 0000000..60d3905 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/synth_1/encoder.vds @@ -0,0 +1,306 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 6 20:19:40 2024 +# Process ID: 27608 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1 +# Command line: vivado.exe -log encoder.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source encoder.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1/encoder.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source encoder.tcl -notrace +Command: synth_design -top encoder -part xc7a35tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 26504 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 409.770 ; gain = 97.609 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'encoder' [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v:23] +INFO: [Synth 8-6157] synthesizing module 'SegDisplayCtrl' [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/SegDisplayCtrl.v:22] +INFO: [Synth 8-226] default block is never used [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/SegDisplayCtrl.v:29] +INFO: [Synth 8-6155] done synthesizing module 'SegDisplayCtrl' (1#1) [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/SegDisplayCtrl.v:22] +INFO: [Synth 8-6155] done synthesizing module 'encoder' (2#1) [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v:23] +WARNING: [Synth 8-3917] design encoder has port seg_cs1[3] driven by constant 0 +WARNING: [Synth 8-3917] design encoder has port seg_cs1[2] driven by constant 0 +WARNING: [Synth 8-3917] design encoder has port seg_cs1[1] driven by constant 0 +WARNING: [Synth 8-3917] design encoder has port seg_cs1[0] driven by constant 1 +WARNING: [Synth 8-3917] design encoder has port seg_cs2[3] driven by constant 0 +WARNING: [Synth 8-3917] design encoder has port seg_cs2[2] driven by constant 0 +WARNING: [Synth 8-3917] design encoder has port seg_cs2[1] driven by constant 0 +WARNING: [Synth 8-3917] design encoder has port seg_cs2[0] driven by constant 1 +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 464.227 ; gain = 152.066 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 464.227 ; gain = 152.066 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 464.227 ; gain = 152.066 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/encoder_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/encoder_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 745.281 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 745.281 ; gain = 433.121 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 745.281 ; gain = 433.121 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 745.281 ; gain = 433.121 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5546] ROM "out" won't be mapped to RAM because it is too sparse +WARNING: [Synth 8-327] inferring latch for variable 'i_sig_reg' [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v:40] +WARNING: [Synth 8-327] inferring latch for variable 'Y_reg' [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v:40] +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 745.281 ; gain = 433.121 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 9 Input 8 Bit Muxes := 1 + 8 Input 7 Bit Muxes := 1 + 9 Input 3 Bit Muxes := 2 + 9 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module encoder +Detailed RTL Component Info : ++---Muxes : + 9 Input 8 Bit Muxes := 1 + 9 Input 3 Bit Muxes := 2 + 9 Input 1 Bit Muxes := 1 +Module SegDisplayCtrl +Detailed RTL Component Info : ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 8 Input 7 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-5546] ROM "out" won't be mapped to RAM because it is too sparse +WARNING: [Synth 8-3917] design encoder has port seg2[6] driven by constant 0 +WARNING: [Synth 8-3917] design encoder has port seg2[5] driven by constant 0 +WARNING: [Synth 8-3917] design encoder has port seg_cs1[3] driven by constant 0 +WARNING: [Synth 8-3917] design encoder has port seg_cs1[2] driven by constant 0 +WARNING: [Synth 8-3917] design encoder has port seg_cs1[1] driven by constant 0 +WARNING: [Synth 8-3917] design encoder has port seg_cs1[0] driven by constant 1 +WARNING: [Synth 8-3917] design encoder has port seg_cs2[3] driven by constant 0 +WARNING: [Synth 8-3917] design encoder has port seg_cs2[2] driven by constant 0 +WARNING: [Synth 8-3917] design encoder has port seg_cs2[1] driven by constant 0 +WARNING: [Synth 8-3917] design encoder has port seg_cs2[0] driven by constant 1 +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 745.281 ; gain = 433.121 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 784.875 ; gain = 472.715 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 784.875 ; gain = 472.715 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 784.949 ; gain = 472.789 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT1 | 7| +|2 |LUT2 | 1| +|3 |LUT3 | 7| +|4 |LUT4 | 3| +|5 |LUT5 | 2| +|6 |LUT6 | 3| +|7 |LD | 11| +|8 |IBUF | 9| +|9 |OBUF | 31| ++------+-----+------+ + +Report Instance Areas: ++------+---------+---------------+------+ +| |Instance |Module |Cells | ++------+---------+---------------+------+ +|1 |top | | 74| +|2 | unit |SegDisplayCtrl | 5| ++------+---------+---------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 12 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 786.082 ; gain = 192.867 +Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.082 ; gain = 473.922 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 20 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 11 instances were transformed. + LD => LDCE: 11 instances + +INFO: [Common 17-83] Releasing license: Synthesis +19 Infos, 20 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 807.133 ; gain = 507.688 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1/encoder.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file encoder_utilization_synth.rpt -pb encoder_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 807.133 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Wed Nov 6 20:20:03 2024... diff --git a/Exp3-1/Exp3-1.runs/synth_1/encoder_utilization_synth.pb b/Exp3-1/Exp3-1.runs/synth_1/encoder_utilization_synth.pb new file mode 100644 index 0000000..b0cfcaf Binary files /dev/null and b/Exp3-1/Exp3-1.runs/synth_1/encoder_utilization_synth.pb differ diff --git a/Exp3-1/Exp3-1.runs/synth_1/encoder_utilization_synth.rpt b/Exp3-1/Exp3-1.runs/synth_1/encoder_utilization_synth.rpt new file mode 100644 index 0000000..80cccd4 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/synth_1/encoder_utilization_synth.rpt @@ -0,0 +1,176 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Wed Nov 6 20:20:03 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file encoder_utilization_synth.rpt -pb encoder_utilization_synth.pb +| Design : encoder +| Device : 7a35tcsg324-1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 16 | 0 | 20800 | 0.08 | +| LUT as Logic | 16 | 0 | 20800 | 0.08 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 11 | 0 | 41600 | 0.03 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 11 | 0 | 41600 | 0.03 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 11 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 40 | 0 | 210 | 19.05 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 31 | IO | +| LDCE | 11 | Flop & Latch | +| IBUF | 9 | IO | +| LUT3 | 7 | LUT | +| LUT1 | 7 | LUT | +| LUT6 | 3 | LUT | +| LUT4 | 3 | LUT | +| LUT5 | 2 | LUT | +| LUT2 | 1 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp3-1/Exp3-1.runs/synth_1/gen_run.xml b/Exp3-1/Exp3-1.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..c271e56 --- /dev/null +++ b/Exp3-1/Exp3-1.runs/synth_1/gen_run.xml @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp3-1/Exp3-1.runs/synth_1/htr.txt b/Exp3-1/Exp3-1.runs/synth_1/htr.txt new file mode 100644 index 0000000..69088ce --- /dev/null +++ b/Exp3-1/Exp3-1.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log encoder.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source encoder.tcl diff --git a/Exp3-1/Exp3-1.runs/synth_1/vivado.jou b/Exp3-1/Exp3-1.runs/synth_1/vivado.jou new file mode 100644 index 0000000..c8c637e --- /dev/null +++ b/Exp3-1/Exp3-1.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 6 20:19:40 2024 +# Process ID: 27608 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1 +# Command line: vivado.exe -log encoder.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source encoder.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1/encoder.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source encoder.tcl -notrace diff --git a/Exp3-1/Exp3-1.runs/synth_1/vivado.pb b/Exp3-1/Exp3-1.runs/synth_1/vivado.pb new file mode 100644 index 0000000..1c25230 Binary files /dev/null and b/Exp3-1/Exp3-1.runs/synth_1/vivado.pb differ diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/encoder.tcl b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/encoder.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/encoder.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/encoder_vlog.prj b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/encoder_vlog.prj new file mode 100644 index 0000000..4681e39 --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/encoder_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp3-1.srcs/sources_1/new/SegDisplayCtrl.v" \ +"../../../../Exp3-1.srcs/sources_1/new/encoder.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/glbl.v b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/tb_encoder.tcl b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/tb_encoder.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/tb_encoder.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/tb_encoder_vlog.prj b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/tb_encoder_vlog.prj new file mode 100644 index 0000000..7d637ee --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/tb_encoder_vlog.prj @@ -0,0 +1,11 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp3-1.srcs/sources_1/new/SegDisplayCtrl.v" \ +"../../../../Exp3-1.srcs/sources_1/new/encoder.v" \ +"../../../../Exp3-1.srcs/sim_1/new/tb_encoder.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk.jou b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..2226147 --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Nov 7 01:27:22 2024 +# Process ID: 29492 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk_16956.backup.jou b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk_16956.backup.jou new file mode 100644 index 0000000..63cacdd --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk_16956.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 31 10:47:51 2024 +# Process ID: 16956 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk_21852.backup.jou b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk_21852.backup.jou new file mode 100644 index 0000000..53d4b26 --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk_21852.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 6 20:00:38 2024 +# Process ID: 21852 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk_3000.backup.jou b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk_3000.backup.jou new file mode 100644 index 0000000..231af27 --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk_3000.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 31 10:28:31 2024 +# Process ID: 3000 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk_6888.backup.jou b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk_6888.backup.jou new file mode 100644 index 0000000..b1bbacc --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk_6888.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 31 10:28:45 2024 +# Process ID: 6888 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk_8340.backup.jou b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk_8340.backup.jou new file mode 100644 index 0000000..5e9c0a0 --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk_8340.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 31 10:23:45 2024 +# Process ID: 8340 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xelab.pb b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..8ab8251 Binary files /dev/null and b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/Compile_Options.txt b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/Compile_Options.txt new file mode 100644 index 0000000..26e5882 --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "a4b1bbaf8249442fb09839d8507c4712" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "encoder_behav" "xil_defaultlib.encoder" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/TempBreakPointFile.txt b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/obj/xsim_1.c b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/obj/xsim_1.c new file mode 100644 index 0000000..671dfbc --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/obj/xsim_1.c @@ -0,0 +1,111 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_2(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_4(char*, char *); +extern void execute_8(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[17] = {(funcp)execute_2, (funcp)execute_5, (funcp)execute_6, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_4, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 17; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/encoder_behav/xsim.reloc", (void **)funcTab, 17); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/encoder_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/encoder_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/encoder_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/encoder_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/encoder_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/xsim.mem b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/xsim.mem new file mode 100644 index 0000000..6d75499 Binary files /dev/null and b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/encoder_behav/xsim.mem differ diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/Compile_Options.txt b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/Compile_Options.txt new file mode 100644 index 0000000..9dde69e --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "a4b1bbaf8249442fb09839d8507c4712" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_encoder_behav" "xil_defaultlib.tb_encoder" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/TempBreakPointFile.txt b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/obj/xsim_1.c b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/obj/xsim_1.c new file mode 100644 index 0000000..029b220 --- /dev/null +++ b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/obj/xsim_1.c @@ -0,0 +1,116 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_7(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_3(char*, char *); +extern void execute_6(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_5(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_25(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[22] = {(funcp)execute_7, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_3, (funcp)execute_6, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_5, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 22; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/tb_encoder_behav/xsim.reloc", (void **)funcTab, 22); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/tb_encoder_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_encoder_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/tb_encoder_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/tb_encoder_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/tb_encoder_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/xsim.mem b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/xsim.mem new file mode 100644 index 0000000..3ed57e8 Binary files /dev/null and b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xsim.dir/tb_encoder_behav/xsim.mem differ diff --git a/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xvlog.pb b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..afec543 Binary files /dev/null and b/Exp3-1/Exp3-1.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc b/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc new file mode 100644 index 0000000..e9e6fa2 --- /dev/null +++ b/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc @@ -0,0 +1,80 @@ +set_property IOSTANDARD LVCMOS33 [get_ports {i[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[0]}] +set_property PACKAGE_PIN B4 [get_ports {seg1[6]}] +set_property PACKAGE_PIN A4 [get_ports {seg1[5]}] +set_property PACKAGE_PIN A3 [get_ports {seg1[4]}] +set_property PACKAGE_PIN B1 [get_ports {seg1[3]}] +set_property PACKAGE_PIN A1 [get_ports {seg1[2]}] +set_property PACKAGE_PIN B3 [get_ports {seg1[1]}] +set_property PACKAGE_PIN B2 [get_ports {seg1[0]}] +set_property PACKAGE_PIN D4 [get_ports {seg2[7]}] +set_property PACKAGE_PIN E3 [get_ports {seg2[6]}] +set_property PACKAGE_PIN D3 [get_ports {seg2[5]}] +set_property PACKAGE_PIN F4 [get_ports {seg2[4]}] +set_property PACKAGE_PIN F3 [get_ports {seg2[3]}] +set_property PACKAGE_PIN E2 [get_ports {seg2[2]}] +set_property PACKAGE_PIN D2 [get_ports {seg2[1]}] +set_property PACKAGE_PIN H2 [get_ports {seg2[0]}] +set_property PACKAGE_PIN G2 [get_ports {seg_cs1[3]}] +set_property PACKAGE_PIN C2 [get_ports {seg_cs1[2]}] +set_property PACKAGE_PIN C1 [get_ports {seg_cs1[1]}] +set_property PACKAGE_PIN H1 [get_ports {seg_cs1[0]}] +set_property PACKAGE_PIN G1 [get_ports {seg_cs2[3]}] +set_property PACKAGE_PIN F1 [get_ports {seg_cs2[2]}] +set_property PACKAGE_PIN E1 [get_ports {seg_cs2[1]}] +set_property PACKAGE_PIN G6 [get_ports {seg_cs2[0]}] +set_property PACKAGE_PIN P5 [get_ports {i[7]}] +set_property PACKAGE_PIN P4 [get_ports {i[6]}] +set_property PACKAGE_PIN P3 [get_ports {i[5]}] +set_property PACKAGE_PIN R2 [get_ports {i[3]}] +set_property PACKAGE_PIN P2 [get_ports {i[4]}] +set_property PACKAGE_PIN M4 [get_ports {i[2]}] +set_property PACKAGE_PIN N4 [get_ports {i[1]}] +set_property PACKAGE_PIN R1 [get_ports {i[0]}] +set_property PACKAGE_PIN F6 [get_ports {i_sig[7]}] +set_property PACKAGE_PIN G4 [get_ports {i_sig[6]}] +set_property PACKAGE_PIN G3 [get_ports {i_sig[5]}] +set_property PACKAGE_PIN J4 [get_ports {i_sig[4]}] +set_property PACKAGE_PIN H4 [get_ports {i_sig[3]}] +set_property PACKAGE_PIN J3 [get_ports {i_sig[2]}] +set_property PACKAGE_PIN J2 [get_ports {i_sig[1]}] +set_property PACKAGE_PIN K2 [get_ports {i_sig[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports en] +set_property PACKAGE_PIN U3 [get_ports en] diff --git a/Exp3-1/Exp3-1.srcs/sim_1/new/encoder_tb.v b/Exp3-1/Exp3-1.srcs/sim_1/new/encoder_tb.v new file mode 100644 index 0000000..669a0ed --- /dev/null +++ b/Exp3-1/Exp3-1.srcs/sim_1/new/encoder_tb.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/11/06 20:00:10 +// Design Name: +// Module Name: encoder_tb +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module encoder_tb( + + ); +endmodule diff --git a/Exp3-1/Exp3-1.srcs/sim_1/new/tb_encoder.v b/Exp3-1/Exp3-1.srcs/sim_1/new/tb_encoder.v new file mode 100644 index 0000000..4a6043a --- /dev/null +++ b/Exp3-1/Exp3-1.srcs/sim_1/new/tb_encoder.v @@ -0,0 +1,58 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/31 10:20:46 +// Design Name: +// Module Name: tb_encoder +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_encoder; + reg en; + reg [7:0] i; + wire [7:0] i_sig; + wire [6:0] seg1; + wire [7:0] seg2; + wire [3:0] seg_cs1; + wire [3:0] seg_cs2; + encoder uut ( + .en(en), + .i(i), + .i_sig(i_sig), + .seg1(seg1), + .seg2(seg2), + .seg_cs1(seg_cs1), + .seg_cs2(seg_cs2) + ); + initial begin + en = 0; + i = 8'b11111110; + #10; + en = 1; + i = 8'b11111110; #10; // Expected: Y = 3'b000, i_sig = 8'b00000001 + i = 8'b11111101; #10; // Expected: Y = 3'b001, i_sig = 8'b00000010 + i = 8'b11111011; #10; // Expected: Y = 3'b010, i_sig = 8'b00000100 + i = 8'b11110111; #10; // Expected: Y = 3'b011, i_sig = 8'b00001000 + i = 8'b11101111; #10; // Expected: Y = 3'b100, i_sig = 8'b00010000 + i = 8'b11011111; #10; // Expected: Y = 3'b101, i_sig = 8'b00100000 + i = 8'b10111111; #10; // Expected: Y = 3'b110, i_sig = 8'b01000000 + i = 8'b01111111; #10; // Expected: Y = 3'b111, i_sig = 8'b10000000 + i = 8'b00000000; #10; // Expected: out = 0, i_sig = undefined + en = 0; #10; // Expected: out = 0, i_sig = undefined + $finish; + end +endmodule + diff --git a/Exp3-1/Exp3-1.srcs/sources_1/new/SegDisplayCtrl.v b/Exp3-1/Exp3-1.srcs/sources_1/new/SegDisplayCtrl.v new file mode 100644 index 0000000..5573586 --- /dev/null +++ b/Exp3-1/Exp3-1.srcs/sources_1/new/SegDisplayCtrl.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/24 11:18:26 +// Design Name: +// Module Name: SegDisplayCtrl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module SegDisplayCtrl( + input wire [2:0] Y, + input wire out, + output reg [6:0] seg1, + output reg [7:0] seg2 +); +always @(*) begin + case (Y) + 3'b000: seg1 = 7'b1111110; // 0 + 3'b001: seg1 = 7'b0110000; // 1 + 3'b010: seg1 = 7'b1101101; // 2 + 3'b011: seg1 = 7'b1111001; // 3 + 3'b100: seg1 = 7'b0110011; // 4 + 3'b101: seg1 = 7'b1011011; // 5 + 3'b110: seg1 = 7'b1011111; // 6 + 3'b111: seg1 = 7'b1110000; // 7 + default: seg1 = 7'b0000000; + endcase + if (out) + seg2 = 8'b00000001; + else + seg2 = 8'b10011110; +end +endmodule diff --git a/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v b/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v new file mode 100644 index 0000000..f8aae9e --- /dev/null +++ b/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v @@ -0,0 +1,62 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/24 10:37:58 +// Design Name: +// Module Name: encoder +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module encoder( + input en, + input [7:0] i, + output reg [7:0] i_sig, + output wire [6:0] seg1, + output wire [7:0] seg2, + output reg [3:0] seg_cs1, + output reg [3:0] seg_cs2 + ); +reg out; +reg [2:0] Y; +always @(*) begin + out = 1; + if (en == 0) + out = 0; + else begin + case (i) + 8'b11111110: begin Y = 3'b000; i_sig = 8'b00000001; end + 8'b11111101: begin Y = 3'b001; i_sig = 8'b00000010; end + 8'b11111011: begin Y = 3'b010; i_sig = 8'b00000100; end + 8'b11110111: begin Y = 3'b011; i_sig = 8'b00001000; end + 8'b11101111: begin Y = 3'b100; i_sig = 8'b00010000; end + 8'b11011111: begin Y = 3'b101; i_sig = 8'b00100000; end + 8'b10111111: begin Y = 3'b110; i_sig = 8'b01000000; end + 8'b01111111: begin Y = 3'b111; i_sig = 8'b10000000; end + default: out = 0; + endcase + end +end +SegDisplayCtrl unit ( + .Y(Y), + .out(out), + .seg1(seg1), + .seg2(seg2) +); +always @(*) begin + seg_cs1 = 4'b0001; + seg_cs2 = 4'b0001; +end +endmodule diff --git a/Exp3-1/Exp3-1.xpr b/Exp3-1/Exp3-1.xpr new file mode 100644 index 0000000..92d1aa9 --- /dev/null +++ b/Exp3-1/Exp3-1.xpr @@ -0,0 +1,158 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp3-1/vivado.jou b/Exp3-1/vivado.jou new file mode 100644 index 0000000..d29a3b8 --- /dev/null +++ b/Exp3-1/vivado.jou @@ -0,0 +1,14 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Sun Dec 1 21:45:21 2024 +# Process ID: 5340 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-1 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent15060 F:\Schoolwork\DigitalLogic\Exp3-1\Exp3-1.xpr +# Log file: F:/Schoolwork/DigitalLogic/Exp3-1/vivado.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-1\vivado.jou +#----------------------------------------------------------- +start_gui +open_project F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.xpr +update_compile_order -fileset sources_1 diff --git a/Exp3-1/vivado_12112.backup.jou b/Exp3-1/vivado_12112.backup.jou new file mode 100644 index 0000000..b734acb --- /dev/null +++ b/Exp3-1/vivado_12112.backup.jou @@ -0,0 +1,67 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Oct 30 22:27:06 2024 +# Process ID: 12112 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-1 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent2764 F:\Schoolwork\DigitalLogic\Exp3-1\Exp3-1.xpr +# Log file: F:/Schoolwork/DigitalLogic/Exp3-1/vivado.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-1\vivado.jou +#----------------------------------------------------------- +start_gui +open_project F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.xpr +update_compile_order -fileset sources_1 +reset_run synth_1 +launch_runs synth_1 -jobs 10 +wait_on_run synth_1 +open_run synth_1 -name synth_1 +launch_runs impl_1 -jobs 10 +wait_on_run impl_1 +launch_runs impl_1 -to_step write_bitstream -jobs 10 +wait_on_run impl_1 +open_hw +connect_hw_server +open_hw_target +set_property PROGRAM.FILE {F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1/encoder.bit} [get_hw_devices xc7a35t_0] +current_hw_device [get_hw_devices xc7a35t_0] +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0] +set_property PROBES.FILE {} [get_hw_devices xc7a35t_0] +set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0] +set_property PROGRAM.FILE {F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1/encoder.bit} [get_hw_devices xc7a35t_0] +program_hw_devices [get_hw_devices xc7a35t_0] +refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0] +close_hw +reset_run synth_1 +launch_runs impl_1 -to_step write_bitstream -jobs 10 +wait_on_run impl_1 +reset_run synth_1 +launch_runs impl_1 -to_step write_bitstream -jobs 10 +wait_on_run impl_1 +refresh_design +close_design +reset_run synth_1 +launch_runs synth_1 -jobs 10 +wait_on_run synth_1 +open_run synth_1 -name synth_1 +launch_runs impl_1 -jobs 10 +wait_on_run impl_1 +reset_run synth_1 +launch_runs synth_1 -jobs 10 +wait_on_run synth_1 +launch_runs impl_1 -jobs 10 +wait_on_run impl_1 +launch_runs impl_1 -to_step write_bitstream -jobs 10 +wait_on_run impl_1 +open_hw +connect_hw_server +open_hw_target +set_property PROGRAM.FILE {F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1/encoder.bit} [get_hw_devices xc7a35t_0] +current_hw_device [get_hw_devices xc7a35t_0] +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0] +set_property PROBES.FILE {} [get_hw_devices xc7a35t_0] +set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0] +set_property PROGRAM.FILE {F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/impl_1/encoder.bit} [get_hw_devices xc7a35t_0] +program_hw_devices [get_hw_devices xc7a35t_0] +refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0] +close_hw diff --git a/Exp3-2/Exp3-2.cache/wt/webtalk_pa.xml b/Exp3-2/Exp3-2.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..3b2a7ae --- /dev/null +++ b/Exp3-2/Exp3-2.cache/wt/webtalk_pa.xml @@ -0,0 +1,81 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp3-2/Exp3-2.hw/hw_1/hw.xml b/Exp3-2/Exp3-2.hw/hw_1/hw.xml new file mode 100644 index 0000000..6148bd5 --- /dev/null +++ b/Exp3-2/Exp3-2.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/Exp3-2/Exp3-2.ip_user_files/README.txt b/Exp3-2/Exp3-2.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp3-2/Exp3-2.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp3-2/Exp3-2.runs/.jobs/vrs_config_1.xml b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..6415fda --- /dev/null +++ b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-2/Exp3-2.runs/.jobs/vrs_config_2.xml b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..9b231fb --- /dev/null +++ b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-2/Exp3-2.runs/.jobs/vrs_config_3.xml b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..bb30f78 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-2/Exp3-2.runs/.jobs/vrs_config_4.xml b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..ab293f7 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp3-2/Exp3-2.runs/.jobs/vrs_config_5.xml b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..ab293f7 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp3-2/Exp3-2.runs/.jobs/vrs_config_6.xml b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..ab293f7 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp3-2/Exp3-2.runs/.jobs/vrs_config_7.xml b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..ab293f7 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp3-2/Exp3-2.runs/.jobs/vrs_config_8.xml b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..caa3f5c --- /dev/null +++ b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp3-2/Exp3-2.runs/.jobs/vrs_config_9.xml b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..bb30f78 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp3-2/Exp3-2.runs/impl_1/gen_run.xml b/Exp3-2/Exp3-2.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..6aa6239 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/gen_run.xml @@ -0,0 +1,96 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp3-2/Exp3-2.runs/impl_1/htr.txt b/Exp3-2/Exp3-2.runs/impl_1/htr.txt new file mode 100644 index 0000000..137bb5a --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log prior_encoder.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source prior_encoder.tcl -notrace diff --git a/Exp3-2/Exp3-2.runs/impl_1/init_design.pb b/Exp3-2/Exp3-2.runs/impl_1/init_design.pb new file mode 100644 index 0000000..ef55daa Binary files /dev/null and b/Exp3-2/Exp3-2.runs/impl_1/init_design.pb differ diff --git a/Exp3-2/Exp3-2.runs/impl_1/opt_design.pb b/Exp3-2/Exp3-2.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..77df7a6 Binary files /dev/null and b/Exp3-2/Exp3-2.runs/impl_1/opt_design.pb differ diff --git a/Exp3-2/Exp3-2.runs/impl_1/place_design.pb b/Exp3-2/Exp3-2.runs/impl_1/place_design.pb new file mode 100644 index 0000000..0d1e6fe Binary files /dev/null and b/Exp3-2/Exp3-2.runs/impl_1/place_design.pb differ diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder.tcl b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder.tcl new file mode 100644 index 0000000..8c91aa2 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder.tcl @@ -0,0 +1,87 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + set_param synth.incrementalSynthesisCache C:/Users/Launchcore/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-18036-W10-20240912132/incrSyn + set_param xicom.use_bs_reader 1 + open_checkpoint prior_encoder_routed.dcp + set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.cache/wt [current_project] + catch { write_mem_info -force prior_encoder.mmi } + write_bitstream -force prior_encoder.bit + catch {write_debug_probes -quiet -force prior_encoder} + catch {file copy -force prior_encoder.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder.vdi b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder.vdi new file mode 100644 index 0000000..c252953 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder.vdi @@ -0,0 +1,489 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 31 10:39:06 2024 +# Process ID: 10496 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1 +# Command line: vivado.exe -log prior_encoder.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source prior_encoder.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source prior_encoder.tcl -notrace +Command: link_design -top prior_encoder -part xc7a35tcsg324-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/constrs_1/new/encoder.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/constrs_1/new/encoder.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 607.816 ; gain = 302.820 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.399 . Memory (MB): peak = 621.617 ; gain = 13.801 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1169.441 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1169.441 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1169.441 ; gain = 561.625 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file prior_encoder_drc_opted.rpt -pb prior_encoder_drc_opted.pb -rpx prior_encoder_drc_opted.rpx +Command: report_drc -file prior_encoder_drc_opted.rpt -pb prior_encoder_drc_opted.pb -rpx prior_encoder_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1169.441 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 10b3cc5b1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1169.441 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1169.441 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 10b3cc5b1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.462 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1e2cf7632 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.472 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1e2cf7632 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.473 . Memory (MB): peak = 1182.070 ; gain = 12.629 +Phase 1 Placer Initialization | Checksum: 1e2cf7632 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.473 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 18e95721a + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.646 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 18e95721a + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.647 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1766832ee + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.655 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1a96c420c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.658 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1a96c420c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.659 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.705 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.707 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.708 . Memory (MB): peak = 1182.070 ; gain = 12.629 +Phase 3 Detail Placement | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.708 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.710 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.712 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.712 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.713 . Memory (MB): peak = 1182.070 ; gain = 12.629 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.713 . Memory (MB): peak = 1182.070 ; gain = 12.629 +Ending Placer Task | Checksum: e791b51c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.715 . Memory (MB): peak = 1182.070 ; gain = 12.629 +INFO: [Common 17-83] Releasing license: Implementation +41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1182.070 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file prior_encoder_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1187.117 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file prior_encoder_utilization_placed.rpt -pb prior_encoder_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1187.117 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file prior_encoder_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1187.117 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: d11c5d6 ConstDB: 0 ShapeSum: da7fef46 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 112c02765 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1301.633 ; gain = 114.516 +Post Restoration Checksum: NetGraph: 75abcc6c NumContArr: 9d145af9 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 112c02765 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1307.668 ; gain = 120.551 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 112c02765 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1307.668 ; gain = 120.551 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 1c130cb9b + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.371 ; gain = 122.254 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 1243fa08a + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.371 ; gain = 122.254 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 6 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 18460bc16 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281 +Phase 4 Rip-up And Reroute | Checksum: 18460bc16 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 18460bc16 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 18460bc16 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281 +Phase 6 Post Hold Fix | Checksum: 18460bc16 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0509447 % + Global Horizontal Routing Utilization = 0.0118428 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 39.6396%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 25%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 18460bc16 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 18460bc16 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1311.676 ; gain = 124.559 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: ab5fb207 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1311.676 ; gain = 124.559 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1311.676 ; gain = 124.559 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1311.676 ; gain = 124.559 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1311.676 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file prior_encoder_drc_routed.rpt -pb prior_encoder_drc_routed.pb -rpx prior_encoder_drc_routed.rpx +Command: report_drc -file prior_encoder_drc_routed.rpt -pb prior_encoder_drc_routed.pb -rpx prior_encoder_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file prior_encoder_methodology_drc_routed.rpt -pb prior_encoder_methodology_drc_routed.pb -rpx prior_encoder_methodology_drc_routed.rpx +Command: report_methodology -file prior_encoder_methodology_drc_routed.rpt -pb prior_encoder_methodology_drc_routed.pb -rpx prior_encoder_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file prior_encoder_power_routed.rpt -pb prior_encoder_power_summary_routed.pb -rpx prior_encoder_power_routed.rpx +Command: report_power -file prior_encoder_power_routed.rpt -pb prior_encoder_power_summary_routed.pb -rpx prior_encoder_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file prior_encoder_route_status.rpt -pb prior_encoder_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file prior_encoder_timing_summary_routed.rpt -pb prior_encoder_timing_summary_routed.pb -rpx prior_encoder_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file prior_encoder_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file prior_encoder_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Thu Oct 31 10:39:45 2024... +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 6 20:31:21 2024 +# Process ID: 24740 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1 +# Command line: vivado.exe -log prior_encoder.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source prior_encoder.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source prior_encoder.tcl -notrace +Command: open_checkpoint prior_encoder_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 240.996 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1126.773 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1126.773 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600 +open_checkpoint: Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1126.773 ; gain = 894.855 +Command: write_bitstream -force prior_encoder.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +WARNING: [DRC PDRC-153] Gated clock check: Net Y_reg[2]_i_2_n_0 is a gated clock net sourced by a combinational pin Y_reg[2]_i_2/O, cell Y_reg[2]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net i_sig_reg[7]_i_2_n_0 is a gated clock net sourced by a combinational pin i_sig_reg[7]_i_2/O, cell i_sig_reg[7]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 3 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./prior_encoder.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +22 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1592.254 ; gain = 465.480 +INFO: [Common 17-206] Exiting Vivado at Wed Nov 6 20:31:44 2024... diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_10496.backup.vdi b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_10496.backup.vdi new file mode 100644 index 0000000..76c3c3d --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_10496.backup.vdi @@ -0,0 +1,416 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 31 10:39:06 2024 +# Process ID: 10496 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1 +# Command line: vivado.exe -log prior_encoder.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source prior_encoder.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source prior_encoder.tcl -notrace +Command: link_design -top prior_encoder -part xc7a35tcsg324-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/constrs_1/new/encoder.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/constrs_1/new/encoder.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 607.816 ; gain = 302.820 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.399 . Memory (MB): peak = 621.617 ; gain = 13.801 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1169.441 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1169.441 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1a0efe7be + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1169.441 ; gain = 561.625 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1169.441 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file prior_encoder_drc_opted.rpt -pb prior_encoder_drc_opted.pb -rpx prior_encoder_drc_opted.rpx +Command: report_drc -file prior_encoder_drc_opted.rpt -pb prior_encoder_drc_opted.pb -rpx prior_encoder_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1169.441 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 10b3cc5b1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1169.441 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1169.441 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 10b3cc5b1 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.462 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1e2cf7632 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.472 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1e2cf7632 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.473 . Memory (MB): peak = 1182.070 ; gain = 12.629 +Phase 1 Placer Initialization | Checksum: 1e2cf7632 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.473 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 18e95721a + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.646 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 18e95721a + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.647 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1766832ee + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.655 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1a96c420c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.658 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1a96c420c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.659 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.705 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.707 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.708 . Memory (MB): peak = 1182.070 ; gain = 12.629 +Phase 3 Detail Placement | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.708 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.710 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.712 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.712 . Memory (MB): peak = 1182.070 ; gain = 12.629 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.713 . Memory (MB): peak = 1182.070 ; gain = 12.629 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 143829d4b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.713 . Memory (MB): peak = 1182.070 ; gain = 12.629 +Ending Placer Task | Checksum: e791b51c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.715 . Memory (MB): peak = 1182.070 ; gain = 12.629 +INFO: [Common 17-83] Releasing license: Implementation +41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1182.070 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file prior_encoder_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1187.117 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file prior_encoder_utilization_placed.rpt -pb prior_encoder_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1187.117 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file prior_encoder_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1187.117 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: d11c5d6 ConstDB: 0 ShapeSum: da7fef46 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 112c02765 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1301.633 ; gain = 114.516 +Post Restoration Checksum: NetGraph: 75abcc6c NumContArr: 9d145af9 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 112c02765 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1307.668 ; gain = 120.551 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 112c02765 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1307.668 ; gain = 120.551 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 1c130cb9b + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.371 ; gain = 122.254 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 1243fa08a + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.371 ; gain = 122.254 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 6 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 18460bc16 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281 +Phase 4 Rip-up And Reroute | Checksum: 18460bc16 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 18460bc16 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 18460bc16 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281 +Phase 6 Post Hold Fix | Checksum: 18460bc16 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0509447 % + Global Horizontal Routing Utilization = 0.0118428 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 39.6396%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 25%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 18460bc16 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.398 ; gain = 122.281 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 18460bc16 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1311.676 ; gain = 124.559 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: ab5fb207 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1311.676 ; gain = 124.559 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1311.676 ; gain = 124.559 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1311.676 ; gain = 124.559 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1311.676 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file prior_encoder_drc_routed.rpt -pb prior_encoder_drc_routed.pb -rpx prior_encoder_drc_routed.rpx +Command: report_drc -file prior_encoder_drc_routed.rpt -pb prior_encoder_drc_routed.pb -rpx prior_encoder_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file prior_encoder_methodology_drc_routed.rpt -pb prior_encoder_methodology_drc_routed.pb -rpx prior_encoder_methodology_drc_routed.rpx +Command: report_methodology -file prior_encoder_methodology_drc_routed.rpt -pb prior_encoder_methodology_drc_routed.pb -rpx prior_encoder_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file prior_encoder_power_routed.rpt -pb prior_encoder_power_summary_routed.pb -rpx prior_encoder_power_routed.rpx +Command: report_power -file prior_encoder_power_routed.rpt -pb prior_encoder_power_summary_routed.pb -rpx prior_encoder_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file prior_encoder_route_status.rpt -pb prior_encoder_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file prior_encoder_timing_summary_routed.rpt -pb prior_encoder_timing_summary_routed.pb -rpx prior_encoder_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file prior_encoder_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file prior_encoder_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Thu Oct 31 10:39:45 2024... diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_clock_utilization_routed.rpt b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_clock_utilization_routed.rpt new file mode 100644 index 0000000..19d61c3 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_clock_utilization_routed.rpt @@ -0,0 +1,92 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 31 10:39:45 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file prior_encoder_clock_utilization_routed.rpt +| Design : prior_encoder +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 0 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_control_sets_placed.rpt b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_control_sets_placed.rpt new file mode 100644 index 0000000..03fc6a1 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_control_sets_placed.rpt @@ -0,0 +1,67 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 31 10:39:30 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file prior_encoder_control_sets_placed.rpt +| Design : prior_encoder +| Device : xc7a35t +------------------------------------------------------------------------------------------ + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 2 | +| Unused register locations in slices containing registers | 5 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ +| 3 | 1 | +| 8 | 1 | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 8 | 2 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 3 | 1 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++-----------------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++-----------------------+---------------+------------------+------------------+----------------+ +| Y_reg[2]_i_2_n_0 | | Y_reg[2]_i_3_n_0 | 1 | 3 | +| i_sig_reg[7]_i_2_n_0 | | | 2 | 8 | ++-----------------------+---------------+------------------+------------------+----------------+ + + diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_opted.pb b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_opted.pb differ diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_opted.rpt b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_opted.rpt new file mode 100644 index 0000000..ac58d4e --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 31 10:39:29 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file prior_encoder_drc_opted.rpt -pb prior_encoder_drc_opted.pb -rpx prior_encoder_drc_opted.rpx +| Design : prior_encoder +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_routed.pb b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_routed.pb new file mode 100644 index 0000000..cb5bb32 Binary files /dev/null and b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_routed.pb differ diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_routed.rpt b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_routed.rpt new file mode 100644 index 0000000..ac170e1 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_drc_routed.rpt @@ -0,0 +1,60 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 31 10:39:44 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file prior_encoder_drc_routed.rpt -pb prior_encoder_drc_routed.pb -rpx prior_encoder_drc_routed.rpx +| Design : prior_encoder +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 3 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| PDRC-153 | Warning | Gated clock check | 2 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +PDRC-153#1 Warning +Gated clock check +Net Y_reg[2]_i_2_n_0 is a gated clock net sourced by a combinational pin Y_reg[2]_i_2/O, cell Y_reg[2]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#2 Warning +Gated clock check +Net i_sig_reg[7]_i_2_n_0 is a gated clock net sourced by a combinational pin i_sig_reg[7]_i_2/O, cell i_sig_reg[7]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + + diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_io_placed.rpt b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_io_placed.rpt new file mode 100644 index 0000000..0bf7d92 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_io_placed.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 31 10:39:30 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_io -file prior_encoder_io_placed.rpt +| Design : prior_encoder +| Device : xc7a35t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2013-12-19 +| Package Pin Delay Version : VERS. 2.0 2013-12-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 40 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | seg1[2] | High Range | IO_L9N_T1_DQS_AD7N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | seg1[4] | High Range | IO_L8N_T1_AD14N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A4 | seg1[5] | High Range | IO_L8P_T1_AD14P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | seg1[3] | High Range | IO_L9P_T1_DQS_AD7P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B2 | seg1[0] | High Range | IO_L10N_T1_AD15N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B3 | seg1[1] | High Range | IO_L10P_T1_AD15P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B4 | seg1[6] | High Range | IO_L7N_T1_AD6N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | seg_cs1[1] | High Range | IO_L16N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C2 | seg_cs1[2] | High Range | IO_L16P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | seg2[1] | High Range | IO_L14N_T2_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D3 | seg2[5] | High Range | IO_L12N_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D4 | seg2[7] | High Range | IO_L11N_T1_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | seg_cs2[1] | High Range | IO_L18N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E2 | seg2[2] | High Range | IO_L14P_T2_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E3 | seg2[6] | High Range | IO_L12P_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | seg_cs2[2] | High Range | IO_L18P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | seg2[3] | High Range | IO_L13N_T2_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F4 | seg2[4] | High Range | IO_L13P_T2_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | i_sig[7] | High Range | IO_L19N_T3_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | seg_cs2[3] | High Range | IO_L17N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G2 | seg_cs1[3] | High Range | IO_L15N_T2_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G3 | i_sig[5] | High Range | IO_L20N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G4 | i_sig[6] | High Range | IO_L20P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | seg_cs2[0] | High Range | IO_L19P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | seg_cs1[0] | High Range | IO_L17P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| H2 | seg2[0] | High Range | IO_L15P_T2_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | i_sig[3] | High Range | IO_L21N_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | i_sig[1] | High Range | IO_L22N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J3 | i_sig[2] | High Range | IO_L22P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J4 | i_sig[4] | High Range | IO_L21P_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | i_sig[0] | High Range | IO_L23P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | i[2] | High Range | IO_L16P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N4 | i[1] | High Range | IO_L16N_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | i[4] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P3 | i[5] | High Range | IO_L14N_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P4 | i[6] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P5 | i[7] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | i[0] | High Range | IO_L17P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| R2 | i[3] | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | en | High Range | IO_L8N_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_methodology_drc_routed.pb b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_methodology_drc_routed.pb new file mode 100644 index 0000000..9c1940f Binary files /dev/null and b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_methodology_drc_routed.pb differ diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_methodology_drc_routed.rpt b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_methodology_drc_routed.rpt new file mode 100644 index 0000000..b316e10 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_methodology_drc_routed.rpt @@ -0,0 +1,90 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 31 10:39:44 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_methodology -file prior_encoder_methodology_drc_routed.rpt -pb prior_encoder_methodology_drc_routed.pb -rpx prior_encoder_methodology_drc_routed.rpx +| Design : prior_encoder +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 11 ++-----------+----------+-------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-------------------+------------+ +| TIMING-20 | Warning | Non-clocked latch | 11 | ++-----------+----------+-------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-20#1 Warning +Non-clocked latch +The latch Y_reg[0] cannot be properly analyzed as its control pin Y_reg[0]/G is not reached by a timing clock +Related violations: + +TIMING-20#2 Warning +Non-clocked latch +The latch Y_reg[1] cannot be properly analyzed as its control pin Y_reg[1]/G is not reached by a timing clock +Related violations: + +TIMING-20#3 Warning +Non-clocked latch +The latch Y_reg[2] cannot be properly analyzed as its control pin Y_reg[2]/G is not reached by a timing clock +Related violations: + +TIMING-20#4 Warning +Non-clocked latch +The latch i_sig_reg[0] cannot be properly analyzed as its control pin i_sig_reg[0]/G is not reached by a timing clock +Related violations: + +TIMING-20#5 Warning +Non-clocked latch +The latch i_sig_reg[1] cannot be properly analyzed as its control pin i_sig_reg[1]/G is not reached by a timing clock +Related violations: + +TIMING-20#6 Warning +Non-clocked latch +The latch i_sig_reg[2] cannot be properly analyzed as its control pin i_sig_reg[2]/G is not reached by a timing clock +Related violations: + +TIMING-20#7 Warning +Non-clocked latch +The latch i_sig_reg[3] cannot be properly analyzed as its control pin i_sig_reg[3]/G is not reached by a timing clock +Related violations: + +TIMING-20#8 Warning +Non-clocked latch +The latch i_sig_reg[4] cannot be properly analyzed as its control pin i_sig_reg[4]/G is not reached by a timing clock +Related violations: + +TIMING-20#9 Warning +Non-clocked latch +The latch i_sig_reg[5] cannot be properly analyzed as its control pin i_sig_reg[5]/G is not reached by a timing clock +Related violations: + +TIMING-20#10 Warning +Non-clocked latch +The latch i_sig_reg[6] cannot be properly analyzed as its control pin i_sig_reg[6]/G is not reached by a timing clock +Related violations: + +TIMING-20#11 Warning +Non-clocked latch +The latch i_sig_reg[7] cannot be properly analyzed as its control pin i_sig_reg[7]/G is not reached by a timing clock +Related violations: + + diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_opt.dcp b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_opt.dcp new file mode 100644 index 0000000..e0539ce Binary files /dev/null and b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_opt.dcp differ diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_placed.dcp b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_placed.dcp new file mode 100644 index 0000000..720fc3e Binary files /dev/null and b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_placed.dcp differ diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_power_routed.rpt b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_power_routed.rpt new file mode 100644 index 0000000..2cf7dcc --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_power_routed.rpt @@ -0,0 +1,143 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 31 10:39:44 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_power -file prior_encoder_power_routed.rpt -pb prior_encoder_power_summary_routed.pb -rpx prior_encoder_power_routed.rpx +| Design : prior_encoder +| Device : xc7a35tcsg324-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.446 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.374 | +| Device Static (W) | 0.072 | +| Effective TJA (C/W) | 4.8 | +| Max Ambient (C) | 82.9 | +| Junction Temperature (C) | 27.1 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.045 | 42 | --- | --- | +| LUT as Logic | 0.045 | 18 | 20800 | 0.09 | +| Others | 0.000 | 4 | --- | --- | +| Register | 0.000 | 11 | 41600 | 0.03 | +| Signals | 0.081 | 46 | --- | --- | +| I/O | 0.248 | 40 | 210 | 19.05 | +| Static Power | 0.072 | | | | +| Total | 0.446 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.168 | 0.158 | 0.010 | +| Vccaux | 1.800 | 0.021 | 0.008 | 0.013 | +| Vcco33 | 3.300 | 0.062 | 0.061 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.8 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++---------------+-----------+ +| Name | Power (W) | ++---------------+-----------+ +| prior_encoder | 0.374 | +| unit | <0.001 | ++---------------+-----------+ + + diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_power_summary_routed.pb b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_power_summary_routed.pb new file mode 100644 index 0000000..e8ac55b Binary files /dev/null and b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_power_summary_routed.pb differ diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_route_status.pb b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_route_status.pb new file mode 100644 index 0000000..933ea7c Binary files /dev/null and b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_route_status.pb differ diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_route_status.rpt b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_route_status.rpt new file mode 100644 index 0000000..b8028d8 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 89 : + # of nets not needing routing.......... : 41 : + # of internally routed nets........ : 41 : + # of routable nets..................... : 48 : + # of fully routed nets............. : 48 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_routed.dcp b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_routed.dcp new file mode 100644 index 0000000..a8f5881 Binary files /dev/null and b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_routed.dcp differ diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_timing_summary_routed.pb b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_timing_summary_routed.pb new file mode 100644 index 0000000..4526e93 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_timing_summary_routed.rpt b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_timing_summary_routed.rpt new file mode 100644 index 0000000..9a8506b --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_timing_summary_routed.rpt @@ -0,0 +1,189 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 31 10:39:44 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file prior_encoder_timing_summary_routed.rpt -pb prior_encoder_timing_summary_routed.pb -rpx prior_encoder_timing_summary_routed.rpx -warn_on_violation +| Design : prior_encoder +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 8 register/latch pins with no clock driven by root clock pin: en (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[0] (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[1] (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[2] (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[3] (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[4] (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[5] (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[6] (HIGH) + + There are 11 register/latch pins with no clock driven by root clock pin: i[7] (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 14 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 9 input ports with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 15 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_utilization_placed.pb b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_utilization_placed.pb new file mode 100644 index 0000000..66462c7 Binary files /dev/null and b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_utilization_placed.pb differ diff --git a/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_utilization_placed.rpt b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_utilization_placed.rpt new file mode 100644 index 0000000..dfd2a4a --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/prior_encoder_utilization_placed.rpt @@ -0,0 +1,203 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 31 10:39:30 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file prior_encoder_utilization_placed.rpt -pb prior_encoder_utilization_placed.pb +| Design : prior_encoder +| Device : 7a35tcsg324-1 +| Design State : Fully Placed +----------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 18 | 0 | 20800 | 0.09 | +| LUT as Logic | 18 | 0 | 20800 | 0.09 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 11 | 0 | 41600 | 0.03 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 11 | 0 | 41600 | 0.03 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 11 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 6 | 0 | 8150 | 0.07 | +| SLICEL | 2 | 0 | | | +| SLICEM | 4 | 0 | | | +| LUT as Logic | 18 | 0 | 20800 | 0.09 | +| using O5 output only | 0 | | | | +| using O6 output only | 9 | | | | +| using O5 and O6 | 9 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 6 | 0 | 20800 | 0.03 | +| fully used LUT-FF pairs | 0 | | | | +| LUT-FF pairs with one unused LUT output | 4 | | | | +| LUT-FF pairs with one unused Flip Flop | 6 | | | | +| Unique Control Sets | 2 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 40 | 40 | 210 | 19.05 | +| IOB Master Pads | 19 | | | | +| IOB Slave Pads | 21 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 31 | IO | +| LDCE | 11 | Flop & Latch | +| IBUF | 9 | IO | +| LUT3 | 8 | LUT | +| LUT6 | 6 | LUT | +| LUT5 | 5 | LUT | +| LUT4 | 4 | LUT | +| LUT2 | 3 | LUT | +| LUT1 | 1 | LUT | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp3-2/Exp3-2.runs/impl_1/route_design.pb b/Exp3-2/Exp3-2.runs/impl_1/route_design.pb new file mode 100644 index 0000000..54b3fc5 Binary files /dev/null and b/Exp3-2/Exp3-2.runs/impl_1/route_design.pb differ diff --git a/Exp3-2/Exp3-2.runs/impl_1/route_report_bus_skew_0.rpt b/Exp3-2/Exp3-2.runs/impl_1/route_report_bus_skew_0.rpt new file mode 100644 index 0000000..dd78c92 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/route_report_bus_skew_0.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 31 10:39:45 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +| Design : prior_encoder +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/Exp3-2/Exp3-2.runs/impl_1/usage_statistics_webtalk.xml b/Exp3-2/Exp3-2.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..ac6d02e --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,463 @@ + + +
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+ diff --git a/Exp3-2/Exp3-2.runs/impl_1/vivado.jou b/Exp3-2/Exp3-2.runs/impl_1/vivado.jou new file mode 100644 index 0000000..32ced8f --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 6 20:31:21 2024 +# Process ID: 24740 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1 +# Command line: vivado.exe -log prior_encoder.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source prior_encoder.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source prior_encoder.tcl -notrace diff --git a/Exp3-2/Exp3-2.runs/impl_1/vivado.pb b/Exp3-2/Exp3-2.runs/impl_1/vivado.pb new file mode 100644 index 0000000..15676cc Binary files /dev/null and b/Exp3-2/Exp3-2.runs/impl_1/vivado.pb differ diff --git a/Exp3-2/Exp3-2.runs/impl_1/vivado_10496.backup.jou b/Exp3-2/Exp3-2.runs/impl_1/vivado_10496.backup.jou new file mode 100644 index 0000000..31ca2f5 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/impl_1/vivado_10496.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 31 10:39:06 2024 +# Process ID: 10496 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1 +# Command line: vivado.exe -log prior_encoder.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source prior_encoder.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1/prior_encoder.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source prior_encoder.tcl -notrace diff --git a/Exp3-2/Exp3-2.runs/impl_1/write_bitstream.pb b/Exp3-2/Exp3-2.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..3b2624b Binary files /dev/null and b/Exp3-2/Exp3-2.runs/impl_1/write_bitstream.pb differ diff --git a/Exp3-2/Exp3-2.runs/synth_1/.Xil/prior_encoder_propImpl.xdc b/Exp3-2/Exp3-2.runs/synth_1/.Xil/prior_encoder_propImpl.xdc new file mode 100644 index 0000000..cef3378 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/synth_1/.Xil/prior_encoder_propImpl.xdc @@ -0,0 +1,81 @@ +set_property SRC_FILE_INFO {cfile:F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/constrs_1/new/encoder.xdc rfile:../../../Exp3-2.srcs/constrs_1/new/encoder.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B4 [get_ports {seg1[6]}] +set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN A4 [get_ports {seg1[5]}] +set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN A3 [get_ports {seg1[4]}] +set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B1 [get_ports {seg1[3]}] +set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN A1 [get_ports {seg1[2]}] +set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B3 [get_ports {seg1[1]}] +set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B2 [get_ports {seg1[0]}] +set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D4 [get_ports {seg2[7]}] +set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E3 [get_ports {seg2[6]}] +set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D3 [get_ports {seg2[5]}] +set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F4 [get_ports {seg2[4]}] +set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F3 [get_ports {seg2[3]}] +set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E2 [get_ports {seg2[2]}] +set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D2 [get_ports {seg2[1]}] +set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN H2 [get_ports {seg2[0]}] +set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G2 [get_ports {seg_cs1[3]}] +set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN C2 [get_ports {seg_cs1[2]}] +set_property src_info {type:XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN C1 [get_ports {seg_cs1[1]}] +set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN H1 [get_ports {seg_cs1[0]}] +set_property src_info {type:XDC file:1 line:59 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G1 [get_ports {seg_cs2[3]}] +set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F1 [get_ports {seg_cs2[2]}] +set_property src_info {type:XDC file:1 line:61 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E1 [get_ports {seg_cs2[1]}] +set_property src_info {type:XDC file:1 line:62 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G6 [get_ports {seg_cs2[0]}] +set_property src_info {type:XDC file:1 line:63 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P5 [get_ports {i[7]}] +set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P4 [get_ports {i[6]}] +set_property src_info {type:XDC file:1 line:65 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P3 [get_ports {i[5]}] +set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R2 [get_ports {i[3]}] +set_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P2 [get_ports {i[4]}] +set_property src_info {type:XDC file:1 line:68 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN M4 [get_ports {i[2]}] +set_property src_info {type:XDC file:1 line:69 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN N4 [get_ports {i[1]}] +set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R1 [get_ports {i[0]}] +set_property src_info {type:XDC file:1 line:71 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F6 [get_ports {i_sig[7]}] +set_property src_info {type:XDC file:1 line:72 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G4 [get_ports {i_sig[6]}] +set_property src_info {type:XDC file:1 line:73 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G3 [get_ports {i_sig[5]}] +set_property src_info {type:XDC file:1 line:74 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J4 [get_ports {i_sig[4]}] +set_property src_info {type:XDC file:1 line:75 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN H4 [get_ports {i_sig[3]}] +set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J3 [get_ports {i_sig[2]}] +set_property src_info {type:XDC file:1 line:77 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J2 [get_ports {i_sig[1]}] +set_property src_info {type:XDC file:1 line:78 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN K2 [get_ports {i_sig[0]}] +set_property src_info {type:XDC file:1 line:80 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U3 [get_ports en] diff --git a/Exp3-2/Exp3-2.runs/synth_1/gen_run.xml b/Exp3-2/Exp3-2.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..7b8ebff --- /dev/null +++ b/Exp3-2/Exp3-2.runs/synth_1/gen_run.xml @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp3-2/Exp3-2.runs/synth_1/htr.txt b/Exp3-2/Exp3-2.runs/synth_1/htr.txt new file mode 100644 index 0000000..658d601 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log prior_encoder.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source prior_encoder.tcl diff --git a/Exp3-2/Exp3-2.runs/synth_1/prior_encoder.dcp b/Exp3-2/Exp3-2.runs/synth_1/prior_encoder.dcp new file mode 100644 index 0000000..e240ca0 Binary files /dev/null and b/Exp3-2/Exp3-2.runs/synth_1/prior_encoder.dcp differ diff --git a/Exp3-2/Exp3-2.runs/synth_1/prior_encoder.tcl b/Exp3-2/Exp3-2.runs/synth_1/prior_encoder.tcl new file mode 100644 index 0000000..c5e8638 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/synth_1/prior_encoder.tcl @@ -0,0 +1,56 @@ +# +# Synthesis run script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +create_project -in_memory -part xc7a35tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.cache/wt [current_project] +set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib { + F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/sources_1/new/SegDisplayCtrl.v + F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/sources_1/new/prior_encoder.v +} +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/constrs_1/new/encoder.xdc +set_property used_in_implementation false [get_files F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/constrs_1/new/encoder.xdc] + +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top prior_encoder -part xc7a35tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef prior_encoder.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file prior_encoder_utilization_synth.rpt -pb prior_encoder_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/Exp3-2/Exp3-2.runs/synth_1/prior_encoder.vds b/Exp3-2/Exp3-2.runs/synth_1/prior_encoder.vds new file mode 100644 index 0000000..04c0442 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/synth_1/prior_encoder.vds @@ -0,0 +1,315 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 31 10:38:29 2024 +# Process ID: 13224 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/synth_1 +# Command line: vivado.exe -log prior_encoder.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source prior_encoder.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/synth_1/prior_encoder.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source prior_encoder.tcl -notrace +Command: synth_design -top prior_encoder -part xc7a35tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 11852 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 408.988 ; gain = 97.160 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'prior_encoder' [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/sources_1/new/prior_encoder.v:23] +INFO: [Synth 8-6157] synthesizing module 'SegDisplayCtrl' [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/sources_1/new/SegDisplayCtrl.v:23] +INFO: [Synth 8-226] default block is never used [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/sources_1/new/SegDisplayCtrl.v:30] +INFO: [Synth 8-6155] done synthesizing module 'SegDisplayCtrl' (1#1) [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/sources_1/new/SegDisplayCtrl.v:23] +INFO: [Synth 8-6155] done synthesizing module 'prior_encoder' (2#1) [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/sources_1/new/prior_encoder.v:23] +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs1[3] driven by constant 0 +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs1[2] driven by constant 0 +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs1[1] driven by constant 0 +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs1[0] driven by constant 1 +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs2[3] driven by constant 0 +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs2[2] driven by constant 0 +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs2[1] driven by constant 0 +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs2[0] driven by constant 1 +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 464.723 ; gain = 152.895 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 464.723 ; gain = 152.895 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 464.723 ; gain = 152.895 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/constrs_1/new/encoder.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/constrs_1/new/encoder.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/constrs_1/new/encoder.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/prior_encoder_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/prior_encoder_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 787.852 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 787.852 ; gain = 476.023 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 787.852 ; gain = 476.023 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 787.852 ; gain = 476.023 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-327] inferring latch for variable 'i_sig_reg' [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/sources_1/new/prior_encoder.v:38] +WARNING: [Synth 8-327] inferring latch for variable 'Y_reg' [F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.srcs/sources_1/new/prior_encoder.v:39] +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 787.852 ; gain = 476.023 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Muxes : + 2 Input 8 Bit Muxes := 3 + 8 Input 7 Bit Muxes := 1 + 2 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 8 + 2 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 15 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module prior_encoder +Detailed RTL Component Info : ++---Muxes : + 2 Input 8 Bit Muxes := 2 + 2 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 8 + 2 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 15 +Module SegDisplayCtrl +Detailed RTL Component Info : ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 8 Input 7 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3917] design prior_encoder has port seg2[6] driven by constant 0 +WARNING: [Synth 8-3917] design prior_encoder has port seg2[5] driven by constant 0 +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs1[3] driven by constant 0 +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs1[2] driven by constant 0 +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs1[1] driven by constant 0 +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs1[0] driven by constant 1 +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs2[3] driven by constant 0 +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs2[2] driven by constant 0 +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs2[1] driven by constant 0 +WARNING: [Synth 8-3917] design prior_encoder has port seg_cs2[0] driven by constant 1 +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 787.852 ; gain = 476.023 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 787.852 ; gain = 476.023 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 787.852 ; gain = 476.023 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 787.852 ; gain = 476.023 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 787.852 ; gain = 476.023 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 787.852 ; gain = 476.023 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 787.852 ; gain = 476.023 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 787.852 ; gain = 476.023 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 787.852 ; gain = 476.023 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 787.852 ; gain = 476.023 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT1 | 1| +|2 |LUT2 | 3| +|3 |LUT3 | 8| +|4 |LUT4 | 4| +|5 |LUT5 | 5| +|6 |LUT6 | 6| +|7 |LD | 8| +|8 |LDC | 3| +|9 |IBUF | 9| +|10 |OBUF | 31| ++------+-----+------+ + +Report Instance Areas: ++------+---------+---------------+------+ +| |Instance |Module |Cells | ++------+---------+---------------+------+ +|1 |top | | 78| +|2 | unit |SegDisplayCtrl | 5| ++------+---------+---------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 787.852 ; gain = 476.023 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 12 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 787.852 ; gain = 152.895 +Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 787.852 ; gain = 476.023 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 20 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 11 instances were transformed. + LD => LDCE: 8 instances + LDC => LDCE: 3 instances + +INFO: [Common 17-83] Releasing license: Synthesis +17 Infos, 20 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 803.570 ; gain = 504.645 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/synth_1/prior_encoder.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file prior_encoder_utilization_synth.rpt -pb prior_encoder_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 803.570 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Thu Oct 31 10:38:59 2024... diff --git a/Exp3-2/Exp3-2.runs/synth_1/prior_encoder_utilization_synth.pb b/Exp3-2/Exp3-2.runs/synth_1/prior_encoder_utilization_synth.pb new file mode 100644 index 0000000..66462c7 Binary files /dev/null and b/Exp3-2/Exp3-2.runs/synth_1/prior_encoder_utilization_synth.pb differ diff --git a/Exp3-2/Exp3-2.runs/synth_1/prior_encoder_utilization_synth.rpt b/Exp3-2/Exp3-2.runs/synth_1/prior_encoder_utilization_synth.rpt new file mode 100644 index 0000000..948b537 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/synth_1/prior_encoder_utilization_synth.rpt @@ -0,0 +1,176 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Oct 31 10:38:59 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file prior_encoder_utilization_synth.rpt -pb prior_encoder_utilization_synth.pb +| Design : prior_encoder +| Device : 7a35tcsg324-1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 18 | 0 | 20800 | 0.09 | +| LUT as Logic | 18 | 0 | 20800 | 0.09 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 11 | 0 | 41600 | 0.03 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 11 | 0 | 41600 | 0.03 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 11 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 40 | 0 | 210 | 19.05 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 31 | IO | +| LDCE | 11 | Flop & Latch | +| IBUF | 9 | IO | +| LUT3 | 8 | LUT | +| LUT6 | 6 | LUT | +| LUT5 | 5 | LUT | +| LUT4 | 4 | LUT | +| LUT2 | 3 | LUT | +| LUT1 | 1 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp3-2/Exp3-2.runs/synth_1/vivado.jou b/Exp3-2/Exp3-2.runs/synth_1/vivado.jou new file mode 100644 index 0000000..f2ab752 --- /dev/null +++ b/Exp3-2/Exp3-2.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 31 10:38:29 2024 +# Process ID: 13224 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/synth_1 +# Command line: vivado.exe -log prior_encoder.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source prior_encoder.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/synth_1/prior_encoder.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source prior_encoder.tcl -notrace diff --git a/Exp3-2/Exp3-2.runs/synth_1/vivado.pb b/Exp3-2/Exp3-2.runs/synth_1/vivado.pb new file mode 100644 index 0000000..bddd97e Binary files /dev/null and b/Exp3-2/Exp3-2.runs/synth_1/vivado.pb differ diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/glbl.v b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/prior_encoder.tcl b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/prior_encoder.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/prior_encoder.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/prior_encoder_vlog.prj b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/prior_encoder_vlog.prj new file mode 100644 index 0000000..76faf7e --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/prior_encoder_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp3-2.srcs/sources_1/new/SegDisplayCtrl.v" \ +"../../../../Exp3-2.srcs/sim_1/new/tb_prior_encoder.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/tb_prior_encoder.tcl b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/tb_prior_encoder.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/tb_prior_encoder.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/tb_prior_encoder_vlog.prj b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/tb_prior_encoder_vlog.prj new file mode 100644 index 0000000..4b5616f --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/tb_prior_encoder_vlog.prj @@ -0,0 +1,11 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp3-2.srcs/sources_1/new/SegDisplayCtrl.v" \ +"../../../../Exp3-2.srcs/sources_1/new/prior_encoder.v" \ +"../../../../Exp3-2.srcs/sim_1/new/tb_prior_encoder.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk.jou b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..4f650c4 --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Nov 7 01:29:35 2024 +# Process ID: 7824 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk_10728.backup.jou b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk_10728.backup.jou new file mode 100644 index 0000000..d5b1e42 --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk_10728.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 31 10:38:09 2024 +# Process ID: 10728 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk_10852.backup.jou b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk_10852.backup.jou new file mode 100644 index 0000000..25ddc48 --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk_10852.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 31 10:33:53 2024 +# Process ID: 10852 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk_2128.backup.jou b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk_2128.backup.jou new file mode 100644 index 0000000..be38061 --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk_2128.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 31 10:48:04 2024 +# Process ID: 2128 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk_28300.backup.jou b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk_28300.backup.jou new file mode 100644 index 0000000..1185b7a --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk_28300.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 6 20:06:00 2024 +# Process ID: 28300 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk_5100.backup.jou b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk_5100.backup.jou new file mode 100644 index 0000000..fcb58a1 --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk_5100.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Oct 31 10:35:41 2024 +# Process ID: 5100 +# Current directory: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xelab.pb b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..219f526 Binary files /dev/null and b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/Compile_Options.txt b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/Compile_Options.txt new file mode 100644 index 0000000..95ccc4d --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "cda63ebb0cfb4de5b85ed29b7000f5fd" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "prior_encoder_behav" "xil_defaultlib.prior_encoder" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/TempBreakPointFile.txt b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/obj/xsim_1.c b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/obj/xsim_1.c new file mode 100644 index 0000000..a418870 --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/obj/xsim_1.c @@ -0,0 +1,110 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_2(char*, char *); +extern void execute_5(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_4(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_9(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[16] = {(funcp)execute_2, (funcp)execute_5, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_4, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 16; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/prior_encoder_behav/xsim.reloc", (void **)funcTab, 16); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/prior_encoder_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/prior_encoder_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/prior_encoder_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/prior_encoder_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/prior_encoder_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/webtalk/xsim_webtalk.tcl b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..291280d --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Thu Oct 31 10:39:37 2024" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.1 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2188600" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "78ec1a93-fd1a-4b14-8c4b-87f04256706b" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "cda63ebb0cfb4de5b85ed29b7000f5fd" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "3" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "13th Gen Intel(R) Core(TM) i7-13700H" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2918 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.00_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6520_KB" -context "xsim\\usage" +webtalk_transmit -clientid 271031535 -regid "" -xml F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/webtalk/usage_statistics_ext_xsim.xml -html F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/webtalk/usage_statistics_ext_xsim.html -wdm F:/Schoolwork/DigitalLogic/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/xsim.mem b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/xsim.mem new file mode 100644 index 0000000..385668b Binary files /dev/null and b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/prior_encoder_behav/xsim.mem differ diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/Compile_Options.txt b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/Compile_Options.txt new file mode 100644 index 0000000..d7fb1e7 --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "cda63ebb0cfb4de5b85ed29b7000f5fd" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_prior_encoder_behav" "xil_defaultlib.tb_prior_encoder" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/TempBreakPointFile.txt b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/obj/xsim_1.c b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/obj/xsim_1.c new file mode 100644 index 0000000..7d9aaa0 --- /dev/null +++ b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/obj/xsim_1.c @@ -0,0 +1,116 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_7(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_3(char*, char *); +extern void execute_6(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_5(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_25(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[22] = {(funcp)execute_7, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_3, (funcp)execute_6, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_5, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 22; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/tb_prior_encoder_behav/xsim.reloc", (void **)funcTab, 22); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/tb_prior_encoder_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_prior_encoder_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/tb_prior_encoder_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/tb_prior_encoder_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/tb_prior_encoder_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/xsim.mem b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/xsim.mem new file mode 100644 index 0000000..e57c165 Binary files /dev/null and b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xsim.dir/tb_prior_encoder_behav/xsim.mem differ diff --git a/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xvlog.pb b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..64f7703 Binary files /dev/null and b/Exp3-2/Exp3-2.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Exp3-2/Exp3-2.srcs/constrs_1/new/encoder.xdc b/Exp3-2/Exp3-2.srcs/constrs_1/new/encoder.xdc new file mode 100644 index 0000000..e9e6fa2 --- /dev/null +++ b/Exp3-2/Exp3-2.srcs/constrs_1/new/encoder.xdc @@ -0,0 +1,80 @@ +set_property IOSTANDARD LVCMOS33 [get_ports {i[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_sig[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg1[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg2[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs2[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs1[0]}] +set_property PACKAGE_PIN B4 [get_ports {seg1[6]}] +set_property PACKAGE_PIN A4 [get_ports {seg1[5]}] +set_property PACKAGE_PIN A3 [get_ports {seg1[4]}] +set_property PACKAGE_PIN B1 [get_ports {seg1[3]}] +set_property PACKAGE_PIN A1 [get_ports {seg1[2]}] +set_property PACKAGE_PIN B3 [get_ports {seg1[1]}] +set_property PACKAGE_PIN B2 [get_ports {seg1[0]}] +set_property PACKAGE_PIN D4 [get_ports {seg2[7]}] +set_property PACKAGE_PIN E3 [get_ports {seg2[6]}] +set_property PACKAGE_PIN D3 [get_ports {seg2[5]}] +set_property PACKAGE_PIN F4 [get_ports {seg2[4]}] +set_property PACKAGE_PIN F3 [get_ports {seg2[3]}] +set_property PACKAGE_PIN E2 [get_ports {seg2[2]}] +set_property PACKAGE_PIN D2 [get_ports {seg2[1]}] +set_property PACKAGE_PIN H2 [get_ports {seg2[0]}] +set_property PACKAGE_PIN G2 [get_ports {seg_cs1[3]}] +set_property PACKAGE_PIN C2 [get_ports {seg_cs1[2]}] +set_property PACKAGE_PIN C1 [get_ports {seg_cs1[1]}] +set_property PACKAGE_PIN H1 [get_ports {seg_cs1[0]}] +set_property PACKAGE_PIN G1 [get_ports {seg_cs2[3]}] +set_property PACKAGE_PIN F1 [get_ports {seg_cs2[2]}] +set_property PACKAGE_PIN E1 [get_ports {seg_cs2[1]}] +set_property PACKAGE_PIN G6 [get_ports {seg_cs2[0]}] +set_property PACKAGE_PIN P5 [get_ports {i[7]}] +set_property PACKAGE_PIN P4 [get_ports {i[6]}] +set_property PACKAGE_PIN P3 [get_ports {i[5]}] +set_property PACKAGE_PIN R2 [get_ports {i[3]}] +set_property PACKAGE_PIN P2 [get_ports {i[4]}] +set_property PACKAGE_PIN M4 [get_ports {i[2]}] +set_property PACKAGE_PIN N4 [get_ports {i[1]}] +set_property PACKAGE_PIN R1 [get_ports {i[0]}] +set_property PACKAGE_PIN F6 [get_ports {i_sig[7]}] +set_property PACKAGE_PIN G4 [get_ports {i_sig[6]}] +set_property PACKAGE_PIN G3 [get_ports {i_sig[5]}] +set_property PACKAGE_PIN J4 [get_ports {i_sig[4]}] +set_property PACKAGE_PIN H4 [get_ports {i_sig[3]}] +set_property PACKAGE_PIN J3 [get_ports {i_sig[2]}] +set_property PACKAGE_PIN J2 [get_ports {i_sig[1]}] +set_property PACKAGE_PIN K2 [get_ports {i_sig[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports en] +set_property PACKAGE_PIN U3 [get_ports en] diff --git a/Exp3-2/Exp3-2.srcs/sim_1/new/tb_prior_encoder.v b/Exp3-2/Exp3-2.srcs/sim_1/new/tb_prior_encoder.v new file mode 100644 index 0000000..3bffb13 --- /dev/null +++ b/Exp3-2/Exp3-2.srcs/sim_1/new/tb_prior_encoder.v @@ -0,0 +1,56 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/31 10:32:45 +// Design Name: +// Module Name: tb_prior_encoder +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_prior_encoder; +reg en; +reg [7:0] i; +wire [7:0] i_sig; +wire [6:0] seg1; +wire [7:0] seg2; +wire [3:0] seg_cs1; +wire [3:0] seg_cs2; +prior_encoder uut ( + .en(en), + .i(i), + .i_sig(i_sig), + .seg1(seg1), + .seg2(seg2), + .seg_cs1(seg_cs1), + .seg_cs2(seg_cs2) +); +initial begin + en = 0; + i = 8'b11111110; + #10; + en = 1; + i = 8'b11111110; #10; // Expected: Y = 3'b000, i_sig = 8'b00000001 + i = 8'b11111100; #10; // Expected: Y = 3'b001, i_sig = 8'b00000010 + i = 8'b11111000; #10; // Expected: Y = 3'b010, i_sig = 8'b00000100 + i = 8'b11110000; #10; // Expected: Y = 3'b011, i_sig = 8'b00001000 + i = 8'b11100000; #10; // Expected: Y = 3'b100, i_sig = 8'b00010000 + i = 8'b11000000; #10; // Expected: Y = 3'b101, i_sig = 8'b00100000 + i = 8'b10000000; #10; // Expected: Y = 3'b110, i_sig = 8'b01000000 + i = 8'b00000000; #10; // Expected: Y = 3'b111, i_sig = 8'b10000000 + en = 0; #10; // Expected: out = 0, i_sig = undefined + $finish; +end +endmodule diff --git a/Exp3-2/Exp3-2.srcs/sources_1/new/SegDisplayCtrl.v b/Exp3-2/Exp3-2.srcs/sources_1/new/SegDisplayCtrl.v new file mode 100644 index 0000000..dd25441 --- /dev/null +++ b/Exp3-2/Exp3-2.srcs/sources_1/new/SegDisplayCtrl.v @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/30 23:15:29 +// Design Name: +// Module Name: SegDisplayCtrl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module SegDisplayCtrl( + input wire [2:0] Y, + input wire out, + output reg [6:0] seg1, + output reg [7:0] seg2 +); +always @(*) begin + case (Y) + 3'b000: seg1 = 7'b1111110; // 0 + 3'b001: seg1 = 7'b0110000; // 1 + 3'b010: seg1 = 7'b1101101; // 2 + 3'b011: seg1 = 7'b1111001; // 3 + 3'b100: seg1 = 7'b0110011; // 4 + 3'b101: seg1 = 7'b1011011; // 5 + 3'b110: seg1 = 7'b1011111; // 6 + 3'b111: seg1 = 7'b1110000; // 7 + default: seg1 = 7'b0000000; + endcase + if (out) + seg2 = 8'b00000001; + else + seg2 = 8'b10011110; +end +endmodule diff --git a/Exp3-2/Exp3-2.srcs/sources_1/new/prior_encoder.v b/Exp3-2/Exp3-2.srcs/sources_1/new/prior_encoder.v new file mode 100644 index 0000000..5053432 --- /dev/null +++ b/Exp3-2/Exp3-2.srcs/sources_1/new/prior_encoder.v @@ -0,0 +1,63 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/30 23:12:14 +// Design Name: +// Module Name: prior_encoder +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module prior_encoder( + input en, + input [7:0] i, + output reg [7:0] i_sig, + output wire [6:0] seg1, + output wire [7:0] seg2, + output reg [3:0] seg_cs1, + output reg [3:0] seg_cs2 +); +reg out; +reg [2:0] Y; +always @(*) begin + out = 1; + if (en == 0) begin + out = 0; + i_sig = 8'b00000000; + Y = 3'b000; + end + else begin + if (i[7] == 0) begin Y = 3'b111; i_sig = 8'b10000000; end + else if (i[6] == 0) begin Y = 3'b110; i_sig = 8'b01000000; end + else if (i[5] == 0) begin Y = 3'b101; i_sig = 8'b00100000; end + else if (i[4] == 0) begin Y = 3'b100; i_sig = 8'b00010000; end + else if (i[3] == 0) begin Y = 3'b011; i_sig = 8'b00001000; end + else if (i[2] == 0) begin Y = 3'b010; i_sig = 8'b00000100; end + else if (i[1] == 0) begin Y = 3'b001; i_sig = 8'b00000010; end + else if (i[0] == 0) begin Y = 3'b000; i_sig = 8'b00000001; end + else out = 0; + end +end +SegDisplayCtrl unit ( + .Y(Y), + .out(out), + .seg1(seg1), + .seg2(seg2) +); +always @(*) begin + seg_cs1 = 4'b0001; + seg_cs2 = 4'b0001; +end +endmodule \ No newline at end of file diff --git a/Exp3-2/Exp3-2.xpr b/Exp3-2/Exp3-2.xpr new file mode 100644 index 0000000..1f86de3 --- /dev/null +++ b/Exp3-2/Exp3-2.xpr @@ -0,0 +1,157 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp4/Exp4.cache/wt/webtalk_pa.xml b/Exp4/Exp4.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..11b5b23 --- /dev/null +++ b/Exp4/Exp4.cache/wt/webtalk_pa.xml @@ -0,0 +1,97 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp4/Exp4.hw/hw_1/hw.xml b/Exp4/Exp4.hw/hw_1/hw.xml new file mode 100644 index 0000000..684cc76 --- /dev/null +++ b/Exp4/Exp4.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/Exp4/Exp4.ip_user_files/README.txt b/Exp4/Exp4.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp4/Exp4.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp4/Exp4.runs/.jobs/vrs_config_1.xml b/Exp4/Exp4.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..f42cb9e --- /dev/null +++ b/Exp4/Exp4.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp4/Exp4.runs/.jobs/vrs_config_2.xml b/Exp4/Exp4.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..f42cb9e --- /dev/null +++ b/Exp4/Exp4.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp4/Exp4.runs/.jobs/vrs_config_3.xml b/Exp4/Exp4.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..0ec69ce --- /dev/null +++ b/Exp4/Exp4.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp4/Exp4.runs/.jobs/vrs_config_4.xml b/Exp4/Exp4.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..28abf73 --- /dev/null +++ b/Exp4/Exp4.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp4/Exp4.runs/.jobs/vrs_config_5.xml b/Exp4/Exp4.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..f42cb9e --- /dev/null +++ b/Exp4/Exp4.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp4/Exp4.runs/.jobs/vrs_config_6.xml b/Exp4/Exp4.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..0f7a564 --- /dev/null +++ b/Exp4/Exp4.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp4/Exp4.runs/.jobs/vrs_config_7.xml b/Exp4/Exp4.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..28abf73 --- /dev/null +++ b/Exp4/Exp4.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp4/Exp4.runs/.jobs/vrs_config_8.xml b/Exp4/Exp4.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..159c3ee --- /dev/null +++ b/Exp4/Exp4.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp4/Exp4.runs/impl_1/calc.tcl b/Exp4/Exp4.runs/impl_1/calc.tcl new file mode 100644 index 0000000..d1a16fe --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/calc.tcl @@ -0,0 +1,170 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param xicom.use_bs_reader 1 + create_project -in_memory -part xc7a35tcsg324-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp4/Exp4.cache/wt [current_project] + set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp4/Exp4.xpr [current_project] + set_property ip_output_repo F:/Schoolwork/DigitalLogic/Exp4/Exp4.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1/calc.dcp + read_xdc F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc + link_design -top calc -part xc7a35tcsg324-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force calc_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file calc_drc_opted.rpt -pb calc_drc_opted.pb -rpx calc_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force calc_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file calc_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file calc_utilization_placed.rpt -pb calc_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file calc_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force calc_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file calc_drc_routed.rpt -pb calc_drc_routed.pb -rpx calc_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file calc_methodology_drc_routed.rpt -pb calc_methodology_drc_routed.pb -rpx calc_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file calc_power_routed.rpt -pb calc_power_summary_routed.pb -rpx calc_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file calc_route_status.rpt -pb calc_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file calc_timing_summary_routed.rpt -pb calc_timing_summary_routed.pb -rpx calc_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file calc_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file calc_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force calc_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force calc.mmi } + write_bitstream -force calc.bit + catch {write_debug_probes -quiet -force calc} + catch {file copy -force calc.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/Exp4/Exp4.runs/impl_1/calc.vdi b/Exp4/Exp4.runs/impl_1/calc.vdi new file mode 100644 index 0000000..5fcaebd --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/calc.vdi @@ -0,0 +1,450 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Nov 7 02:28:43 2024 +# Process ID: 25584 +# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1 +# Command line: vivado.exe -log calc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source calc.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source calc.tcl -notrace +Command: link_design -top calc -part xc7a35tcsg324-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 2 instances were transformed. + LDCP => LDCP (GND, LUT3, LUT3, LDCE, VCC): 2 instances + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 608.344 ; gain = 303.082 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.373 . Memory (MB): peak = 623.590 ; gain = 15.246 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 276aac3f7 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1170.543 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 276aac3f7 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1170.543 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 276aac3f7 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1170.543 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 276aac3f7 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1170.543 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 276aac3f7 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1170.543 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 276aac3f7 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1170.543 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1170.543 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 276aac3f7 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1170.543 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 276aac3f7 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1170.543 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1170.543 ; gain = 562.199 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1170.543 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file calc_drc_opted.rpt -pb calc_drc_opted.pb -rpx calc_drc_opted.rpx +Command: report_drc -file calc_drc_opted.rpt -pb calc_drc_opted.pb -rpx calc_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1170.543 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e2929c37 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1170.543 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1170.543 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 137b1e3de + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.322 . Memory (MB): peak = 1183.531 ; gain = 12.988 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1dab45a3d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.330 . Memory (MB): peak = 1183.531 ; gain = 12.988 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1dab45a3d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.330 . Memory (MB): peak = 1183.531 ; gain = 12.988 +Phase 1 Placer Initialization | Checksum: 1dab45a3d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.331 . Memory (MB): peak = 1183.531 ; gain = 12.988 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 1e6d939ab + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.463 . Memory (MB): peak = 1183.531 ; gain = 12.988 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1e6d939ab + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.464 . Memory (MB): peak = 1183.531 ; gain = 12.988 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 219db61c9 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.470 . Memory (MB): peak = 1183.531 ; gain = 12.988 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 151450402 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.474 . Memory (MB): peak = 1183.531 ; gain = 12.988 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 151450402 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.474 . Memory (MB): peak = 1183.531 ; gain = 12.988 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 14e2b920e + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.516 . Memory (MB): peak = 1183.531 ; gain = 12.988 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 14e2b920e + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.519 . Memory (MB): peak = 1183.531 ; gain = 12.988 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 14e2b920e + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.519 . Memory (MB): peak = 1183.531 ; gain = 12.988 +Phase 3 Detail Placement | Checksum: 14e2b920e + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.519 . Memory (MB): peak = 1183.531 ; gain = 12.988 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 14e2b920e + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.521 . Memory (MB): peak = 1183.531 ; gain = 12.988 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 14e2b920e + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.522 . Memory (MB): peak = 1183.531 ; gain = 12.988 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 14e2b920e + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.523 . Memory (MB): peak = 1183.531 ; gain = 12.988 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 14e2b920e + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.523 . Memory (MB): peak = 1183.531 ; gain = 12.988 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 14e2b920e + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.523 . Memory (MB): peak = 1183.531 ; gain = 12.988 +Ending Placer Task | Checksum: 1015e41ce + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.525 . Memory (MB): peak = 1183.531 ; gain = 12.988 +INFO: [Common 17-83] Releasing license: Implementation +41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1183.531 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file calc_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1188.391 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file calc_utilization_placed.rpt -pb calc_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1188.391 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file calc_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1188.391 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 37ead21 ConstDB: 0 ShapeSum: fddf94ad RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: bf67df9b + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1302.117 ; gain = 113.727 +Post Restoration Checksum: NetGraph: 4572a9c8 NumContArr: 79f535d3 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: bf67df9b + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1308.117 ; gain = 119.727 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: bf67df9b + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1308.117 ; gain = 119.727 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 11937b63c + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 1a7a41aad + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 6 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: b875e9c3 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508 +Phase 4 Rip-up And Reroute | Checksum: b875e9c3 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: b875e9c3 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: b875e9c3 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508 +Phase 6 Post Hold Fix | Checksum: b875e9c3 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0557283 % + Global Horizontal Routing Utilization = 0.0265487 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 26.1261%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: b875e9c3 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: b875e9c3 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.164 ; gain = 123.773 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 144801a5b + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.164 ; gain = 123.773 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.164 ; gain = 123.773 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.164 ; gain = 123.773 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1312.164 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file calc_drc_routed.rpt -pb calc_drc_routed.pb -rpx calc_drc_routed.rpx +Command: report_drc -file calc_drc_routed.rpt -pb calc_drc_routed.pb -rpx calc_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file calc_methodology_drc_routed.rpt -pb calc_methodology_drc_routed.pb -rpx calc_methodology_drc_routed.rpx +Command: report_methodology -file calc_methodology_drc_routed.rpt -pb calc_methodology_drc_routed.pb -rpx calc_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file calc_power_routed.rpt -pb calc_power_summary_routed.pb -rpx calc_power_routed.rpx +Command: report_power -file calc_power_routed.rpt -pb calc_power_summary_routed.pb -rpx calc_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file calc_route_status.rpt -pb calc_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file calc_timing_summary_routed.rpt -pb calc_timing_summary_routed.pb -rpx calc_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file calc_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file calc_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force calc.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +WARNING: [DRC PDRC-153] Gated clock check: Net run/result_reg[2]/G0 is a gated clock net sourced by a combinational pin run/result_reg[2]/L3_2/O, cell run/result_reg[2]/L3_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net run/result_reg[3]/G0 is a gated clock net sourced by a combinational pin run/result_reg[3]/L3_2/O, cell run/result_reg[3]/L3_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +WARNING: [DRC PDRC-153] Gated clock check: Net run/result_reg[3]_i_1_n_0 is a gated clock net sourced by a combinational pin run/result_reg[3]_i_1/O, cell run/result_reg[3]_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 4 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./calc.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +84 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1766.340 ; gain = 420.117 +INFO: [Common 17-206] Exiting Vivado at Thu Nov 7 02:29:25 2024... diff --git a/Exp4/Exp4.runs/impl_1/calc_20992.backup.vdi b/Exp4/Exp4.runs/impl_1/calc_20992.backup.vdi new file mode 100644 index 0000000..d75d26b --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/calc_20992.backup.vdi @@ -0,0 +1,424 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Nov 7 02:25:03 2024 +# Process ID: 20992 +# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1 +# Command line: vivado.exe -log calc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source calc.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source calc.tcl -notrace +Command: open_checkpoint F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 241.820 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1100.367 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1100.367 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 2 instances were transformed. + LDCP => LDCP (GND, LUT3, LUT3, LDCE, VCC): 2 instances + +INFO: [Project 1-604] Checkpoint was created with Vivado v2018.1 (64-bit) build 2188600 +open_checkpoint: Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1100.367 ; gain = 867.789 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.315 . Memory (MB): peak = 1100.367 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 22bbafb85 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1182.973 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 22bbafb85 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1182.973 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 22bbafb85 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1182.973 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 22bbafb85 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1182.973 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 22bbafb85 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1182.973 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 22bbafb85 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1182.973 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1182.973 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 22bbafb85 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1182.973 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 22bbafb85 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1182.973 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +27 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1182.973 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file calc_drc_opted.rpt -pb calc_drc_opted.pb -rpx calc_drc_opted.rpx +Command: report_drc -file calc_drc_opted.rpt -pb calc_drc_opted.pb -rpx calc_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1182.973 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e2929c37 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1182.973 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1182.973 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 137b1e3de + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.353 . Memory (MB): peak = 1184.621 ; gain = 1.648 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1a38e33f2 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.372 . Memory (MB): peak = 1184.621 ; gain = 1.648 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1a38e33f2 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.374 . Memory (MB): peak = 1184.621 ; gain = 1.648 +Phase 1 Placer Initialization | Checksum: 1a38e33f2 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.376 . Memory (MB): peak = 1184.621 ; gain = 1.648 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 165725f0a + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.517 . Memory (MB): peak = 1184.621 ; gain = 1.648 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 165725f0a + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.519 . Memory (MB): peak = 1184.621 ; gain = 1.648 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c30658d9 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.527 . Memory (MB): peak = 1184.621 ; gain = 1.648 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 151c71063 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.530 . Memory (MB): peak = 1184.621 ; gain = 1.648 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 151c71063 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.531 . Memory (MB): peak = 1184.621 ; gain = 1.648 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1f97b56aa + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.574 . Memory (MB): peak = 1184.621 ; gain = 1.648 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1f97b56aa + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.577 . Memory (MB): peak = 1184.621 ; gain = 1.648 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1f97b56aa + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.577 . Memory (MB): peak = 1184.621 ; gain = 1.648 +Phase 3 Detail Placement | Checksum: 1f97b56aa + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.578 . Memory (MB): peak = 1184.621 ; gain = 1.648 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1f97b56aa + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.579 . Memory (MB): peak = 1184.621 ; gain = 1.648 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1f97b56aa + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.583 . Memory (MB): peak = 1184.621 ; gain = 1.648 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1f97b56aa + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.583 . Memory (MB): peak = 1184.621 ; gain = 1.648 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1f97b56aa + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.584 . Memory (MB): peak = 1184.621 ; gain = 1.648 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f97b56aa + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.584 . Memory (MB): peak = 1184.621 ; gain = 1.648 +Ending Placer Task | Checksum: 14b4f553e + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.586 . Memory (MB): peak = 1184.621 ; gain = 1.648 +INFO: [Common 17-83] Releasing license: Implementation +45 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1184.621 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file calc_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1189.809 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file calc_utilization_placed.rpt -pb calc_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1189.809 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file calc_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1189.809 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 4d6fc091 ConstDB: 0 ShapeSum: fddf94ad RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 98e94c16 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 1302.215 ; gain = 112.406 +Post Restoration Checksum: NetGraph: 3ae684d6 NumContArr: 5e02c740 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 98e94c16 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1308.246 ; gain = 118.438 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 98e94c16 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1308.246 ; gain = 118.438 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 123501692 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 10ee29832 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: fb0c9e35 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270 +Phase 4 Rip-up And Reroute | Checksum: fb0c9e35 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: fb0c9e35 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: fb0c9e35 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270 +Phase 6 Post Hold Fix | Checksum: fb0c9e35 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0416168 % + Global Horizontal Routing Utilization = 0.0260281 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: fb0c9e35 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.078 ; gain = 122.270 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: fb0c9e35 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1313.828 ; gain = 124.020 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 1664a9788 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1313.828 ; gain = 124.020 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1313.828 ; gain = 124.020 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +58 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1313.828 ; gain = 124.020 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1313.828 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file calc_drc_routed.rpt -pb calc_drc_routed.pb -rpx calc_drc_routed.rpx +Command: report_drc -file calc_drc_routed.rpt -pb calc_drc_routed.pb -rpx calc_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file calc_methodology_drc_routed.rpt -pb calc_methodology_drc_routed.pb -rpx calc_methodology_drc_routed.rpx +Command: report_methodology -file calc_methodology_drc_routed.rpt -pb calc_methodology_drc_routed.pb -rpx calc_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file calc_power_routed.rpt -pb calc_power_summary_routed.pb -rpx calc_power_routed.rpx +Command: report_power -file calc_power_routed.rpt -pb calc_power_summary_routed.pb -rpx calc_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +70 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file calc_route_status.rpt -pb calc_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file calc_timing_summary_routed.rpt -pb calc_timing_summary_routed.pb -rpx calc_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file calc_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file calc_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Thu Nov 7 02:25:37 2024... diff --git a/Exp4/Exp4.runs/impl_1/calc_clock_utilization_routed.rpt b/Exp4/Exp4.runs/impl_1/calc_clock_utilization_routed.rpt new file mode 100644 index 0000000..2582fba --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/calc_clock_utilization_routed.rpt @@ -0,0 +1,145 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Nov 7 02:29:18 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file calc_clock_utilization_routed.rpt +| Design : calc +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +------------------------------------------------------------------------------------ + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X1Y0 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 5 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | IOB_X0Y26 | IOB_X0Y26 | X0Y0 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 5 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 1 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | | | | 5 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 5 | ++----+----+----+ + + +7. Clock Region Cell Placement per Global Clock: Region X1Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y26 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0} +#endgroup diff --git a/Exp4/Exp4.runs/impl_1/calc_control_sets_placed.rpt b/Exp4/Exp4.runs/impl_1/calc_control_sets_placed.rpt new file mode 100644 index 0000000..6e5c167 --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/calc_control_sets_placed.rpt @@ -0,0 +1,69 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Nov 7 02:29:04 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file calc_control_sets_placed.rpt +| Design : calc +| Device : xc7a35t +------------------------------------------------------------------------------------ + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 4 | +| Unused register locations in slices containing registers | 24 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ +| 1 | 3 | +| 5 | 1 | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 2 | 2 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 1 | 1 | +| Yes | No | No | 5 | 2 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++----------------------------+------------------------+---------------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++----------------------------+------------------------+---------------------------+------------------+----------------+ +| run/result_reg[2]/G0 | | | 1 | 1 | +| run/result_reg[3]_i_1_n_0 | | run/result_reg[1]_i_1_n_0 | 1 | 1 | +| run/result_reg[3]/G0 | | | 1 | 1 | +| clk_IBUF_BUFG | stored_type[4]_i_1_n_0 | | 2 | 5 | ++----------------------------+------------------------+---------------------------+------------------+----------------+ + + diff --git a/Exp4/Exp4.runs/impl_1/calc_drc_opted.pb b/Exp4/Exp4.runs/impl_1/calc_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp4/Exp4.runs/impl_1/calc_drc_opted.pb differ diff --git a/Exp4/Exp4.runs/impl_1/calc_drc_opted.rpt b/Exp4/Exp4.runs/impl_1/calc_drc_opted.rpt new file mode 100644 index 0000000..ee1b81e --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/calc_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Nov 7 02:29:03 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file calc_drc_opted.rpt -pb calc_drc_opted.pb -rpx calc_drc_opted.rpx +| Design : calc +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp4/Exp4.runs/impl_1/calc_drc_routed.pb b/Exp4/Exp4.runs/impl_1/calc_drc_routed.pb new file mode 100644 index 0000000..4458cdc Binary files /dev/null and b/Exp4/Exp4.runs/impl_1/calc_drc_routed.pb differ diff --git a/Exp4/Exp4.runs/impl_1/calc_drc_routed.rpt b/Exp4/Exp4.runs/impl_1/calc_drc_routed.rpt new file mode 100644 index 0000000..79c38b5 --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/calc_drc_routed.rpt @@ -0,0 +1,65 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Nov 7 02:29:17 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file calc_drc_routed.rpt -pb calc_drc_routed.pb -rpx calc_drc_routed.rpx +| Design : calc +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 4 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| PDRC-153 | Warning | Gated clock check | 3 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +PDRC-153#1 Warning +Gated clock check +Net run/result_reg[2]/G0 is a gated clock net sourced by a combinational pin run/result_reg[2]/L3_2/O, cell run/result_reg[2]/L3_2 (in run/result_reg[2] macro). This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#2 Warning +Gated clock check +Net run/result_reg[3]/G0 is a gated clock net sourced by a combinational pin run/result_reg[3]/L3_2/O, cell run/result_reg[3]/L3_2 (in run/result_reg[3] macro). This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + +PDRC-153#3 Warning +Gated clock check +Net run/result_reg[3]_i_1_n_0 is a gated clock net sourced by a combinational pin run/result_reg[3]_i_1/O, cell run/result_reg[3]_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. +Related violations: + + diff --git a/Exp4/Exp4.runs/impl_1/calc_io_placed.rpt b/Exp4/Exp4.runs/impl_1/calc_io_placed.rpt new file mode 100644 index 0000000..7fb7779 --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/calc_io_placed.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Nov 7 02:29:04 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_io -file calc_io_placed.rpt +| Design : calc +| Device : xc7a35t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2013-12-19 +| Package Pin Delay Version : VERS. 2.0 2013-12-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 30 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | seg[0] | High Range | IO_L14N_T2_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D3 | seg[4] | High Range | IO_L12N_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D4 | seg[6] | High Range | IO_L11N_T1_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | seg_cs[1] | High Range | IO_L18N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E2 | seg[1] | High Range | IO_L14P_T2_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E3 | seg[5] | High Range | IO_L12P_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | seg_cs[2] | High Range | IO_L18P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | seg[2] | High Range | IO_L13N_T2_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F4 | seg[3] | High Range | IO_L13P_T2_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | result[4] | High Range | IO_L19N_T3_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | seg_cs[3] | High Range | IO_L17N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | result[2] | High Range | IO_L20N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G4 | result[3] | High Range | IO_L20P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | seg_cs[0] | High Range | IO_L19P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | result[0] | High Range | IO_L21N_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J4 | result[1] | High Range | IO_L21P_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | data2[2] | High Range | IO_L16P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N4 | data2[1] | High Range | IO_L16N_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | data1[0] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P3 | data1[1] | High Range | IO_L14N_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P4 | data1[2] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P5 | data1[3] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P17 | clk | High Range | IO_L12P_T1_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | data2[0] | High Range | IO_L17P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| R2 | data2[3] | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | type[1] | High Range | IO_0_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | type[2] | High Range | IO_L13N_T2_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | type[0] | High Range | IO_L12N_T1_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | type[4] | High Range | IO_L8P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | type[3] | High Range | IO_L7N_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Exp4/Exp4.runs/impl_1/calc_methodology_drc_routed.pb b/Exp4/Exp4.runs/impl_1/calc_methodology_drc_routed.pb new file mode 100644 index 0000000..c491e05 Binary files /dev/null and b/Exp4/Exp4.runs/impl_1/calc_methodology_drc_routed.pb differ diff --git a/Exp4/Exp4.runs/impl_1/calc_methodology_drc_routed.rpt b/Exp4/Exp4.runs/impl_1/calc_methodology_drc_routed.rpt new file mode 100644 index 0000000..f9bffde --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/calc_methodology_drc_routed.rpt @@ -0,0 +1,82 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Nov 7 02:29:17 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_methodology -file calc_methodology_drc_routed.rpt -pb calc_methodology_drc_routed.pb -rpx calc_methodology_drc_routed.rpx +| Design : calc +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +-------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 9 ++-----------+----------+------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+------------------------------+------------+ +| LUTAR-1 | Warning | LUT drives async reset alert | 1 | +| TIMING-17 | Warning | Non-clocked sequential cell | 5 | +| TIMING-20 | Warning | Non-clocked latch | 3 | ++-----------+----------+------------------------------+------------+ + +2. REPORT DETAILS +----------------- +LUTAR-1#1 Warning +LUT drives async reset alert +LUT cell run/result_reg[1]_i_1, with 2 or more inputs, drives asynchronous reset pin(s) run/result_reg[1]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +TIMING-17#1 Warning +Non-clocked sequential cell +The clock pin stored_type_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Warning +Non-clocked sequential cell +The clock pin stored_type_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Warning +Non-clocked sequential cell +The clock pin stored_type_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Warning +Non-clocked sequential cell +The clock pin stored_type_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#5 Warning +Non-clocked sequential cell +The clock pin stored_type_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-20#1 Warning +Non-clocked latch +The latch run/result_reg[1] cannot be properly analyzed as its control pin run/result_reg[1]/G is not reached by a timing clock +Related violations: + +TIMING-20#2 Warning +Non-clocked latch +The latch run/result_reg[2]/L7 (in run/result_reg[2] macro) cannot be properly analyzed as its control pin run/result_reg[2]/L7/G is not reached by a timing clock +Related violations: + +TIMING-20#3 Warning +Non-clocked latch +The latch run/result_reg[3]/L7 (in run/result_reg[3] macro) cannot be properly analyzed as its control pin run/result_reg[3]/L7/G is not reached by a timing clock +Related violations: + + diff --git a/Exp4/Exp4.runs/impl_1/calc_opt.dcp b/Exp4/Exp4.runs/impl_1/calc_opt.dcp new file mode 100644 index 0000000..193ff57 Binary files /dev/null and b/Exp4/Exp4.runs/impl_1/calc_opt.dcp differ diff --git a/Exp4/Exp4.runs/impl_1/calc_placed.dcp b/Exp4/Exp4.runs/impl_1/calc_placed.dcp new file mode 100644 index 0000000..a0a5749 Binary files /dev/null and b/Exp4/Exp4.runs/impl_1/calc_placed.dcp differ diff --git a/Exp4/Exp4.runs/impl_1/calc_power_routed.rpt b/Exp4/Exp4.runs/impl_1/calc_power_routed.rpt new file mode 100644 index 0000000..b05e4ba --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/calc_power_routed.rpt @@ -0,0 +1,146 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Nov 7 02:29:17 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_power -file calc_power_routed.rpt -pb calc_power_summary_routed.pb -rpx calc_power_routed.rpx +| Design : calc +| Device : xc7a35tcsg324-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 7.595 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 7.488 | +| Device Static (W) | 0.107 | +| Effective TJA (C/W) | 4.8 | +| Max Ambient (C) | 48.7 | +| Junction Temperature (C) | 61.3 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.133 | 54 | --- | --- | +| LUT as Logic | 0.126 | 32 | 20800 | 0.15 | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| Register | 0.001 | 8 | 41600 | 0.02 | +| Others | 0.000 | 8 | --- | --- | +| Signals | 0.248 | 58 | --- | --- | +| I/O | 7.107 | 30 | 210 | 14.29 | +| Static Power | 0.107 | | | | +| Total | 7.595 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.475 | 0.437 | 0.039 | +| Vccaux | 1.800 | 0.274 | 0.258 | 0.016 | +| Vcco33 | 3.300 | 1.997 | 1.996 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.8 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++-------------------+-----------+ +| Name | Power (W) | ++-------------------+-----------+ +| calc | 7.488 | +| run | 0.116 | +| result_reg[2] | 0.012 | +| result_reg[3] | 0.012 | ++-------------------+-----------+ + + diff --git a/Exp4/Exp4.runs/impl_1/calc_power_summary_routed.pb b/Exp4/Exp4.runs/impl_1/calc_power_summary_routed.pb new file mode 100644 index 0000000..baff6b2 Binary files /dev/null and b/Exp4/Exp4.runs/impl_1/calc_power_summary_routed.pb differ diff --git a/Exp4/Exp4.runs/impl_1/calc_route_status.pb b/Exp4/Exp4.runs/impl_1/calc_route_status.pb new file mode 100644 index 0000000..7d37df1 Binary files /dev/null and b/Exp4/Exp4.runs/impl_1/calc_route_status.pb differ diff --git a/Exp4/Exp4.runs/impl_1/calc_route_status.rpt b/Exp4/Exp4.runs/impl_1/calc_route_status.rpt new file mode 100644 index 0000000..032fd5f --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/calc_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 92 : + # of nets not needing routing.......... : 32 : + # of internally routed nets........ : 32 : + # of routable nets..................... : 60 : + # of fully routed nets............. : 60 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Exp4/Exp4.runs/impl_1/calc_routed.dcp b/Exp4/Exp4.runs/impl_1/calc_routed.dcp new file mode 100644 index 0000000..8a96157 Binary files /dev/null and b/Exp4/Exp4.runs/impl_1/calc_routed.dcp differ diff --git a/Exp4/Exp4.runs/impl_1/calc_timing_summary_routed.pb b/Exp4/Exp4.runs/impl_1/calc_timing_summary_routed.pb new file mode 100644 index 0000000..4526e93 --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/calc_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/Exp4/Exp4.runs/impl_1/calc_timing_summary_routed.rpt b/Exp4/Exp4.runs/impl_1/calc_timing_summary_routed.rpt new file mode 100644 index 0000000..c8fa525 --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/calc_timing_summary_routed.rpt @@ -0,0 +1,189 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Nov 7 02:29:17 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file calc_timing_summary_routed.rpt -pb calc_timing_summary_routed.pb -rpx calc_timing_summary_routed.rpx -warn_on_violation +| Design : calc +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 5 register/latch pins with no clock driven by root clock pin: clk (HIGH) + + There are 3 register/latch pins with no clock driven by root clock pin: data1[0] (HIGH) + + There are 3 register/latch pins with no clock driven by root clock pin: data1[1] (HIGH) + + There are 3 register/latch pins with no clock driven by root clock pin: data1[2] (HIGH) + + There are 3 register/latch pins with no clock driven by root clock pin: data1[3] (HIGH) + + There are 3 register/latch pins with no clock driven by root clock pin: data2[0] (HIGH) + + There are 3 register/latch pins with no clock driven by root clock pin: data2[1] (HIGH) + + There are 3 register/latch pins with no clock driven by root clock pin: data2[2] (HIGH) + + There are 3 register/latch pins with no clock driven by root clock pin: data2[3] (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 13 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 13 input ports with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 13 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/Exp4/Exp4.runs/impl_1/calc_utilization_placed.pb b/Exp4/Exp4.runs/impl_1/calc_utilization_placed.pb new file mode 100644 index 0000000..0884b94 Binary files /dev/null and b/Exp4/Exp4.runs/impl_1/calc_utilization_placed.pb differ diff --git a/Exp4/Exp4.runs/impl_1/calc_utilization_placed.rpt b/Exp4/Exp4.runs/impl_1/calc_utilization_placed.rpt new file mode 100644 index 0000000..e640df7 --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/calc_utilization_placed.rpt @@ -0,0 +1,204 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Nov 7 02:29:04 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file calc_utilization_placed.rpt -pb calc_utilization_placed.pb +| Design : calc +| Device : 7a35tcsg324-1 +| Design State : Fully Placed +----------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 32 | 0 | 20800 | 0.15 | +| LUT as Logic | 32 | 0 | 20800 | 0.15 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 8 | 0 | 41600 | 0.02 | +| Register as Flip Flop | 5 | 0 | 41600 | 0.01 | +| Register as Latch | 3 | 0 | 41600 | <0.01 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 2 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 1 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 5 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 12 | 0 | 8150 | 0.15 | +| SLICEL | 8 | 0 | | | +| SLICEM | 4 | 0 | | | +| LUT as Logic | 32 | 0 | 20800 | 0.15 | +| using O5 output only | 0 | | | | +| using O6 output only | 27 | | | | +| using O5 and O6 | 5 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 2 | 0 | 20800 | <0.01 | +| fully used LUT-FF pairs | 0 | | | | +| LUT-FF pairs with one unused LUT output | 1 | | | | +| LUT-FF pairs with one unused Flip Flop | 2 | | | | +| Unique Control Sets | 4 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 30 | 30 | 210 | 14.29 | +| IOB Master Pads | 13 | | | | +| IOB Slave Pads | 16 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 16 | IO | +| IBUF | 14 | IO | +| LUT6 | 12 | LUT | +| LUT5 | 11 | LUT | +| LUT3 | 8 | LUT | +| FDRE | 5 | Flop & Latch | +| LUT2 | 4 | LUT | +| LDCE | 3 | Flop & Latch | +| LUT4 | 2 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp4/Exp4.runs/impl_1/gen_run.xml b/Exp4/Exp4.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..bf925e7 --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/gen_run.xml @@ -0,0 +1,104 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp4/Exp4.runs/impl_1/htr.txt b/Exp4/Exp4.runs/impl_1/htr.txt new file mode 100644 index 0000000..6cceab8 --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log calc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source calc.tcl -notrace diff --git a/Exp4/Exp4.runs/impl_1/init_design.pb b/Exp4/Exp4.runs/impl_1/init_design.pb new file mode 100644 index 0000000..562b473 Binary files /dev/null and b/Exp4/Exp4.runs/impl_1/init_design.pb differ diff --git a/Exp4/Exp4.runs/impl_1/opt_design.pb b/Exp4/Exp4.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..0dfea64 Binary files /dev/null and b/Exp4/Exp4.runs/impl_1/opt_design.pb differ diff --git a/Exp4/Exp4.runs/impl_1/place_design.pb b/Exp4/Exp4.runs/impl_1/place_design.pb new file mode 100644 index 0000000..d2af5bd Binary files /dev/null and b/Exp4/Exp4.runs/impl_1/place_design.pb differ diff --git a/Exp4/Exp4.runs/impl_1/route_design.pb b/Exp4/Exp4.runs/impl_1/route_design.pb new file mode 100644 index 0000000..75c5d90 Binary files /dev/null and b/Exp4/Exp4.runs/impl_1/route_design.pb differ diff --git a/Exp4/Exp4.runs/impl_1/route_report_bus_skew_0.rpt b/Exp4/Exp4.runs/impl_1/route_report_bus_skew_0.rpt new file mode 100644 index 0000000..f4b16c0 --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/route_report_bus_skew_0.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Nov 7 02:29:18 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +| Design : calc +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/Exp4/Exp4.runs/impl_1/usage_statistics_webtalk.xml b/Exp4/Exp4.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..645a74c --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,609 @@ + + +
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+ diff --git a/Exp4/Exp4.runs/impl_1/vivado.jou b/Exp4/Exp4.runs/impl_1/vivado.jou new file mode 100644 index 0000000..cfcedf2 --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Nov 7 02:28:43 2024 +# Process ID: 25584 +# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1 +# Command line: vivado.exe -log calc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source calc.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source calc.tcl -notrace diff --git a/Exp4/Exp4.runs/impl_1/vivado.pb b/Exp4/Exp4.runs/impl_1/vivado.pb new file mode 100644 index 0000000..283fada Binary files /dev/null and b/Exp4/Exp4.runs/impl_1/vivado.pb differ diff --git a/Exp4/Exp4.runs/impl_1/vivado_20992.backup.jou b/Exp4/Exp4.runs/impl_1/vivado_20992.backup.jou new file mode 100644 index 0000000..74e51ef --- /dev/null +++ b/Exp4/Exp4.runs/impl_1/vivado_20992.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Nov 7 02:25:03 2024 +# Process ID: 20992 +# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1 +# Command line: vivado.exe -log calc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source calc.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source calc.tcl -notrace diff --git a/Exp4/Exp4.runs/impl_1/write_bitstream.pb b/Exp4/Exp4.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..dd869c7 Binary files /dev/null and b/Exp4/Exp4.runs/impl_1/write_bitstream.pb differ diff --git a/Exp4/Exp4.runs/synth_1/.Xil/calc_propImpl.xdc b/Exp4/Exp4.runs/synth_1/.Xil/calc_propImpl.xdc new file mode 100644 index 0000000..887c4d4 --- /dev/null +++ b/Exp4/Exp4.runs/synth_1/.Xil/calc_propImpl.xdc @@ -0,0 +1,61 @@ +set_property SRC_FILE_INFO {cfile:F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc rfile:../../../Exp4.srcs/constrs_1/new/calc.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P5 [get_ports {data1[3]}] +set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P4 [get_ports {data1[2]}] +set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P3 [get_ports {data1[1]}] +set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P2 [get_ports {data1[0]}] +set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R2 [get_ports {data2[3]}] +set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN M4 [get_ports {data2[2]}] +set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN N4 [get_ports {data2[1]}] +set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R1 [get_ports {data2[0]}] +set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F6 [get_ports {result[4]}] +set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G4 [get_ports {result[3]}] +set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G3 [get_ports {result[2]}] +set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J4 [get_ports {result[1]}] +set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN H4 [get_ports {result[0]}] +set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D4 [get_ports {seg[6]}] +set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E3 [get_ports {seg[5]}] +set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D3 [get_ports {seg[4]}] +set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F4 [get_ports {seg[3]}] +set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F3 [get_ports {seg[2]}] +set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E2 [get_ports {seg[1]}] +set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D2 [get_ports {seg[0]}] +set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G1 [get_ports {seg_cs[3]}] +set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F1 [get_ports {seg_cs[2]}] +set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E1 [get_ports {seg_cs[1]}] +set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G6 [get_ports {seg_cs[0]}] +set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN U4 [get_ports {type[4]}] +set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V1 [get_ports {type[3]}] +set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R15 [get_ports {type[2]}] +set_property src_info {type:XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R11 [get_ports {type[1]}] +set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R17 [get_ports {type[0]}] +set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P17 [get_ports clk] diff --git a/Exp4/Exp4.runs/synth_1/calc.dcp b/Exp4/Exp4.runs/synth_1/calc.dcp new file mode 100644 index 0000000..c83ebeb Binary files /dev/null and b/Exp4/Exp4.runs/synth_1/calc.dcp differ diff --git a/Exp4/Exp4.runs/synth_1/calc.tcl b/Exp4/Exp4.runs/synth_1/calc.tcl new file mode 100644 index 0000000..e55ef1f --- /dev/null +++ b/Exp4/Exp4.runs/synth_1/calc.tcl @@ -0,0 +1,58 @@ +# +# Synthesis run script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param xicom.use_bs_reader 1 +create_project -in_memory -part xc7a35tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp4/Exp4.cache/wt [current_project] +set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp4/Exp4.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp4/Exp4.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib { + F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v + F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/judge.v + F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/calc.v +} +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc +set_property used_in_implementation false [get_files F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc] + +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top calc -part xc7a35tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef calc.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file calc_utilization_synth.rpt -pb calc_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/Exp4/Exp4.runs/synth_1/calc.vds b/Exp4/Exp4.runs/synth_1/calc.vds new file mode 100644 index 0000000..91bceea --- /dev/null +++ b/Exp4/Exp4.runs/synth_1/calc.vds @@ -0,0 +1,306 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Nov 7 02:28:12 2024 +# Process ID: 21720 +# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1 +# Command line: vivado.exe -log calc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source calc.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1/calc.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source calc.tcl -notrace +Command: synth_design -top calc -part xc7a35tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 28152 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 410.371 ; gain = 97.773 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'calc' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/calc.v:23] +INFO: [Synth 8-6157] synthesizing module 'judge' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/judge.v:23] +INFO: [Synth 8-6155] done synthesizing module 'judge' (1#1) [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/judge.v:23] +INFO: [Synth 8-6157] synthesizing module 'SegDisplayCtrl' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v:23] +INFO: [Synth 8-6155] done synthesizing module 'SegDisplayCtrl' (2#1) [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v:23] +INFO: [Synth 8-6155] done synthesizing module 'calc' (3#1) [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/calc.v:23] +WARNING: [Synth 8-3917] design calc has port seg_cs[3] driven by constant 0 +WARNING: [Synth 8-3917] design calc has port seg_cs[2] driven by constant 0 +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 465.418 ; gain = 152.820 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 465.418 ; gain = 152.820 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 465.418 ; gain = 152.820 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/calc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/calc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 770.922 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5587] ROM size for "seg" is below threshold of ROM address width. It will be mapped to LUTs +WARNING: [Synth 8-327] inferring latch for variable 'result_reg' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/judge.v:29] +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 5 Bit Adders := 1 ++---XORs : + 2 Input 5 Bit XORs := 1 ++---Registers : + 5 Bit Registers := 1 ++---Muxes : + 6 Input 7 Bit Muxes := 1 + 3 Input 5 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module calc +Detailed RTL Component Info : ++---Adders : + 2 Input 5 Bit Adders := 1 ++---XORs : + 2 Input 5 Bit XORs := 1 ++---Registers : + 5 Bit Registers := 1 +Module judge +Detailed RTL Component Info : ++---Muxes : + 3 Input 5 Bit Muxes := 1 +Module SegDisplayCtrl +Detailed RTL Component Info : ++---Muxes : + 6 Input 7 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3917] design calc has port seg_cs[3] driven by constant 0 +WARNING: [Synth 8-3917] design calc has port seg_cs[2] driven by constant 0 +WARNING: [Synth 8-3917] design calc has port seg_cs[1] driven by constant 0 +INFO: [Synth 8-3886] merging instance 'run/result_reg[0]' (LDC) to 'run/result_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\run/result_reg[4] ) +WARNING: [Synth 8-3332] Sequential element (run/result_reg[4]) is unused and will be removed from module calc. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 770.922 ; gain = 458.324 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 786.383 ; gain = 473.785 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 786.383 ; gain = 473.785 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 786.754 ; gain = 474.156 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |BUFG | 1| +|2 |LUT2 | 4| +|3 |LUT3 | 4| +|4 |LUT4 | 2| +|5 |LUT5 | 11| +|6 |LUT6 | 12| +|7 |FDRE | 5| +|8 |LDC | 1| +|9 |LDCP | 2| +|10 |IBUF | 14| +|11 |OBUF | 16| ++------+-----+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 72| +|2 | run |judge | 18| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 5 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 787.938 ; gain = 169.836 +Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.938 ; gain = 475.340 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 17 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 3 instances were transformed. + LDC => LDCE: 1 instances + LDCP => LDCP (GND, LUT3, LUT3, LDCE, VCC): 2 instances + +INFO: [Common 17-83] Releasing license: Synthesis +21 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 804.738 ; gain = 504.793 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1/calc.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file calc_utilization_synth.rpt -pb calc_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 804.738 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Thu Nov 7 02:28:37 2024... diff --git a/Exp4/Exp4.runs/synth_1/calc_utilization_synth.pb b/Exp4/Exp4.runs/synth_1/calc_utilization_synth.pb new file mode 100644 index 0000000..9366138 Binary files /dev/null and b/Exp4/Exp4.runs/synth_1/calc_utilization_synth.pb differ diff --git a/Exp4/Exp4.runs/synth_1/calc_utilization_synth.rpt b/Exp4/Exp4.runs/synth_1/calc_utilization_synth.rpt new file mode 100644 index 0000000..9a0a367 --- /dev/null +++ b/Exp4/Exp4.runs/synth_1/calc_utilization_synth.rpt @@ -0,0 +1,177 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Nov 7 02:28:37 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file calc_utilization_synth.rpt -pb calc_utilization_synth.pb +| Design : calc +| Device : 7a35tcsg324-1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 33 | 0 | 20800 | 0.16 | +| LUT as Logic | 33 | 0 | 20800 | 0.16 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 8 | 0 | 41600 | 0.02 | +| Register as Flip Flop | 5 | 0 | 41600 | 0.01 | +| Register as Latch | 3 | 0 | 41600 | <0.01 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 2 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 1 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 5 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 30 | 0 | 210 | 14.29 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 16 | IO | +| IBUF | 14 | IO | +| LUT6 | 12 | LUT | +| LUT5 | 11 | LUT | +| LUT3 | 8 | LUT | +| FDRE | 5 | Flop & Latch | +| LUT2 | 4 | LUT | +| LDCE | 3 | Flop & Latch | +| LUT4 | 2 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp4/Exp4.runs/synth_1/gen_run.xml b/Exp4/Exp4.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..f2e4cb4 --- /dev/null +++ b/Exp4/Exp4.runs/synth_1/gen_run.xml @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp4/Exp4.runs/synth_1/htr.txt b/Exp4/Exp4.runs/synth_1/htr.txt new file mode 100644 index 0000000..ddbdbc1 --- /dev/null +++ b/Exp4/Exp4.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log calc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source calc.tcl diff --git a/Exp4/Exp4.runs/synth_1/vivado.jou b/Exp4/Exp4.runs/synth_1/vivado.jou new file mode 100644 index 0000000..d6e7760 --- /dev/null +++ b/Exp4/Exp4.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Nov 7 02:28:12 2024 +# Process ID: 21720 +# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1 +# Command line: vivado.exe -log calc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source calc.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1/calc.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source calc.tcl -notrace diff --git a/Exp4/Exp4.runs/synth_1/vivado.pb b/Exp4/Exp4.runs/synth_1/vivado.pb new file mode 100644 index 0000000..0dc68d0 Binary files /dev/null and b/Exp4/Exp4.runs/synth_1/vivado.pb differ diff --git a/Exp4/Exp4.sim/sim_1/behav/xsim/calc_tb.tcl b/Exp4/Exp4.sim/sim_1/behav/xsim/calc_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp4/Exp4.sim/sim_1/behav/xsim/calc_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp4/Exp4.sim/sim_1/behav/xsim/calc_tb_vlog.prj b/Exp4/Exp4.sim/sim_1/behav/xsim/calc_tb_vlog.prj new file mode 100644 index 0000000..d190392 --- /dev/null +++ b/Exp4/Exp4.sim/sim_1/behav/xsim/calc_tb_vlog.prj @@ -0,0 +1,12 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp4.srcs/sources_1/new/SegDisplayCtrl.v" \ +"../../../../Exp4.srcs/sources_1/new/calc.v" \ +"../../../../Exp4.srcs/sources_1/new/judge.v" \ +"../../../../Exp4.srcs/sim_1/new/calc_tb.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp4/Exp4.sim/sim_1/behav/xsim/glbl.v b/Exp4/Exp4.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp4/Exp4.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.jou b/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..4047d7d --- /dev/null +++ b/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 13 22:33:02 2024 +# Process ID: 36096 +# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk_35820.backup.jou b/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk_35820.backup.jou new file mode 100644 index 0000000..3881957 --- /dev/null +++ b/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk_35820.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 13 22:26:32 2024 +# Process ID: 35820 +# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp4/Exp4.sim/sim_1/behav/xsim/xelab.pb b/Exp4/Exp4.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..ce8cf1d Binary files /dev/null and b/Exp4/Exp4.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/Compile_Options.txt b/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..c912b69 --- /dev/null +++ b/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "56490f59f5644a478a040843011181be" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "calc_tb_behav" "xil_defaultlib.calc_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/TempBreakPointFile.txt b/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/obj/xsim_1.c b/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..e561c93 --- /dev/null +++ b/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/obj/xsim_1.c @@ -0,0 +1,119 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void execute_24(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_9(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_4(char*, char *); +extern void execute_8(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_25(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_28(char*, char *); +extern void execute_29(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[25] = {(funcp)execute_10, (funcp)execute_11, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_5, (funcp)execute_6, (funcp)execute_9, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_4, (funcp)execute_8, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 25; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/calc_tb_behav/xsim.reloc", (void **)funcTab, 25); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/calc_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/calc_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/calc_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/calc_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/calc_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/xsim.mem b/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/xsim.mem new file mode 100644 index 0000000..911ce17 Binary files /dev/null and b/Exp4/Exp4.sim/sim_1/behav/xsim/xsim.dir/calc_tb_behav/xsim.mem differ diff --git a/Exp4/Exp4.sim/sim_1/behav/xsim/xvlog.pb b/Exp4/Exp4.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..ad55def Binary files /dev/null and b/Exp4/Exp4.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Exp4/Exp4.srcs/constrs_1/new/calc.xdc b/Exp4/Exp4.srcs/constrs_1/new/calc.xdc new file mode 100644 index 0000000..7c62bb5 --- /dev/null +++ b/Exp4/Exp4.srcs/constrs_1/new/calc.xdc @@ -0,0 +1,61 @@ +set_property IOSTANDARD LVCMOS33 [get_ports {data1[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {data1[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {data1[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {data1[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {data2[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {data2[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {data2[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {data2[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {result[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {result[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {result[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {result[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {result[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {type[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {type[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {type[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {type[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {type[0]}] +set_property PACKAGE_PIN P5 [get_ports {data1[3]}] +set_property PACKAGE_PIN P4 [get_ports {data1[2]}] +set_property PACKAGE_PIN P3 [get_ports {data1[1]}] +set_property PACKAGE_PIN P2 [get_ports {data1[0]}] +set_property PACKAGE_PIN R2 [get_ports {data2[3]}] +set_property PACKAGE_PIN M4 [get_ports {data2[2]}] +set_property PACKAGE_PIN N4 [get_ports {data2[1]}] +set_property PACKAGE_PIN R1 [get_ports {data2[0]}] +set_property PACKAGE_PIN F6 [get_ports {result[4]}] +set_property PACKAGE_PIN G4 [get_ports {result[3]}] +set_property PACKAGE_PIN G3 [get_ports {result[2]}] +set_property PACKAGE_PIN J4 [get_ports {result[1]}] +set_property PACKAGE_PIN H4 [get_ports {result[0]}] +set_property PACKAGE_PIN D4 [get_ports {seg[6]}] +set_property PACKAGE_PIN E3 [get_ports {seg[5]}] +set_property PACKAGE_PIN D3 [get_ports {seg[4]}] +set_property PACKAGE_PIN F4 [get_ports {seg[3]}] +set_property PACKAGE_PIN F3 [get_ports {seg[2]}] +set_property PACKAGE_PIN E2 [get_ports {seg[1]}] +set_property PACKAGE_PIN D2 [get_ports {seg[0]}] +set_property PACKAGE_PIN G1 [get_ports {seg_cs[3]}] +set_property PACKAGE_PIN F1 [get_ports {seg_cs[2]}] +set_property PACKAGE_PIN E1 [get_ports {seg_cs[1]}] +set_property PACKAGE_PIN G6 [get_ports {seg_cs[0]}] +set_property PACKAGE_PIN U4 [get_ports {type[4]}] +set_property PACKAGE_PIN V1 [get_ports {type[3]}] +set_property PACKAGE_PIN R15 [get_ports {type[2]}] +set_property PACKAGE_PIN R11 [get_ports {type[1]}] +set_property PACKAGE_PIN R17 [get_ports {type[0]}] + +set_property PACKAGE_PIN P17 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports clk] diff --git a/Exp4/Exp4.srcs/sim_1/new/calc_tb.v b/Exp4/Exp4.srcs/sim_1/new/calc_tb.v new file mode 100644 index 0000000..20112e7 --- /dev/null +++ b/Exp4/Exp4.srcs/sim_1/new/calc_tb.v @@ -0,0 +1,60 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/11/13 22:21:16 +// Design Name: +// Module Name: calc_tb +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module calc_tb(); + reg [3:0] data1; + reg [3:0] data2; + reg [4:0] type; + reg clk; + wire [4:0] result; + wire [6:0] seg; + wire [3:0] seg_cs; + calc uut ( + .data1(data1), + .data2(data2), + .type(type), + .clk(clk), + .result(result), + .seg(seg), + .seg_cs(seg_cs) + ); + initial begin + clk = 0; + forever #5 clk = ~clk; // Clock signal + end + initial begin + data1 = 4'b0011; + data2 = 4'b0101; + type = 5'b10000; #10; // Plus + type = 5'b01000; #10; // AND + type = 5'b00100; #10; // OR + type = 5'b00010; #10; // XOR + type = 5'b00001; #10; // Judge 1 < + data1 = 4'b0101; + data2 = 4'b0011; + type = 5'b00001; #10; // Judge 2 > + data1 = 4'b0101; + data2 = 4'b0101; + type = 5'b00001; #10; // Judge 3 = + $stop; + end +endmodule \ No newline at end of file diff --git a/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v b/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v new file mode 100644 index 0000000..0e65109 --- /dev/null +++ b/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v @@ -0,0 +1,37 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/31 11:26:14 +// Design Name: +// Module Name: SegDisplayCtrl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module SegDisplayCtrl( + input wire [4:0] type, + output reg [6:0] seg +); +always @(*) begin + case (type) + 5'b10000: seg = 7'b1110111; // a + 5'b01000: seg = 7'b0011111; // b + 5'b00100: seg = 7'b1001110; // c + 5'b00010: seg = 7'b0111101; // d + 5'b00001: seg = 7'b1001111; // e + default: seg = 7'b0000000; + endcase +end +endmodule diff --git a/Exp4/Exp4.srcs/sources_1/new/calc.v b/Exp4/Exp4.srcs/sources_1/new/calc.v new file mode 100644 index 0000000..e4314c7 --- /dev/null +++ b/Exp4/Exp4.srcs/sources_1/new/calc.v @@ -0,0 +1,51 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/31 10:43:01 +// Design Name: +// Module Name: calc +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module calc( + input [3:0] data1, + input [3:0] data2, + input [4:0] type, + input clk, + output reg [4:0] result, + output wire [6:0] seg, + output reg [3:0] seg_cs +); +reg [4:0] stored_type = 5'b00000; +wire [4:0] judge_result; +wire [4:0] operation_result; +judge run (.data1(data1), .data2(data2), .result(judge_result)); +always @(posedge clk) begin + if (type != 5'b00000) stored_type <= type; +end +always @(*) begin + case (stored_type) + 5'b10000: result = data1 + data2; + 5'b01000: result = data1 & data2; + 5'b00100: result = data1 | data2; + 5'b00010: result = data1 ^ data2; + 5'b00001: result = judge_result; + default: result = 5'b00000; + endcase + seg_cs = (stored_type != 5'b00000) ? 4'b0001 : 4'b0000; +end +SegDisplayCtrl unit (.type(stored_type), .seg(seg)); +endmodule diff --git a/Exp4/Exp4.srcs/sources_1/new/judge.v b/Exp4/Exp4.srcs/sources_1/new/judge.v new file mode 100644 index 0000000..673d48b --- /dev/null +++ b/Exp4/Exp4.srcs/sources_1/new/judge.v @@ -0,0 +1,33 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/31 11:22:30 +// Design Name: +// Module Name: judge +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module judge( + input [3:0] data1, + input [3:0] data2, + output reg [4:0] result +); +always @(*) begin + if (data1 > data2) result = 4'b1000; + else if (data1 < data2) result = 4'b0100; + else if (data1 == data2) result = 4'b0010; +end +endmodule diff --git a/Exp4/Exp4.xpr b/Exp4/Exp4.xpr new file mode 100644 index 0000000..efb68d8 --- /dev/null +++ b/Exp4/Exp4.xpr @@ -0,0 +1,165 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp4/vivado.jou b/Exp4/vivado.jou new file mode 100644 index 0000000..bd36864 --- /dev/null +++ b/Exp4/vivado.jou @@ -0,0 +1,14 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Mon Dec 2 10:27:41 2024 +# Process ID: 18304 +# Current directory: F:/Schoolwork/DigitalLogic/Exp4 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11156 F:\Schoolwork\DigitalLogic\Exp4\Exp4.xpr +# Log file: F:/Schoolwork/DigitalLogic/Exp4/vivado.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp4\vivado.jou +#----------------------------------------------------------- +start_gui +open_project F:/Schoolwork/DigitalLogic/Exp4/Exp4.xpr +update_compile_order -fileset sources_1 diff --git a/Exp4/vivado_19868.backup.jou b/Exp4/vivado_19868.backup.jou new file mode 100644 index 0000000..51463fa --- /dev/null +++ b/Exp4/vivado_19868.backup.jou @@ -0,0 +1,14 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Sun Dec 1 21:44:01 2024 +# Process ID: 19868 +# Current directory: F:/Schoolwork/DigitalLogic/Exp4 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent8772 F:\Schoolwork\DigitalLogic\Exp4\Exp4.xpr +# Log file: F:/Schoolwork/DigitalLogic/Exp4/vivado.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp4\vivado.jou +#----------------------------------------------------------- +start_gui +open_project F:/Schoolwork/DigitalLogic/Exp4/Exp4.xpr +update_compile_order -fileset sources_1 diff --git a/Exp4/vivado_26344.backup.jou b/Exp4/vivado_26344.backup.jou new file mode 100644 index 0000000..a66d447 --- /dev/null +++ b/Exp4/vivado_26344.backup.jou @@ -0,0 +1,44 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 13 21:13:18 2024 +# Process ID: 26344 +# Current directory: F:/Schoolwork/DigitalLogic/Exp4 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent29944 F:\Schoolwork\DigitalLogic\Exp4\Exp4.xpr +# Log file: F:/Schoolwork/DigitalLogic/Exp4/vivado.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp4\vivado.jou +#----------------------------------------------------------- +start_gui +open_project F:/Schoolwork/DigitalLogic/Exp4/Exp4.xpr +update_compile_order -fileset sources_1 +open_hw +connect_hw_server +refresh_hw_server {localhost:3121} +open_hw_target {localhost:3121/xilinx_tcf/Xilinx/1234-tulA} +set_property PROGRAM.FILE {F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.bit} [get_hw_devices xc7a35t_0] +current_hw_device [get_hw_devices xc7a35t_0] +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0] +set_property PROBES.FILE {} [get_hw_devices xc7a35t_0] +set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0] +set_property PROGRAM.FILE {F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.bit} [get_hw_devices xc7a35t_0] +program_hw_devices [get_hw_devices xc7a35t_0] +refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0] +close_hw +file mkdir F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sim_1/new +set_property SOURCE_SET sources_1 [get_filesets sim_1] +close [ open F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sim_1/new/calc_tb.v w ] +add_files -fileset sim_1 F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sim_1/new/calc_tb.v +update_compile_order -fileset sim_1 +update_compile_order -fileset sim_1 +launch_simulation +source calc_tb.tcl +synth_design -rtl -name rtl_1 +close_sim +open_hw +connect_hw_server +open_hw_target +set_property PROGRAM.FILE {F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.bit} [get_hw_devices xc7a35t_0] +current_hw_device [get_hw_devices xc7a35t_0] +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0] +close_hw_target {localhost:3121/xilinx_tcf/Xilinx/1234-tulA} diff --git a/Exp5-1/Exp5-1.cache/wt/webtalk_pa.xml b/Exp5-1/Exp5-1.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..bc8109f --- /dev/null +++ b/Exp5-1/Exp5-1.cache/wt/webtalk_pa.xml @@ -0,0 +1,56 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp5-1/Exp5-1.ip_user_files/README.txt b/Exp5-1/Exp5-1.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp5-1/Exp5-1.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/DFlipFlop_tb.tcl b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/DFlipFlop_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/DFlipFlop_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/DFlipFlop_tb_vlog.prj b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/DFlipFlop_tb_vlog.prj new file mode 100644 index 0000000..7329e7d --- /dev/null +++ b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/DFlipFlop_tb_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp5-1.srcs/sources_1/new/DFlipFlop.v" \ +"../../../../Exp5-1.srcs/sim_1/new/DFlipFlop_tb.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/glbl.v b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/webtalk.jou b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..77a3dd5 --- /dev/null +++ b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Sun Dec 1 23:01:42 2024 +# Process ID: 10636 +# Current directory: F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/webtalk_15748.backup.jou b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/webtalk_15748.backup.jou new file mode 100644 index 0000000..05be23d --- /dev/null +++ b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/webtalk_15748.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Sun Nov 24 20:31:34 2024 +# Process ID: 15748 +# Current directory: F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/webtalk_17748.backup.jou b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/webtalk_17748.backup.jou new file mode 100644 index 0000000..3556204 --- /dev/null +++ b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/webtalk_17748.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 27 15:40:27 2024 +# Process ID: 17748 +# Current directory: F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xelab.pb b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..ed5ef6d Binary files /dev/null and b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/Compile_Options.txt b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..6b65001 --- /dev/null +++ b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "4decd03d1e614943807131858106a64c" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "DFlipFlop_tb_behav" "xil_defaultlib.DFlipFlop_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/TempBreakPointFile.txt b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/obj/xsim_1.c b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..3a277f3 --- /dev/null +++ b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/obj/xsim_1.c @@ -0,0 +1,109 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_5(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_3(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_9(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[15] = {(funcp)execute_4, (funcp)execute_5, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_3, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 15; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/DFlipFlop_tb_behav/xsim.reloc", (void **)funcTab, 15); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/DFlipFlop_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/DFlipFlop_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/DFlipFlop_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/DFlipFlop_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/DFlipFlop_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..f457766 --- /dev/null +++ b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Mon Dec 2 10:47:15 2024" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.1 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2188600" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "78ec1a93-fd1a-4b14-8c4b-87f04256706b" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "4decd03d1e614943807131858106a64c" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "13th Gen Intel(R) Core(TM) i7-13700H" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2918 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "55 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6552_KB" -context "xsim\\usage" +webtalk_transmit -clientid 669397634 -regid "" -xml F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/xsim.mem b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/xsim.mem new file mode 100644 index 0000000..1e993db Binary files /dev/null and b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xsim.dir/DFlipFlop_tb_behav/xsim.mem differ diff --git a/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xvlog.pb b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..b155e40 --- /dev/null +++ b/Exp5-1/Exp5-1.sim/sim_1/behav/xsim/xvlog.pb @@ -0,0 +1,4 @@ + + + +End Record \ No newline at end of file diff --git a/Exp5-1/Exp5-1.srcs/sim_1/new/DFlipFlop_tb.v b/Exp5-1/Exp5-1.srcs/sim_1/new/DFlipFlop_tb.v new file mode 100644 index 0000000..e7c17c5 --- /dev/null +++ b/Exp5-1/Exp5-1.srcs/sim_1/new/DFlipFlop_tb.v @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/11/24 20:30:43 +// Design Name: +// Module Name: DFlipFlop_tb +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module DFlipFlop_tb; + reg D, clk; + wire Q; +DFlipFlop uut ( + .D(D), + .clk(clk), + .Q(Q) +); +initial begin + clk = 0; + forever #10 clk = ~clk; +end +initial begin + D = 0; #15; + D = 1; #20; + D = 0; #20; + $stop; +end +endmodule diff --git a/Exp5-1/Exp5-1.srcs/sources_1/new/DFlipFlop.v b/Exp5-1/Exp5-1.srcs/sources_1/new/DFlipFlop.v new file mode 100644 index 0000000..11654b4 --- /dev/null +++ b/Exp5-1/Exp5-1.srcs/sources_1/new/DFlipFlop.v @@ -0,0 +1,31 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/11/24 20:29:26 +// Design Name: +// Module Name: DFlipFlop +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module DFlipFlop ( + input wire D, + input wire clk, + output reg Q +); +always @(posedge clk) begin + Q <= D; +end +endmodule \ No newline at end of file diff --git a/Exp5-1/Exp5-1.xpr b/Exp5-1/Exp5-1.xpr new file mode 100644 index 0000000..3aff935 --- /dev/null +++ b/Exp5-1/Exp5-1.xpr @@ -0,0 +1,142 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp5-1/vivado.jou b/Exp5-1/vivado.jou new file mode 100644 index 0000000..fc2af36 --- /dev/null +++ b/Exp5-1/vivado.jou @@ -0,0 +1,17 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Mon Dec 2 10:28:47 2024 +# Process ID: 6940 +# Current directory: F:/Schoolwork/DigitalLogic/Exp5-1 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent7884 F:\Schoolwork\DigitalLogic\Exp5-1\Exp5-1.xpr +# Log file: F:/Schoolwork/DigitalLogic/Exp5-1/vivado.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp5-1\vivado.jou +#----------------------------------------------------------- +start_gui +open_project F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.xpr +update_compile_order -fileset sources_1 +launch_simulation +source DFlipFlop_tb.tcl +close_sim diff --git a/Exp5-1/vivado_26464.backup.jou b/Exp5-1/vivado_26464.backup.jou new file mode 100644 index 0000000..1d3563d --- /dev/null +++ b/Exp5-1/vivado_26464.backup.jou @@ -0,0 +1,24 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Sun Dec 1 22:25:46 2024 +# Process ID: 26464 +# Current directory: F:/Schoolwork/DigitalLogic/Exp5-1 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent5180 F:\Schoolwork\DigitalLogic\Exp5-1\Exp5-1.xpr +# Log file: F:/Schoolwork/DigitalLogic/Exp5-1/vivado.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp5-1\vivado.jou +#----------------------------------------------------------- +start_gui +open_project F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.xpr +update_compile_order -fileset sources_1 +set_property SOURCE_SET sources_1 [get_filesets sim_1] +close [ open F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.srcs/sim_1/new/counter_10_tb.v w ] +add_files -fileset sim_1 F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.srcs/sim_1/new/counter_10_tb.v +update_compile_order -fileset sim_1 +launch_simulation +source DFlipFlop_tb.tcl +close_sim +export_ip_user_files -of_objects [get_files F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.srcs/sim_1/new/counter_10_tb.v] -no_script -reset -force -quiet +remove_files -fileset sim_1 F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.srcs/sim_1/new/counter_10_tb.v +file delete -force F:/Schoolwork/DigitalLogic/Exp5-1/Exp5-1.srcs/sim_1/new/counter_10_tb.v diff --git a/Exp5-2-1/Exp5-2-1.cache/wt/webtalk_pa.xml b/Exp5-2-1/Exp5-2-1.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..2d29495 --- /dev/null +++ b/Exp5-2-1/Exp5-2-1.cache/wt/webtalk_pa.xml @@ -0,0 +1,44 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp5-2-1/Exp5-2-1.ip_user_files/README.txt b/Exp5-2-1/Exp5-2-1.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp5-2-1/Exp5-2-1.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/SyncDFlipFlop_tb.tcl b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/SyncDFlipFlop_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/SyncDFlipFlop_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/SyncDFlipFlop_tb_vlog.prj b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/SyncDFlipFlop_tb_vlog.prj new file mode 100644 index 0000000..0668695 --- /dev/null +++ b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/SyncDFlipFlop_tb_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp5-2-1.srcs/sources_1/new/SyncDFlipFlop.v" \ +"../../../../Exp5-2-1.srcs/sim_1/new/SyncDFlipFlop_tb.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/glbl.v b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/webtalk.jou b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..08371ac --- /dev/null +++ b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 27 15:40:25 2024 +# Process ID: 10224 +# Current directory: F:/Schoolwork/DigitalLogic/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/webtalk_19920.backup.jou b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/webtalk_19920.backup.jou new file mode 100644 index 0000000..a4bd8f4 --- /dev/null +++ b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/webtalk_19920.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 27 04:03:08 2024 +# Process ID: 19920 +# Current directory: F:/Schoolwork/DigitalLogic/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xelab.pb b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..4b19a10 Binary files /dev/null and b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/Compile_Options.txt b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..2e163e5 --- /dev/null +++ b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "40faf35dcc6949ebaea6ef8e73de4456" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "SyncDFlipFlop_tb_behav" "xil_defaultlib.SyncDFlipFlop_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/TempBreakPointFile.txt b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/obj/xsim_1.c b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..3184dc6 --- /dev/null +++ b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/obj/xsim_1.c @@ -0,0 +1,111 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_5(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_3(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_9(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[17] = {(funcp)execute_4, (funcp)execute_5, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_3, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 17; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/SyncDFlipFlop_tb_behav/xsim.reloc", (void **)funcTab, 17); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/SyncDFlipFlop_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/SyncDFlipFlop_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/SyncDFlipFlop_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/SyncDFlipFlop_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/SyncDFlipFlop_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/xsim.mem b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/xsim.mem new file mode 100644 index 0000000..2641a8e Binary files /dev/null and b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xsim.dir/SyncDFlipFlop_tb_behav/xsim.mem differ diff --git a/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xvlog.pb b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..bed9b3d Binary files /dev/null and b/Exp5-2-1/Exp5-2-1.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Exp5-2-1/Exp5-2-1.srcs/sim_1/new/SyncDFlipFlop_tb.v b/Exp5-2-1/Exp5-2-1.srcs/sim_1/new/SyncDFlipFlop_tb.v new file mode 100644 index 0000000..0cf3e30 --- /dev/null +++ b/Exp5-2-1/Exp5-2-1.srcs/sim_1/new/SyncDFlipFlop_tb.v @@ -0,0 +1,50 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/11/27 03:58:06 +// Design Name: +// Module Name: SyncDFlipFlop_tb +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module SyncDFlipFlop_tb; +reg D, clk, rst, set; +wire Q; +SyncDFlipFlop uut ( + .D(D), + .clk(clk), + .rst(rst), + .set(set), + .Q(Q) +); +initial begin + clk = 0; + forever #10 clk = ~clk; +end +initial begin + D = 0; rst = 0; set = 0; #15; + // Reset test + rst = 1; #20; + rst = 0; #20; + // Set test + set = 1; #20; + set = 0; #20; + // Data input test + D = 1; #30; + D = 0; #30; + $stop; +end +endmodule diff --git a/Exp5-2-1/Exp5-2-1.srcs/sources_1/new/SyncDFlipFlop.v b/Exp5-2-1/Exp5-2-1.srcs/sources_1/new/SyncDFlipFlop.v new file mode 100644 index 0000000..71a62df --- /dev/null +++ b/Exp5-2-1/Exp5-2-1.srcs/sources_1/new/SyncDFlipFlop.v @@ -0,0 +1,39 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/11/24 20:35:59 +// Design Name: +// Module Name: SyncDFlipFlop +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module SyncDFlipFlop ( + input wire D, + input wire clk, + input wire rst, + input wire set, + output reg Q +); +always @(posedge clk) begin + if (rst) + Q <= 0; // Reset Q clear + else if (set) + Q <= 1; // Set Q = 1 + else + Q <= D; +end +endmodule + diff --git a/Exp5-2-1/Exp5-2-1.xpr b/Exp5-2-1/Exp5-2-1.xpr new file mode 100644 index 0000000..429a9dc --- /dev/null +++ b/Exp5-2-1/Exp5-2-1.xpr @@ -0,0 +1,145 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + diff --git a/Exp5-2-1/vivado.jou b/Exp5-2-1/vivado.jou new file mode 100644 index 0000000..940b154 --- /dev/null +++ b/Exp5-2-1/vivado.jou @@ -0,0 +1,14 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Mon Dec 2 10:28:52 2024 +# Process ID: 6088 +# Current directory: F:/Schoolwork/DigitalLogic/Exp5-2-1 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11040 F:\Schoolwork\DigitalLogic\Exp5-2-1\Exp5-2-1.xpr +# Log file: F:/Schoolwork/DigitalLogic/Exp5-2-1/vivado.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp5-2-1\vivado.jou +#----------------------------------------------------------- +start_gui +open_project F:/Schoolwork/DigitalLogic/Exp5-2-1/Exp5-2-1.xpr +update_compile_order -fileset sources_1 diff --git a/Exp5-2-2/Exp5-2-2.cache/wt/webtalk_pa.xml b/Exp5-2-2/Exp5-2-2.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..2987683 --- /dev/null +++ b/Exp5-2-2/Exp5-2-2.cache/wt/webtalk_pa.xml @@ -0,0 +1,44 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp5-2-2/Exp5-2-2.ip_user_files/README.txt b/Exp5-2-2/Exp5-2-2.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp5-2-2/Exp5-2-2.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/AsyncDFlipFlop_tb.tcl b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/AsyncDFlipFlop_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/AsyncDFlipFlop_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/AsyncDFlipFlop_tb_vlog.prj b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/AsyncDFlipFlop_tb_vlog.prj new file mode 100644 index 0000000..b71c1dd --- /dev/null +++ b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/AsyncDFlipFlop_tb_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp5-2-2.srcs/sources_1/new/AsyncDFlipFlop.v" \ +"../../../../Exp5-2-2.srcs/sim_1/new/AsyncDFlipFlop_tb.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/glbl.v b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/webtalk.jou b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..bb0f5e7 --- /dev/null +++ b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 27 15:40:21 2024 +# Process ID: 5576 +# Current directory: F:/Schoolwork/DigitalLogic/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/webtalk_28036.backup.jou b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/webtalk_28036.backup.jou new file mode 100644 index 0000000..bf77eab --- /dev/null +++ b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/webtalk_28036.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 27 04:06:21 2024 +# Process ID: 28036 +# Current directory: F:/Schoolwork/DigitalLogic/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xelab.pb b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..596f79f Binary files /dev/null and b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/Compile_Options.txt b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..c484bdb --- /dev/null +++ b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "3e5c53c971ec4d04b1f9bfab9126bca1" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "AsyncDFlipFlop_tb_behav" "xil_defaultlib.AsyncDFlipFlop_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/TempBreakPointFile.txt b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/obj/xsim_1.c b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..9b2d851 --- /dev/null +++ b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/obj/xsim_1.c @@ -0,0 +1,111 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_5(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_3(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_9(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[17] = {(funcp)execute_4, (funcp)execute_5, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_3, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 17; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/AsyncDFlipFlop_tb_behav/xsim.reloc", (void **)funcTab, 17); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/AsyncDFlipFlop_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/AsyncDFlipFlop_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/AsyncDFlipFlop_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/AsyncDFlipFlop_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/AsyncDFlipFlop_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/xsim.mem b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/xsim.mem new file mode 100644 index 0000000..fc599e0 Binary files /dev/null and b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xsim.dir/AsyncDFlipFlop_tb_behav/xsim.mem differ diff --git a/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xvlog.pb b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..6639f89 Binary files /dev/null and b/Exp5-2-2/Exp5-2-2.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Exp5-2-2/Exp5-2-2.srcs/sim_1/new/AsyncDFlipFlop_tb.v b/Exp5-2-2/Exp5-2-2.srcs/sim_1/new/AsyncDFlipFlop_tb.v new file mode 100644 index 0000000..daabc02 --- /dev/null +++ b/Exp5-2-2/Exp5-2-2.srcs/sim_1/new/AsyncDFlipFlop_tb.v @@ -0,0 +1,51 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/11/27 04:01:26 +// Design Name: +// Module Name: AsyncDFlipFlop_tb +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module AsyncDFlipFlop_tb; +reg D, clk, rst, set; +wire Q; +AsyncDFlipFlop uut ( + .D(D), + .clk(clk), + .rst(rst), + .set(set), + .Q(Q) +); +initial begin + clk = 0; + forever #10 clk = ~clk; +end +initial begin + D = 0; rst = 0; set = 0; #15; + // Reset test + rst = 1; #20; + rst = 0; #20; + // Set test + set = 1; #20; + set = 0; #20; + // Data input test + D = 1; #30; + D = 0; #30; + $stop; +end +endmodule + diff --git a/Exp5-2-2/Exp5-2-2.srcs/sources_1/new/AsyncDFlipFlop.v b/Exp5-2-2/Exp5-2-2.srcs/sources_1/new/AsyncDFlipFlop.v new file mode 100644 index 0000000..9960d06 --- /dev/null +++ b/Exp5-2-2/Exp5-2-2.srcs/sources_1/new/AsyncDFlipFlop.v @@ -0,0 +1,38 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/11/24 23:40:16 +// Design Name: +// Module Name: AsyncDFlipFlop +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module AsyncDFlipFlop ( + input wire D, + input wire clk, + input wire rst, + input wire set, + output reg Q +); +always @(posedge clk or posedge rst or posedge set) begin + if (rst) + Q <= 0; // Reset Q clear + else if (set) + Q <= 1; // Set Q = 1 + else + Q <= D; +end +endmodule diff --git a/Exp5-2-2/Exp5-2-2.xpr b/Exp5-2-2/Exp5-2-2.xpr new file mode 100644 index 0000000..3a62baf --- /dev/null +++ b/Exp5-2-2/Exp5-2-2.xpr @@ -0,0 +1,145 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + diff --git a/Exp5-2-2/vivado.jou b/Exp5-2-2/vivado.jou new file mode 100644 index 0000000..6aeffee --- /dev/null +++ b/Exp5-2-2/vivado.jou @@ -0,0 +1,14 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Mon Dec 2 10:28:55 2024 +# Process ID: 3676 +# Current directory: F:/Schoolwork/DigitalLogic/Exp5-2-2 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent19792 F:\Schoolwork\DigitalLogic\Exp5-2-2\Exp5-2-2.xpr +# Log file: F:/Schoolwork/DigitalLogic/Exp5-2-2/vivado.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp5-2-2\vivado.jou +#----------------------------------------------------------- +start_gui +open_project F:/Schoolwork/DigitalLogic/Exp5-2-2/Exp5-2-2.xpr +update_compile_order -fileset sources_1 diff --git a/Exp5-3/Exp5-3.cache/wt/webtalk_pa.xml b/Exp5-3/Exp5-3.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..5c670dc --- /dev/null +++ b/Exp5-3/Exp5-3.cache/wt/webtalk_pa.xml @@ -0,0 +1,45 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp5-3/Exp5-3.ip_user_files/README.txt b/Exp5-3/Exp5-3.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp5-3/Exp5-3.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/Register32_tb.tcl b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/Register32_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/Register32_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/Register32_tb_vlog.prj b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/Register32_tb_vlog.prj new file mode 100644 index 0000000..d9d4a5b --- /dev/null +++ b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/Register32_tb_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp5-3.srcs/sources_1/new/Register32.v" \ +"../../../../Exp5-3.srcs/sim_1/new/Register32_tb.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/glbl.v b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/webtalk.jou b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..24b1adb --- /dev/null +++ b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 27 15:40:18 2024 +# Process ID: 33904 +# Current directory: F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/webtalk_34348.backup.jou b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/webtalk_34348.backup.jou new file mode 100644 index 0000000..c22a220 --- /dev/null +++ b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/webtalk_34348.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Nov 27 04:06:33 2024 +# Process ID: 34348 +# Current directory: F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xelab.pb b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..4a295a2 Binary files /dev/null and b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/Compile_Options.txt b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..71460d2 --- /dev/null +++ b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "3466f69b37c149a9988e8ad9bd948ef1" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "Register32_tb_behav" "xil_defaultlib.Register32_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/TempBreakPointFile.txt b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/obj/xsim_1.c b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..0b4f8a3 --- /dev/null +++ b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/obj/xsim_1.c @@ -0,0 +1,111 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_5(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_3(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_9(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[17] = {(funcp)execute_4, (funcp)execute_5, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_3, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 17; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/Register32_tb_behav/xsim.reloc", (void **)funcTab, 17); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/Register32_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/Register32_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/Register32_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/Register32_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/Register32_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/xsim.mem b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/xsim.mem new file mode 100644 index 0000000..2fc5245 Binary files /dev/null and b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xsim.dir/Register32_tb_behav/xsim.mem differ diff --git a/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xvlog.pb b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..7845fea Binary files /dev/null and b/Exp5-3/Exp5-3.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Exp5-3/Exp5-3.srcs/sim_1/new/Register32_tb.v b/Exp5-3/Exp5-3.srcs/sim_1/new/Register32_tb.v new file mode 100644 index 0000000..2790520 --- /dev/null +++ b/Exp5-3/Exp5-3.srcs/sim_1/new/Register32_tb.v @@ -0,0 +1,51 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/11/27 04:03:49 +// Design Name: +// Module Name: Register32_tb +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Register32_tb; +reg [31:0] D; +reg clk, rst, set; +wire [31:0] Q; +Register32 uut ( + .D(D), + .clk(clk), + .rst(rst), + .set(set), + .Q(Q) +); +initial begin + clk = 0; + forever #10 clk = ~clk; +end +initial begin + D = 32'b0; rst = 0; set = 0; #15; + // Reset test + rst = 1; #20; + rst = 0; #20; + // Set test + set = 1; #20; + set = 0; #20; + // Data input test + D = 32'hA5A5A5A5; #30; + D = 32'h5A5A5A5A; #30; + $stop; +end +endmodule diff --git a/Exp5-3/Exp5-3.srcs/sources_1/new/Register32.v b/Exp5-3/Exp5-3.srcs/sources_1/new/Register32.v new file mode 100644 index 0000000..abe359b --- /dev/null +++ b/Exp5-3/Exp5-3.srcs/sources_1/new/Register32.v @@ -0,0 +1,39 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/11/24 23:42:48 +// Design Name: +// Module Name: Register32 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Register32 ( + input wire [31:0] D, + input wire clk, + input wire rst, + input wire set, + output reg [31:0] Q +); +always @(posedge clk or posedge rst or posedge set) begin + if (rst) + Q <= 32'h00000000; // Reset clear + else if (set) + Q <= 32'hFFFFFFFF; // Set all 1 + else + Q <= D; +end +endmodule + diff --git a/Exp5-3/Exp5-3.xpr b/Exp5-3/Exp5-3.xpr new file mode 100644 index 0000000..3061bda --- /dev/null +++ b/Exp5-3/Exp5-3.xpr @@ -0,0 +1,145 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + diff --git a/Exp5-3/vivado.jou b/Exp5-3/vivado.jou new file mode 100644 index 0000000..272f420 --- /dev/null +++ b/Exp5-3/vivado.jou @@ -0,0 +1,14 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Mon Dec 2 10:28:58 2024 +# Process ID: 2072 +# Current directory: F:/Schoolwork/DigitalLogic/Exp5-3 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent20832 F:\Schoolwork\DigitalLogic\Exp5-3\Exp5-3.xpr +# Log file: F:/Schoolwork/DigitalLogic/Exp5-3/vivado.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp5-3\vivado.jou +#----------------------------------------------------------- +start_gui +open_project F:/Schoolwork/DigitalLogic/Exp5-3/Exp5-3.xpr +update_compile_order -fileset sources_1 diff --git a/Exp6-1/Exp6-1.cache/wt/webtalk_pa.xml b/Exp6-1/Exp6-1.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..e853d2c --- /dev/null +++ b/Exp6-1/Exp6-1.cache/wt/webtalk_pa.xml @@ -0,0 +1,67 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp6-1/Exp6-1.hw/hw_1/hw.xml b/Exp6-1/Exp6-1.hw/hw_1/hw.xml new file mode 100644 index 0000000..9793165 --- /dev/null +++ b/Exp6-1/Exp6-1.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/Exp6-1/Exp6-1.ip_user_files/README.txt b/Exp6-1/Exp6-1.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp6-1/Exp6-1.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp6-1/Exp6-1.runs/.jobs/vrs_config_1.xml b/Exp6-1/Exp6-1.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..faf8e44 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp6-1/Exp6-1.runs/.jobs/vrs_config_2.xml b/Exp6-1/Exp6-1.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..cba17e6 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10.tcl b/Exp6-1/Exp6-1.runs/impl_1/counter_10.tcl new file mode 100644 index 0000000..9c24acf --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/counter_10.tcl @@ -0,0 +1,172 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param synth.incrementalSynthesisCache C:/Users/Launchcore/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-57964-W10-20240912132/incrSyn + create_project -in_memory -part xc7a35tcsg324-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.cache/wt [current_project] + set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.xpr [current_project] + set_property ip_output_repo F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/synth_1/counter_10.dcp + read_xdc F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.srcs/constrs_1/new/counter_19.xdc + link_design -top counter_10 -part xc7a35tcsg324-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force counter_10_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file counter_10_drc_opted.rpt -pb counter_10_drc_opted.pb -rpx counter_10_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force counter_10_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file counter_10_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file counter_10_utilization_placed.rpt -pb counter_10_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file counter_10_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force counter_10_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file counter_10_drc_routed.rpt -pb counter_10_drc_routed.pb -rpx counter_10_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file counter_10_methodology_drc_routed.rpt -pb counter_10_methodology_drc_routed.pb -rpx counter_10_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file counter_10_power_routed.rpt -pb counter_10_power_summary_routed.pb -rpx counter_10_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file counter_10_route_status.rpt -pb counter_10_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file counter_10_timing_summary_routed.rpt -pb counter_10_timing_summary_routed.pb -rpx counter_10_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file counter_10_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file counter_10_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force counter_10_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force counter_10.mmi } + write_bitstream -force counter_10.bit + catch {write_debug_probes -quiet -force counter_10} + catch {file copy -force counter_10.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10.vdi b/Exp6-1/Exp6-1.runs/impl_1/counter_10.vdi new file mode 100644 index 0000000..ea63281 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/counter_10.vdi @@ -0,0 +1,445 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 11:42:45 2024 +# Process ID: 26148 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1 +# Command line: vivado.exe -log counter_10.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source counter_10.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source counter_10.tcl -notrace +Command: link_design -top counter_10 -part xc7a35tcsg324-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.srcs/constrs_1/new/counter_19.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.srcs/constrs_1/new/counter_19.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 608.109 ; gain = 302.410 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 621.867 ; gain = 13.758 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1a3a304eb + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1152.344 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1a3a304eb + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1152.344 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1a3a304eb + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1152.344 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1a3a304eb + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1152.344 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1a3a304eb + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1152.344 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1a3a304eb + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1152.344 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1152.344 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1a3a304eb + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1152.344 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1a3a304eb + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1152.344 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1152.344 ; gain = 544.234 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1152.344 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file counter_10_drc_opted.rpt -pb counter_10_drc_opted.pb -rpx counter_10_drc_opted.rpx +Command: report_drc -file counter_10_drc_opted.rpt -pb counter_10_drc_opted.pb -rpx counter_10_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1152.344 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 144551012 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1152.344 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1152.344 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 40a97d45 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.451 . Memory (MB): peak = 1175.508 ; gain = 23.164 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 6ec5449b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.480 . Memory (MB): peak = 1175.508 ; gain = 23.164 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 6ec5449b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.482 . Memory (MB): peak = 1175.508 ; gain = 23.164 +Phase 1 Placer Initialization | Checksum: 6ec5449b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.487 . Memory (MB): peak = 1175.508 ; gain = 23.164 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 67ab0db0 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.669 . Memory (MB): peak = 1175.508 ; gain = 23.164 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 67ab0db0 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.672 . Memory (MB): peak = 1175.508 ; gain = 23.164 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: b44dab5c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.680 . Memory (MB): peak = 1175.508 ; gain = 23.164 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 654b6a0f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.684 . Memory (MB): peak = 1175.508 ; gain = 23.164 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 654b6a0f + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.685 . Memory (MB): peak = 1175.508 ; gain = 23.164 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1600cb152 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.737 . Memory (MB): peak = 1175.508 ; gain = 23.164 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1600cb152 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.739 . Memory (MB): peak = 1175.508 ; gain = 23.164 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1600cb152 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.739 . Memory (MB): peak = 1175.508 ; gain = 23.164 +Phase 3 Detail Placement | Checksum: 1600cb152 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.739 . Memory (MB): peak = 1175.508 ; gain = 23.164 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1600cb152 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.741 . Memory (MB): peak = 1175.508 ; gain = 23.164 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1600cb152 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.748 . Memory (MB): peak = 1175.508 ; gain = 23.164 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1600cb152 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.748 . Memory (MB): peak = 1175.508 ; gain = 23.164 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 225cdd995 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.749 . Memory (MB): peak = 1175.508 ; gain = 23.164 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 225cdd995 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.749 . Memory (MB): peak = 1175.508 ; gain = 23.164 +Ending Placer Task | Checksum: 1c5b8b459 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.752 . Memory (MB): peak = 1175.508 ; gain = 23.164 +INFO: [Common 17-83] Releasing license: Implementation +41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1175.508 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file counter_10_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1183.660 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file counter_10_utilization_placed.rpt -pb counter_10_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1183.660 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file counter_10_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1183.660 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: e83a1a30 ConstDB: 0 ShapeSum: dd7e9a29 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 1294bf7db + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1299.867 ; gain = 116.207 +Post Restoration Checksum: NetGraph: b4a6849b NumContArr: 74a57340 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 1294bf7db + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1305.926 ; gain = 122.266 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 1294bf7db + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1305.926 ; gain = 122.266 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 65671432 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 12301e04d + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 12c9b5e41 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043 +Phase 4 Rip-up And Reroute | Checksum: 12c9b5e41 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 12c9b5e41 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 12c9b5e41 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043 +Phase 6 Post Hold Fix | Checksum: 12c9b5e41 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0168221 % + Global Horizontal Routing Utilization = 0.00429464 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 21.6216%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 12c9b5e41 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 12c9b5e41 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.992 ; gain = 126.332 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 18b7847b5 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.992 ; gain = 126.332 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.992 ; gain = 126.332 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1309.992 ; gain = 126.332 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1309.992 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file counter_10_drc_routed.rpt -pb counter_10_drc_routed.pb -rpx counter_10_drc_routed.rpx +Command: report_drc -file counter_10_drc_routed.rpt -pb counter_10_drc_routed.pb -rpx counter_10_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file counter_10_methodology_drc_routed.rpt -pb counter_10_methodology_drc_routed.pb -rpx counter_10_methodology_drc_routed.rpx +Command: report_methodology -file counter_10_methodology_drc_routed.rpt -pb counter_10_methodology_drc_routed.pb -rpx counter_10_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file counter_10_power_routed.rpt -pb counter_10_power_summary_routed.pb -rpx counter_10_power_routed.rpx +Command: report_power -file counter_10_power_routed.rpt -pb counter_10_power_summary_routed.pb -rpx counter_10_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file counter_10_route_status.rpt -pb counter_10_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file counter_10_timing_summary_routed.rpt -pb counter_10_timing_summary_routed.pb -rpx counter_10_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file counter_10_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file counter_10_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force counter_10.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./counter_10.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +84 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1760.434 ; gain = 417.121 +INFO: [Common 17-206] Exiting Vivado at Thu Dec 12 11:43:50 2024... diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_clock_utilization_routed.rpt b/Exp6-1/Exp6-1.runs/impl_1/counter_10_clock_utilization_routed.rpt new file mode 100644 index 0000000..01e78f7 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/counter_10_clock_utilization_routed.rpt @@ -0,0 +1,145 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 11:43:42 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file counter_10_clock_utilization_routed.rpt +| Design : counter_10 +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +---------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X1Y0 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 4 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | IOB_X0Y26 | IOB_X0Y26 | X0Y0 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 1 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | | | | 4 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 4 | ++----+----+----+ + + +7. Clock Region Cell Placement per Global Clock: Region X1Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 4 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y26 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0} +#endgroup diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_control_sets_placed.rpt b/Exp6-1/Exp6-1.runs/impl_1/counter_10_control_sets_placed.rpt new file mode 100644 index 0000000..bc59f91 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/counter_10_control_sets_placed.rpt @@ -0,0 +1,65 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 11:43:27 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file counter_10_control_sets_placed.rpt +| Design : counter_10 +| Device : xc7a35t +--------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 1 | +| Unused register locations in slices containing registers | 4 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ +| 4 | 1 | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 4 | 1 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++----------------+-----------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++----------------+-----------------+------------------+------------------+----------------+ +| clk_IBUF_BUFG | qout[3]_i_1_n_0 | qout[3]_i_3_n_0 | 1 | 4 | ++----------------+-----------------+------------------+------------------+----------------+ + + diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_opted.pb b/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_opted.pb differ diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_opted.rpt b/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_opted.rpt new file mode 100644 index 0000000..25066fd --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 11:43:26 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file counter_10_drc_opted.rpt -pb counter_10_drc_opted.pb -rpx counter_10_drc_opted.rpx +| Design : counter_10 +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_routed.pb b/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_routed.pb differ diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_routed.rpt b/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_routed.rpt new file mode 100644 index 0000000..4e8d785 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_routed.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 11:43:41 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file counter_10_drc_routed.rpt -pb counter_10_drc_routed.pb -rpx counter_10_drc_routed.rpx +| Design : counter_10 +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_io_placed.rpt b/Exp6-1/Exp6-1.runs/impl_1/counter_10_io_placed.rpt new file mode 100644 index 0000000..e52668e --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/counter_10_io_placed.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 11:43:27 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_io -file counter_10_io_placed.rpt +| Design : counter_10 +| Device : xc7a35t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2013-12-19 +| Package Pin Delay Version : VERS. 2.0 2013-12-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 14 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | qout[3] | High Range | IO_L19N_T3_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | qout[1] | High Range | IO_L20N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G4 | qout[2] | High Range | IO_L20P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J4 | qout[0] | High Range | IO_L21P_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | rco | High Range | IO_L23P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | ent | High Range | IO_L16P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N4 | enp | High Range | IO_L16N_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | din[0] | High Range | IO_L15P_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P3 | din[1] | High Range | IO_L14N_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P4 | din[2] | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P5 | din[3] | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P17 | clk | High Range | IO_L12P_T1_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | clrn | High Range | IO_L17P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| R2 | ldn | High Range | IO_L15N_T2_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_methodology_drc_routed.pb b/Exp6-1/Exp6-1.runs/impl_1/counter_10_methodology_drc_routed.pb new file mode 100644 index 0000000..0d6626b Binary files /dev/null and b/Exp6-1/Exp6-1.runs/impl_1/counter_10_methodology_drc_routed.pb differ diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_methodology_drc_routed.rpt b/Exp6-1/Exp6-1.runs/impl_1/counter_10_methodology_drc_routed.rpt new file mode 100644 index 0000000..daa6473 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/counter_10_methodology_drc_routed.rpt @@ -0,0 +1,55 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 11:43:41 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_methodology -file counter_10_methodology_drc_routed.rpt -pb counter_10_methodology_drc_routed.pb -rpx counter_10_methodology_drc_routed.rpx +| Design : counter_10 +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 4 ++-----------+----------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------+------------+ +| TIMING-17 | Warning | Non-clocked sequential cell | 4 | ++-----------+----------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Warning +Non-clocked sequential cell +The clock pin qout_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Warning +Non-clocked sequential cell +The clock pin qout_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Warning +Non-clocked sequential cell +The clock pin qout_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Warning +Non-clocked sequential cell +The clock pin qout_reg[3]/C is not reached by a timing clock +Related violations: + + diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_opt.dcp b/Exp6-1/Exp6-1.runs/impl_1/counter_10_opt.dcp new file mode 100644 index 0000000..89d6180 Binary files /dev/null and b/Exp6-1/Exp6-1.runs/impl_1/counter_10_opt.dcp differ diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_placed.dcp b/Exp6-1/Exp6-1.runs/impl_1/counter_10_placed.dcp new file mode 100644 index 0000000..d2cb0e8 Binary files /dev/null and b/Exp6-1/Exp6-1.runs/impl_1/counter_10_placed.dcp differ diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_power_routed.rpt b/Exp6-1/Exp6-1.runs/impl_1/counter_10_power_routed.rpt new file mode 100644 index 0000000..eda9934 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/counter_10_power_routed.rpt @@ -0,0 +1,142 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 11:43:42 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_power -file counter_10_power_routed.rpt -pb counter_10_power_summary_routed.pb -rpx counter_10_power_routed.rpx +| Design : counter_10 +| Device : xc7a35tcsg324-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 4.962 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 4.873 | +| Device Static (W) | 0.088 | +| Effective TJA (C/W) | 4.8 | +| Max Ambient (C) | 61.3 | +| Junction Temperature (C) | 48.7 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.032 | 12 | --- | --- | +| LUT as Logic | 0.024 | 7 | 20800 | 0.03 | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| Register | 0.002 | 4 | 41600 | <0.01 | +| Signals | 0.085 | 17 | --- | --- | +| I/O | 4.756 | 14 | 210 | 6.67 | +| Static Power | 0.088 | | | | +| Total | 4.962 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.173 | 0.149 | 0.024 | +| Vccaux | 1.800 | 0.187 | 0.173 | 0.014 | +| Vcco33 | 3.300 | 1.338 | 1.337 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.8 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------------+-----------+ +| Name | Power (W) | ++------------+-----------+ +| counter_10 | 4.873 | ++------------+-----------+ + + diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_power_summary_routed.pb b/Exp6-1/Exp6-1.runs/impl_1/counter_10_power_summary_routed.pb new file mode 100644 index 0000000..f407c5b Binary files /dev/null and b/Exp6-1/Exp6-1.runs/impl_1/counter_10_power_summary_routed.pb differ diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_route_status.pb b/Exp6-1/Exp6-1.runs/impl_1/counter_10_route_status.pb new file mode 100644 index 0000000..87c0f25 Binary files /dev/null and b/Exp6-1/Exp6-1.runs/impl_1/counter_10_route_status.pb differ diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_route_status.rpt b/Exp6-1/Exp6-1.runs/impl_1/counter_10_route_status.rpt new file mode 100644 index 0000000..985acde --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/counter_10_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 35 : + # of nets not needing routing.......... : 18 : + # of internally routed nets........ : 18 : + # of routable nets..................... : 17 : + # of fully routed nets............. : 17 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_routed.dcp b/Exp6-1/Exp6-1.runs/impl_1/counter_10_routed.dcp new file mode 100644 index 0000000..9c3a20f Binary files /dev/null and b/Exp6-1/Exp6-1.runs/impl_1/counter_10_routed.dcp differ diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_timing_summary_routed.pb b/Exp6-1/Exp6-1.runs/impl_1/counter_10_timing_summary_routed.pb new file mode 100644 index 0000000..4526e93 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/counter_10_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_timing_summary_routed.rpt b/Exp6-1/Exp6-1.runs/impl_1/counter_10_timing_summary_routed.rpt new file mode 100644 index 0000000..0019c12 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/counter_10_timing_summary_routed.rpt @@ -0,0 +1,173 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 11:43:42 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file counter_10_timing_summary_routed.rpt -pb counter_10_timing_summary_routed.pb -rpx counter_10_timing_summary_routed.rpx -warn_on_violation +| Design : counter_10 +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 4 register/latch pins with no clock driven by root clock pin: clk (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 12 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 8 input ports with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 5 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_utilization_placed.pb b/Exp6-1/Exp6-1.runs/impl_1/counter_10_utilization_placed.pb new file mode 100644 index 0000000..fe9cd25 Binary files /dev/null and b/Exp6-1/Exp6-1.runs/impl_1/counter_10_utilization_placed.pb differ diff --git a/Exp6-1/Exp6-1.runs/impl_1/counter_10_utilization_placed.rpt b/Exp6-1/Exp6-1.runs/impl_1/counter_10_utilization_placed.rpt new file mode 100644 index 0000000..ffb4259 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/counter_10_utilization_placed.rpt @@ -0,0 +1,202 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 11:43:27 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file counter_10_utilization_placed.rpt -pb counter_10_utilization_placed.pb +| Design : counter_10 +| Device : 7a35tcsg324-1 +| Design State : Fully Placed +----------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 7 | 0 | 20800 | 0.03 | +| LUT as Logic | 7 | 0 | 20800 | 0.03 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 4 | 0 | 41600 | <0.01 | +| Register as Flip Flop | 4 | 0 | 41600 | <0.01 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 4 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 4 | 0 | 8150 | 0.05 | +| SLICEL | 3 | 0 | | | +| SLICEM | 1 | 0 | | | +| LUT as Logic | 7 | 0 | 20800 | 0.03 | +| using O5 output only | 0 | | | | +| using O6 output only | 7 | | | | +| using O5 and O6 | 0 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 4 | 0 | 20800 | 0.02 | +| fully used LUT-FF pairs | 0 | | | | +| LUT-FF pairs with one unused LUT output | 4 | | | | +| LUT-FF pairs with one unused Flip Flop | 4 | | | | +| Unique Control Sets | 1 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 14 | 14 | 210 | 6.67 | +| IOB Master Pads | 8 | | | | +| IOB Slave Pads | 6 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| IBUF | 9 | IO | +| OBUF | 5 | IO | +| FDCE | 4 | Flop & Latch | +| LUT6 | 2 | LUT | +| LUT5 | 2 | LUT | +| LUT3 | 2 | LUT | +| LUT1 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp6-1/Exp6-1.runs/impl_1/gen_run.xml b/Exp6-1/Exp6-1.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..512756c --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/gen_run.xml @@ -0,0 +1,114 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp6-1/Exp6-1.runs/impl_1/htr.txt b/Exp6-1/Exp6-1.runs/impl_1/htr.txt new file mode 100644 index 0000000..a4f5c42 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log counter_10.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source counter_10.tcl -notrace diff --git a/Exp6-1/Exp6-1.runs/impl_1/init_design.pb b/Exp6-1/Exp6-1.runs/impl_1/init_design.pb new file mode 100644 index 0000000..4178374 Binary files /dev/null and b/Exp6-1/Exp6-1.runs/impl_1/init_design.pb differ diff --git a/Exp6-1/Exp6-1.runs/impl_1/opt_design.pb b/Exp6-1/Exp6-1.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..ee916d5 Binary files /dev/null and b/Exp6-1/Exp6-1.runs/impl_1/opt_design.pb differ diff --git a/Exp6-1/Exp6-1.runs/impl_1/place_design.pb b/Exp6-1/Exp6-1.runs/impl_1/place_design.pb new file mode 100644 index 0000000..8e85056 Binary files /dev/null and b/Exp6-1/Exp6-1.runs/impl_1/place_design.pb differ diff --git a/Exp6-1/Exp6-1.runs/impl_1/route_design.pb b/Exp6-1/Exp6-1.runs/impl_1/route_design.pb new file mode 100644 index 0000000..db45da9 Binary files /dev/null and b/Exp6-1/Exp6-1.runs/impl_1/route_design.pb differ diff --git a/Exp6-1/Exp6-1.runs/impl_1/route_report_bus_skew_0.rpt b/Exp6-1/Exp6-1.runs/impl_1/route_report_bus_skew_0.rpt new file mode 100644 index 0000000..847b90a --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/route_report_bus_skew_0.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 11:43:42 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +| Design : counter_10 +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/Exp6-1/Exp6-1.runs/impl_1/usage_statistics_webtalk.xml b/Exp6-1/Exp6-1.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..89c75e9 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,575 @@ + + +
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+ diff --git a/Exp6-1/Exp6-1.runs/impl_1/vivado.jou b/Exp6-1/Exp6-1.runs/impl_1/vivado.jou new file mode 100644 index 0000000..993e123 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 11:42:45 2024 +# Process ID: 26148 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1 +# Command line: vivado.exe -log counter_10.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source counter_10.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source counter_10.tcl -notrace diff --git a/Exp6-1/Exp6-1.runs/impl_1/vivado.pb b/Exp6-1/Exp6-1.runs/impl_1/vivado.pb new file mode 100644 index 0000000..be368a8 Binary files /dev/null and b/Exp6-1/Exp6-1.runs/impl_1/vivado.pb differ diff --git a/Exp6-1/Exp6-1.runs/impl_1/write_bitstream.pb b/Exp6-1/Exp6-1.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..dd074b8 Binary files /dev/null and b/Exp6-1/Exp6-1.runs/impl_1/write_bitstream.pb differ diff --git a/Exp6-1/Exp6-1.runs/synth_1/.Xil/counter_10_propImpl.xdc b/Exp6-1/Exp6-1.runs/synth_1/.Xil/counter_10_propImpl.xdc new file mode 100644 index 0000000..09870c0 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/synth_1/.Xil/counter_10_propImpl.xdc @@ -0,0 +1,29 @@ +set_property SRC_FILE_INFO {cfile:F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.srcs/constrs_1/new/counter_19.xdc rfile:../../../Exp6-1.srcs/constrs_1/new/counter_19.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P5 [get_ports {din[3]}] +set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P4 [get_ports {din[2]}] +set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P3 [get_ports {din[1]}] +set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P2 [get_ports {din[0]}] +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F6 [get_ports {qout[3]}] +set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G4 [get_ports {qout[2]}] +set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G3 [get_ports {qout[1]}] +set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J4 [get_ports {qout[0]}] +set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P17 [get_ports clk] +set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R1 [get_ports clrn] +set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN N4 [get_ports enp] +set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN M4 [get_ports ent] +set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R2 [get_ports ldn] +set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN K2 [get_ports rco] diff --git a/Exp6-1/Exp6-1.runs/synth_1/counter_10.dcp b/Exp6-1/Exp6-1.runs/synth_1/counter_10.dcp new file mode 100644 index 0000000..04d9c18 Binary files /dev/null and b/Exp6-1/Exp6-1.runs/synth_1/counter_10.dcp differ diff --git a/Exp6-1/Exp6-1.runs/synth_1/counter_10.tcl b/Exp6-1/Exp6-1.runs/synth_1/counter_10.tcl new file mode 100644 index 0000000..33d64e8 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/synth_1/counter_10.tcl @@ -0,0 +1,56 @@ +# +# Synthesis run script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param synth.incrementalSynthesisCache C:/Users/Launchcore/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-57964-W10-20240912132/incrSyn +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 +create_project -in_memory -part xc7a35tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.cache/wt [current_project] +set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.srcs/sources_1/new/counter_10.v +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.srcs/constrs_1/new/counter_19.xdc +set_property used_in_implementation false [get_files F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.srcs/constrs_1/new/counter_19.xdc] + +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top counter_10 -part xc7a35tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef counter_10.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file counter_10_utilization_synth.rpt -pb counter_10_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/Exp6-1/Exp6-1.runs/synth_1/counter_10.vds b/Exp6-1/Exp6-1.runs/synth_1/counter_10.vds new file mode 100644 index 0000000..55fef0e --- /dev/null +++ b/Exp6-1/Exp6-1.runs/synth_1/counter_10.vds @@ -0,0 +1,280 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 11:42:04 2024 +# Process ID: 48080 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/synth_1 +# Command line: vivado.exe -log counter_10.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source counter_10.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/synth_1/counter_10.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source counter_10.tcl -notrace +Command: synth_design -top counter_10 -part xc7a35tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 59584 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 410.250 ; gain = 97.734 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'counter_10' [F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.srcs/sources_1/new/counter_10.v:23] + Parameter din_width bound to: 4 - type: integer + Parameter qout_width bound to: 4 - type: integer + Parameter counter_size bound to: 10 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'counter_10' (1#1) [F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.srcs/sources_1/new/counter_10.v:23] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 464.277 ; gain = 151.762 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 464.277 ; gain = 151.762 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 464.277 ; gain = 151.762 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.srcs/constrs_1/new/counter_19.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.srcs/constrs_1/new/counter_19.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.srcs/constrs_1/new/counter_19.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/counter_10_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/counter_10_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 745.055 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 745.055 ; gain = 432.539 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 745.055 ; gain = 432.539 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 745.055 ; gain = 432.539 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 745.055 ; gain = 432.539 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 4 Bit Registers := 1 ++---Muxes : + 2 Input 4 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module counter_10 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 4 Bit Registers := 1 ++---Muxes : + 2 Input 4 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 745.055 ; gain = 432.539 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 782.766 ; gain = 470.250 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 782.766 ; gain = 470.250 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 792.332 ; gain = 479.816 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 792.332 ; gain = 479.816 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 792.332 ; gain = 479.816 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 792.332 ; gain = 479.816 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 792.332 ; gain = 479.816 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 792.332 ; gain = 479.816 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 792.332 ; gain = 479.816 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |BUFG | 1| +|2 |LUT1 | 1| +|3 |LUT3 | 2| +|4 |LUT5 | 2| +|5 |LUT6 | 2| +|6 |FDCE | 4| +|7 |IBUF | 9| +|8 |OBUF | 5| ++------+-----+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 26| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 792.332 ; gain = 479.816 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 792.332 ; gain = 199.039 +Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 792.332 ; gain = 479.816 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 804.652 ; gain = 504.836 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/synth_1/counter_10.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file counter_10_utilization_synth.rpt -pb counter_10_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 804.652 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Thu Dec 12 11:42:37 2024... diff --git a/Exp6-1/Exp6-1.runs/synth_1/counter_10_utilization_synth.pb b/Exp6-1/Exp6-1.runs/synth_1/counter_10_utilization_synth.pb new file mode 100644 index 0000000..fe9cd25 Binary files /dev/null and b/Exp6-1/Exp6-1.runs/synth_1/counter_10_utilization_synth.pb differ diff --git a/Exp6-1/Exp6-1.runs/synth_1/counter_10_utilization_synth.rpt b/Exp6-1/Exp6-1.runs/synth_1/counter_10_utilization_synth.rpt new file mode 100644 index 0000000..740b078 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/synth_1/counter_10_utilization_synth.rpt @@ -0,0 +1,175 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 11:42:37 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file counter_10_utilization_synth.rpt -pb counter_10_utilization_synth.pb +| Design : counter_10 +| Device : 7a35tcsg324-1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 7 | 0 | 20800 | 0.03 | +| LUT as Logic | 7 | 0 | 20800 | 0.03 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 4 | 0 | 41600 | <0.01 | +| Register as Flip Flop | 4 | 0 | 41600 | <0.01 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 4 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 14 | 0 | 210 | 6.67 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| IBUF | 9 | IO | +| OBUF | 5 | IO | +| FDCE | 4 | Flop & Latch | +| LUT6 | 2 | LUT | +| LUT5 | 2 | LUT | +| LUT3 | 2 | LUT | +| LUT1 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp6-1/Exp6-1.runs/synth_1/gen_run.xml b/Exp6-1/Exp6-1.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..52b9fb7 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/synth_1/gen_run.xml @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp6-1/Exp6-1.runs/synth_1/htr.txt b/Exp6-1/Exp6-1.runs/synth_1/htr.txt new file mode 100644 index 0000000..96e5e2a --- /dev/null +++ b/Exp6-1/Exp6-1.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log counter_10.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source counter_10.tcl diff --git a/Exp6-1/Exp6-1.runs/synth_1/vivado.jou b/Exp6-1/Exp6-1.runs/synth_1/vivado.jou new file mode 100644 index 0000000..c5a44f8 --- /dev/null +++ b/Exp6-1/Exp6-1.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 11:42:04 2024 +# Process ID: 48080 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/synth_1 +# Command line: vivado.exe -log counter_10.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source counter_10.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/synth_1/counter_10.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source counter_10.tcl -notrace diff --git a/Exp6-1/Exp6-1.runs/synth_1/vivado.pb b/Exp6-1/Exp6-1.runs/synth_1/vivado.pb new file mode 100644 index 0000000..27da341 Binary files /dev/null and b/Exp6-1/Exp6-1.runs/synth_1/vivado.pb differ diff --git a/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/counter_10_tb.tcl b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/counter_10_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/counter_10_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/counter_10_tb_vlog.prj b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/counter_10_tb_vlog.prj new file mode 100644 index 0000000..36aad30 --- /dev/null +++ b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/counter_10_tb_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp6-1.srcs/sources_1/new/counter_10.v" \ +"../../../../Exp6-1.srcs/sim_1/new/counter_10_tb.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/glbl.v b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/webtalk.jou b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..1cee6a5 --- /dev/null +++ b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 14:36:23 2024 +# Process ID: 50688 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/webtalk_34540.backup.jou b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/webtalk_34540.backup.jou new file mode 100644 index 0000000..f972d80 --- /dev/null +++ b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/webtalk_34540.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 11:31:18 2024 +# Process ID: 34540 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xelab.pb b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..49f3798 Binary files /dev/null and b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/Compile_Options.txt b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..fa48c4f --- /dev/null +++ b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "bebe73b94cff42d7b1c5d8a3c661ada3" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "counter_10_tb_behav" "xil_defaultlib.counter_10_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/TempBreakPointFile.txt b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/obj/xsim_1.c b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..bede11f --- /dev/null +++ b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/obj/xsim_1.c @@ -0,0 +1,114 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_5(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_3(char*, char *); +extern void execute_10(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_9(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[20] = {(funcp)execute_4, (funcp)execute_5, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_3, (funcp)execute_10, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 20; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/counter_10_tb_behav/xsim.reloc", (void **)funcTab, 20); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/counter_10_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/counter_10_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/counter_10_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/counter_10_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/counter_10_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/xsim.mem b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/xsim.mem new file mode 100644 index 0000000..4c6d6a7 Binary files /dev/null and b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xsim.dir/counter_10_tb_behav/xsim.mem differ diff --git a/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xvlog.pb b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..77eba85 Binary files /dev/null and b/Exp6-1/Exp6-1.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Exp6-1/Exp6-1.srcs/constrs_1/new/counter_19.xdc b/Exp6-1/Exp6-1.srcs/constrs_1/new/counter_19.xdc new file mode 100644 index 0000000..04ac297 --- /dev/null +++ b/Exp6-1/Exp6-1.srcs/constrs_1/new/counter_19.xdc @@ -0,0 +1,28 @@ +set_property IOSTANDARD LVCMOS33 [get_ports {din[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {din[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {din[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {din[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {qout[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {qout[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {qout[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {qout[0]}] +set_property PACKAGE_PIN P5 [get_ports {din[3]}] +set_property PACKAGE_PIN P4 [get_ports {din[2]}] +set_property PACKAGE_PIN P3 [get_ports {din[1]}] +set_property PACKAGE_PIN P2 [get_ports {din[0]}] +set_property PACKAGE_PIN F6 [get_ports {qout[3]}] +set_property PACKAGE_PIN G4 [get_ports {qout[2]}] +set_property PACKAGE_PIN G3 [get_ports {qout[1]}] +set_property PACKAGE_PIN J4 [get_ports {qout[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports clrn] +set_property IOSTANDARD LVCMOS33 [get_ports enp] +set_property IOSTANDARD LVCMOS33 [get_ports ent] +set_property IOSTANDARD LVCMOS33 [get_ports ldn] +set_property IOSTANDARD LVCMOS33 [get_ports rco] +set_property PACKAGE_PIN P17 [get_ports clk] +set_property PACKAGE_PIN R1 [get_ports clrn] +set_property PACKAGE_PIN N4 [get_ports enp] +set_property PACKAGE_PIN M4 [get_ports ent] +set_property PACKAGE_PIN R2 [get_ports ldn] +set_property PACKAGE_PIN K2 [get_ports rco] diff --git a/Exp6-1/Exp6-1.srcs/sim_1/new/counter_10_tb.v b/Exp6-1/Exp6-1.srcs/sim_1/new/counter_10_tb.v new file mode 100644 index 0000000..9fbfd87 --- /dev/null +++ b/Exp6-1/Exp6-1.srcs/sim_1/new/counter_10_tb.v @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/01 23:02:08 +// Design Name: +// Module Name: counter_10_tb +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module counter_10_tb; +reg clrn, clk, enp, ldn, ent; +reg [3:0] din; +wire [3:0] qout; +wire rco; +counter_10 dut ( + .clrn(clrn), + .clk(clk), + .enp(enp), + .ent(ent), + .ldn(ldn), + .din(din), + .qout(qout), + .rco(rco) +); +always #5 clk = ~clk; +initial begin + // Initialize inputs + clrn = 1'b1; + clk = 1'b0; + enp = 1'b0; + ent = 1'b1; + ldn = 1'b1; + din = 4'b0000; + // Test async reset + #10 clrn = 1'b0; + #10 clrn = 1'b1; + // Test async preset + #10 ldn = 1'b0; + din = 4'b1001; + #10 ldn = 1'b1; + // Test counting up + #10 enp = 1'b1; + repeat (15) #10; + // Test holding + #10 enp = 1'b0; + repeat (5) #10; + $finish; +end +endmodule diff --git a/Exp6-1/Exp6-1.srcs/sources_1/new/counter_10.v b/Exp6-1/Exp6-1.srcs/sources_1/new/counter_10.v new file mode 100644 index 0000000..d3c631b --- /dev/null +++ b/Exp6-1/Exp6-1.srcs/sources_1/new/counter_10.v @@ -0,0 +1,49 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/01 22:50:46 +// Design Name: +// Module Name: counter_10 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module counter_10 (clrn, clk, enp, ent, ldn, din, qout, rco); + // clrn: Asynchronous clear (active low) + // clk: Clock signal + // ent: Enable counting terminal + // enp: Enable counting parallel + // ldn: Load enable (active low) + // din: Input data + // qout: Current counter value + // rco: Ripple Carry Out + parameter din_width = 'd4; + parameter qout_width = 'd4; + parameter counter_size = 'd10; + input clrn, clk, ent, enp, ldn; + input [din_width - 1 : 0] din; + output [qout_width - 1 : 0] qout; + output rco; + reg [qout_width - 1 : 0] qout; + always @(posedge clk or negedge clrn) begin + if (~clrn) qout <= 0; // Async clear + else if (!ldn) qout <= din; // Async preset initial value + else if (enp && ent == 1) + if (qout == counter_size - 1) qout <= 0; // If maximum clear + else qout <= qout + 1; // Counter ++ + else qout <= qout; // Keep + end + assign rco = (qout == counter_size - 1 && ent) ? 1 : 0; // Output highest bit +endmodule diff --git a/Exp6-1/Exp6-1.srcs/sources_1/new/counter_10_alt.v b/Exp6-1/Exp6-1.srcs/sources_1/new/counter_10_alt.v new file mode 100644 index 0000000..2b3c6e8 --- /dev/null +++ b/Exp6-1/Exp6-1.srcs/sources_1/new/counter_10_alt.v @@ -0,0 +1,33 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/02 11:13:43 +// Design Name: +// Module Name: counter_10_alt +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module counter_10_alt( + input wire clk, + input wire rst, + output reg [3:0] count +); +always @(posedge clk or posedge rst) begin + if (rst) + count <= 4'b0000; + else + count <= count + 1; +end +endmodule diff --git a/Exp6-1/Exp6-1.xpr b/Exp6-1/Exp6-1.xpr new file mode 100644 index 0000000..10c76e3 --- /dev/null +++ b/Exp6-1/Exp6-1.xpr @@ -0,0 +1,159 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp6-1/vivado.jou b/Exp6-1/vivado.jou new file mode 100644 index 0000000..475cb57 --- /dev/null +++ b/Exp6-1/vivado.jou @@ -0,0 +1,48 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 20:01:22 2024 +# Process ID: 14980 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-1 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent13000 F:\Schoolwork\DigitalLogic\Exp6-1\Exp6-1.xpr +# Log file: F:/Schoolwork/DigitalLogic/Exp6-1/vivado.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-1\vivado.jou +#----------------------------------------------------------- +start_gui +open_project F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.xpr +update_compile_order -fileset sources_1 +open_hw +connect_hw_server +open_hw_target +set_property PROGRAM.FILE {F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10.bit} [get_hw_devices xc7a35t_0] +current_hw_device [get_hw_devices xc7a35t_0] +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0] +set_property PROBES.FILE {} [get_hw_devices xc7a35t_0] +set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0] +set_property PROGRAM.FILE {F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10.bit} [get_hw_devices xc7a35t_0] +program_hw_devices [get_hw_devices xc7a35t_0] +refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0] +set_property PROBES.FILE {} [get_hw_devices xc7a35t_0] +set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0] +set_property PROGRAM.FILE {F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10.bit} [get_hw_devices xc7a35t_0] +program_hw_devices [get_hw_devices xc7a35t_0] +refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0] +open_project F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.xpr +current_project Exp6-1 +close_project +update_compile_order -fileset sources_1 +reset_run synth_1 +launch_runs impl_1 -to_step write_bitstream -jobs 10 +wait_on_run impl_1 +open_hw +connect_hw_server +open_hw_target +set_property PROGRAM.FILE {F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/impl_1/slowClock.bit} [get_hw_devices xc7a35t_0] +current_hw_device [get_hw_devices xc7a35t_0] +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0] +set_property PROBES.FILE {} [get_hw_devices xc7a35t_0] +set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0] +set_property PROGRAM.FILE {F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/impl_1/slowClock.bit} [get_hw_devices xc7a35t_0] +program_hw_devices [get_hw_devices xc7a35t_0] +refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0] diff --git a/Exp6-2/Exp6-2.cache/wt/webtalk_pa.xml b/Exp6-2/Exp6-2.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..cd85062 --- /dev/null +++ b/Exp6-2/Exp6-2.cache/wt/webtalk_pa.xml @@ -0,0 +1,78 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp6-2/Exp6-2.hw/hw_1/hw.xml b/Exp6-2/Exp6-2.hw/hw_1/hw.xml new file mode 100644 index 0000000..7c4b3bd --- /dev/null +++ b/Exp6-2/Exp6-2.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/Exp6-2/Exp6-2.ip_user_files/README.txt b/Exp6-2/Exp6-2.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp6-2/Exp6-2.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp6-2/Exp6-2.runs/.jobs/vrs_config_1.xml b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..f792e04 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp6-2/Exp6-2.runs/.jobs/vrs_config_2.xml b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..41ef7bf --- /dev/null +++ b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp6-2/Exp6-2.runs/.jobs/vrs_config_3.xml b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..41ef7bf --- /dev/null +++ b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp6-2/Exp6-2.runs/.jobs/vrs_config_4.xml b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..f792e04 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp6-2/Exp6-2.runs/.jobs/vrs_config_5.xml b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..f792e04 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp6-2/Exp6-2.runs/.jobs/vrs_config_6.xml b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..c4806fc --- /dev/null +++ b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp6-2/Exp6-2.runs/.jobs/vrs_config_7.xml b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..41ef7bf --- /dev/null +++ b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp6-2/Exp6-2.runs/.jobs/vrs_config_8.xml b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..41ef7bf --- /dev/null +++ b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp6-2/Exp6-2.runs/.jobs/vrs_config_9.xml b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..41ef7bf --- /dev/null +++ b/Exp6-2/Exp6-2.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp6-2/Exp6-2.runs/impl_1/gen_run.xml b/Exp6-2/Exp6-2.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..9654c5f --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/gen_run.xml @@ -0,0 +1,106 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp6-2/Exp6-2.runs/impl_1/htr.txt b/Exp6-2/Exp6-2.runs/impl_1/htr.txt new file mode 100644 index 0000000..761ad3f --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log slowClock.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source slowClock.tcl -notrace diff --git a/Exp6-2/Exp6-2.runs/impl_1/init_design.pb b/Exp6-2/Exp6-2.runs/impl_1/init_design.pb new file mode 100644 index 0000000..5710373 Binary files /dev/null and b/Exp6-2/Exp6-2.runs/impl_1/init_design.pb differ diff --git a/Exp6-2/Exp6-2.runs/impl_1/opt_design.pb b/Exp6-2/Exp6-2.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..b4d274e Binary files /dev/null and b/Exp6-2/Exp6-2.runs/impl_1/opt_design.pb differ diff --git a/Exp6-2/Exp6-2.runs/impl_1/place_design.pb b/Exp6-2/Exp6-2.runs/impl_1/place_design.pb new file mode 100644 index 0000000..806940c Binary files /dev/null and b/Exp6-2/Exp6-2.runs/impl_1/place_design.pb differ diff --git a/Exp6-2/Exp6-2.runs/impl_1/route_design.pb b/Exp6-2/Exp6-2.runs/impl_1/route_design.pb new file mode 100644 index 0000000..d15ed4f Binary files /dev/null and b/Exp6-2/Exp6-2.runs/impl_1/route_design.pb differ diff --git a/Exp6-2/Exp6-2.runs/impl_1/route_report_bus_skew_0.rpt b/Exp6-2/Exp6-2.runs/impl_1/route_report_bus_skew_0.rpt new file mode 100644 index 0000000..ef8435a --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/route_report_bus_skew_0.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 20:12:58 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +| Design : slowClock +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock.tcl b/Exp6-2/Exp6-2.runs/impl_1/slowClock.tcl new file mode 100644 index 0000000..7584cb4 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/slowClock.tcl @@ -0,0 +1,170 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param xicom.use_bs_reader 1 + create_project -in_memory -part xc7a35tcsg324-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.cache/wt [current_project] + set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.xpr [current_project] + set_property ip_output_repo F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1/slowClock.dcp + read_xdc F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc + link_design -top slowClock -part xc7a35tcsg324-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force slowClock_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file slowClock_drc_opted.rpt -pb slowClock_drc_opted.pb -rpx slowClock_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force slowClock_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file slowClock_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file slowClock_utilization_placed.rpt -pb slowClock_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file slowClock_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force slowClock_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file slowClock_drc_routed.rpt -pb slowClock_drc_routed.pb -rpx slowClock_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file slowClock_methodology_drc_routed.rpt -pb slowClock_methodology_drc_routed.pb -rpx slowClock_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file slowClock_power_routed.rpt -pb slowClock_power_summary_routed.pb -rpx slowClock_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file slowClock_route_status.rpt -pb slowClock_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file slowClock_timing_summary_routed.rpt -pb slowClock_timing_summary_routed.pb -rpx slowClock_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file slowClock_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file slowClock_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force slowClock_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force slowClock.mmi } + write_bitstream -force slowClock.bit + catch {write_debug_probes -quiet -force slowClock} + catch {file copy -force slowClock.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock.vdi b/Exp6-2/Exp6-2.runs/impl_1/slowClock.vdi new file mode 100644 index 0000000..d2b20c2 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/slowClock.vdi @@ -0,0 +1,448 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 20:12:20 2024 +# Process ID: 14488 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/impl_1 +# Command line: vivado.exe -log slowClock.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source slowClock.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/impl_1/slowClock.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source slowClock.tcl -notrace +Command: link_design -top slowClock -part xc7a35tcsg324-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 25 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 608.359 ; gain = 303.055 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.383 . Memory (MB): peak = 622.270 ; gain = 13.910 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 22b2d50d0 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1177.168 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 22b2d50d0 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1177.168 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 22e647d89 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1177.168 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 22e647d89 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1177.168 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 22e647d89 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1177.168 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 22e647d89 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1177.168 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1177.168 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 22e647d89 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1177.168 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1cb6f9192 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1177.168 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.168 ; gain = 568.809 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1177.168 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/impl_1/slowClock_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file slowClock_drc_opted.rpt -pb slowClock_drc_opted.pb -rpx slowClock_drc_opted.rpx +Command: report_drc -file slowClock_drc_opted.rpt -pb slowClock_drc_opted.pb -rpx slowClock_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/impl_1/slowClock_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1177.168 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11537eee7 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1177.168 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1186.875 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1160462b5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.438 . Memory (MB): peak = 1187.145 ; gain = 9.977 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1aab7bc66 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.461 . Memory (MB): peak = 1187.145 ; gain = 9.977 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1aab7bc66 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.463 . Memory (MB): peak = 1187.145 ; gain = 9.977 +Phase 1 Placer Initialization | Checksum: 1aab7bc66 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.465 . Memory (MB): peak = 1187.145 ; gain = 9.977 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 1bbab23c7 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.823 . Memory (MB): peak = 1187.145 ; gain = 9.977 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1bbab23c7 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.825 . Memory (MB): peak = 1187.145 ; gain = 9.977 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 154a43cce + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.836 . Memory (MB): peak = 1187.145 ; gain = 9.977 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1cc877c4c + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.839 . Memory (MB): peak = 1187.145 ; gain = 9.977 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1cc877c4c + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.840 . Memory (MB): peak = 1187.145 ; gain = 9.977 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1b964ddc4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.905 . Memory (MB): peak = 1187.145 ; gain = 9.977 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1b964ddc4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.911 . Memory (MB): peak = 1187.145 ; gain = 9.977 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1b964ddc4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.912 . Memory (MB): peak = 1187.145 ; gain = 9.977 +Phase 3 Detail Placement | Checksum: 1b964ddc4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.912 . Memory (MB): peak = 1187.145 ; gain = 9.977 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1b964ddc4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.914 . Memory (MB): peak = 1187.145 ; gain = 9.977 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1b964ddc4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.918 . Memory (MB): peak = 1187.145 ; gain = 9.977 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1b964ddc4 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.919 . Memory (MB): peak = 1187.145 ; gain = 9.977 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1ebebb615 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.920 . Memory (MB): peak = 1187.145 ; gain = 9.977 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ebebb615 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.921 . Memory (MB): peak = 1187.145 ; gain = 9.977 +Ending Placer Task | Checksum: 15b8c651e + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.923 . Memory (MB): peak = 1187.145 ; gain = 9.977 +INFO: [Common 17-83] Releasing license: Implementation +43 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1187.145 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/impl_1/slowClock_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file slowClock_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1189.641 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file slowClock_utilization_placed.rpt -pb slowClock_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1189.641 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file slowClock_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1189.641 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 5d145269 ConstDB: 0 ShapeSum: fe7812b5 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 8b844256 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1307.223 ; gain = 117.582 +Post Restoration Checksum: NetGraph: 6a9b952e NumContArr: 20e8ad28 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 8b844256 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1313.254 ; gain = 123.613 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 8b844256 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1313.254 ; gain = 123.613 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 12685bc94 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1318.059 ; gain = 128.418 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 75fdbc17 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1318.059 ; gain = 128.418 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 19ff504a3 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1318.059 ; gain = 128.418 +Phase 4 Rip-up And Reroute | Checksum: 19ff504a3 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1318.059 ; gain = 128.418 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 19ff504a3 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1318.059 ; gain = 128.418 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 19ff504a3 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1318.059 ; gain = 128.418 +Phase 6 Post Hold Fix | Checksum: 19ff504a3 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1318.059 ; gain = 128.418 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0301363 % + Global Horizontal Routing Utilization = 0.0273295 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 14.7059%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 10.2941%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 19ff504a3 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1318.059 ; gain = 128.418 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 19ff504a3 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1318.824 ; gain = 129.184 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 1658e90b2 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1318.824 ; gain = 129.184 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1318.824 ; gain = 129.184 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1318.824 ; gain = 129.184 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1318.824 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/impl_1/slowClock_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file slowClock_drc_routed.rpt -pb slowClock_drc_routed.pb -rpx slowClock_drc_routed.rpx +Command: report_drc -file slowClock_drc_routed.rpt -pb slowClock_drc_routed.pb -rpx slowClock_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/impl_1/slowClock_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file slowClock_methodology_drc_routed.rpt -pb slowClock_methodology_drc_routed.pb -rpx slowClock_methodology_drc_routed.rpx +Command: report_methodology -file slowClock_methodology_drc_routed.rpt -pb slowClock_methodology_drc_routed.pb -rpx slowClock_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/impl_1/slowClock_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file slowClock_power_routed.rpt -pb slowClock_power_summary_routed.pb -rpx slowClock_power_routed.rpx +Command: report_power -file slowClock_power_routed.rpt -pb slowClock_power_summary_routed.pb -rpx slowClock_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +68 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file slowClock_route_status.rpt -pb slowClock_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file slowClock_timing_summary_routed.rpt -pb slowClock_timing_summary_routed.pb -rpx slowClock_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file slowClock_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file slowClock_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force slowClock.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./slowClock.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +86 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1769.531 ; gain = 418.285 +INFO: [Common 17-206] Exiting Vivado at Thu Dec 12 20:13:05 2024... diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_clock_utilization_routed.rpt b/Exp6-2/Exp6-2.runs/impl_1/slowClock_clock_utilization_routed.rpt new file mode 100644 index 0000000..9f43953 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/slowClock_clock_utilization_routed.rpt @@ -0,0 +1,145 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 20:12:58 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file slowClock_clock_utilization_routed.rpt +| Design : slowClock +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +--------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X1Y1 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 93 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | IOB_X0Y26 | IOB_X0Y26 | X0Y0 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 93 | 1500 | 35 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 1 | +| Y0 | 0 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | | | | 93 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+-----+ +| | X0 | X1 | ++----+----+-----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 93 | +| Y0 | 0 | 0 | ++----+----+-----+ + + +7. Clock Region Cell Placement per Global Clock: Region X1Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 93 | 0 | 93 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y26 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} +#endgroup diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_control_sets_placed.rpt b/Exp6-2/Exp6-2.runs/impl_1/slowClock_control_sets_placed.rpt new file mode 100644 index 0000000..7c4cd7f --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/slowClock_control_sets_placed.rpt @@ -0,0 +1,65 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 20:12:45 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file slowClock_control_sets_placed.rpt +| Design : slowClock +| Device : xc7a35t +-------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 1 | +| Unused register locations in slices containing registers | 3 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ +| 16+ | 1 | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 93 | 30 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++----------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++----------------+---------------+------------------+------------------+----------------+ +| clk_IBUF_BUFG | | reset_IBUF | 30 | 93 | ++----------------+---------------+------------------+------------------+----------------+ + + diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_drc_opted.pb b/Exp6-2/Exp6-2.runs/impl_1/slowClock_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp6-2/Exp6-2.runs/impl_1/slowClock_drc_opted.pb differ diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_drc_opted.rpt b/Exp6-2/Exp6-2.runs/impl_1/slowClock_drc_opted.rpt new file mode 100644 index 0000000..dc92aa1 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/slowClock_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 20:12:43 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file slowClock_drc_opted.rpt -pb slowClock_drc_opted.pb -rpx slowClock_drc_opted.rpx +| Design : slowClock +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_drc_routed.pb b/Exp6-2/Exp6-2.runs/impl_1/slowClock_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp6-2/Exp6-2.runs/impl_1/slowClock_drc_routed.pb differ diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_drc_routed.rpt b/Exp6-2/Exp6-2.runs/impl_1/slowClock_drc_routed.rpt new file mode 100644 index 0000000..69b3f28 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/slowClock_drc_routed.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 20:12:57 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file slowClock_drc_routed.rpt -pb slowClock_drc_routed.pb -rpx slowClock_drc_routed.rpx +| Design : slowClock +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_io_placed.rpt b/Exp6-2/Exp6-2.runs/impl_1/slowClock_io_placed.rpt new file mode 100644 index 0000000..1a32616 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/slowClock_io_placed.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 20:12:45 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_io -file slowClock_io_placed.rpt +| Design : slowClock +| Device : xc7a35t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2013-12-19 +| Package Pin Delay Version : VERS. 2.0 2013-12-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 6 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | clk_1Hz | High Range | IO_L20N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | clk_48Hz | High Range | IO_L21N_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | clk_190Hz | High Range | IO_L22P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J4 | clk_12Hz | High Range | IO_L21P_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N4 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| P3 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P4 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P5 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P17 | clk | High Range | IO_L12P_T1_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | reset | High Range | IO_L17P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| R2 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_methodology_drc_routed.pb b/Exp6-2/Exp6-2.runs/impl_1/slowClock_methodology_drc_routed.pb new file mode 100644 index 0000000..44a0680 Binary files /dev/null and b/Exp6-2/Exp6-2.runs/impl_1/slowClock_methodology_drc_routed.pb differ diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_methodology_drc_routed.rpt b/Exp6-2/Exp6-2.runs/impl_1/slowClock_methodology_drc_routed.rpt new file mode 100644 index 0000000..bc7d961 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/slowClock_methodology_drc_routed.rpt @@ -0,0 +1,500 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 20:12:57 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_methodology -file slowClock_methodology_drc_routed.rpt -pb slowClock_methodology_drc_routed.pb -rpx slowClock_methodology_drc_routed.rpx +| Design : slowClock +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +----------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 93 ++-----------+----------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------+------------+ +| TIMING-17 | Warning | Non-clocked sequential cell | 93 | ++-----------+----------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Warning +Non-clocked sequential cell +The clock pin clk_12Hz_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Warning +Non-clocked sequential cell +The clock pin clk_190Hz_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Warning +Non-clocked sequential cell +The clock pin clk_1Hz_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Warning +Non-clocked sequential cell +The clock pin clk_48Hz_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#5 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#6 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#7 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#8 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#9 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#10 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#11 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#12 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#13 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#14 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#15 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#16 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#17 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#18 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#19 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#20 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#21 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#22 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#23 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#24 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#25 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#26 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#27 Warning +Non-clocked sequential cell +The clock pin counter12Hz_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#28 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#29 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#30 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#31 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#32 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#33 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#34 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#35 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#36 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#37 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#38 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#39 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#40 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#41 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#42 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#43 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#44 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#45 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#46 Warning +Non-clocked sequential cell +The clock pin counter190Hz_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#47 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#48 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#49 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#50 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#51 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#52 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#53 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#54 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#55 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#56 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#57 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#58 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#59 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#60 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#61 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#62 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#63 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#64 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#65 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#66 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#67 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#68 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#69 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#70 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#71 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#72 Warning +Non-clocked sequential cell +The clock pin counter1Hz_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#73 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#74 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#75 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#76 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#77 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#78 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#79 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#80 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#81 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#82 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#83 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#84 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#85 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#86 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#87 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#88 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#89 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#90 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#91 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#92 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#93 Warning +Non-clocked sequential cell +The clock pin counter48Hz_reg[9]/C is not reached by a timing clock +Related violations: + + diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_opt.dcp b/Exp6-2/Exp6-2.runs/impl_1/slowClock_opt.dcp new file mode 100644 index 0000000..9a4b901 Binary files /dev/null and b/Exp6-2/Exp6-2.runs/impl_1/slowClock_opt.dcp differ diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_placed.dcp b/Exp6-2/Exp6-2.runs/impl_1/slowClock_placed.dcp new file mode 100644 index 0000000..7e2580d Binary files /dev/null and b/Exp6-2/Exp6-2.runs/impl_1/slowClock_placed.dcp differ diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_power_routed.rpt b/Exp6-2/Exp6-2.runs/impl_1/slowClock_power_routed.rpt new file mode 100644 index 0000000..301da34 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/slowClock_power_routed.rpt @@ -0,0 +1,144 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 20:12:57 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_power -file slowClock_power_routed.rpt -pb slowClock_power_summary_routed.pb -rpx slowClock_power_routed.rpx +| Design : slowClock +| Device : xc7a35tcsg324-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 1.159 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 1.088 | +| Device Static (W) | 0.071 | +| Effective TJA (C/W) | 4.8 | +| Max Ambient (C) | 79.5 | +| Junction Temperature (C) | 30.5 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.540 | 235 | --- | --- | +| LUT as Logic | 0.439 | 90 | 20800 | 0.43 | +| CARRY4 | 0.053 | 23 | 8150 | 0.28 | +| Register | 0.042 | 93 | 41600 | 0.22 | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| Others | 0.000 | 2 | --- | --- | +| Signals | 0.544 | 224 | --- | --- | +| I/O | 0.004 | 6 | 210 | 2.86 | +| Static Power | 0.071 | | | | +| Total | 1.159 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 1.100 | 1.088 | 0.012 | +| Vccaux | 1.800 | 0.013 | 0.000 | 0.013 | +| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.8 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++-----------+-----------+ +| Name | Power (W) | ++-----------+-----------+ +| slowClock | 1.088 | ++-----------+-----------+ + + diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_power_summary_routed.pb b/Exp6-2/Exp6-2.runs/impl_1/slowClock_power_summary_routed.pb new file mode 100644 index 0000000..8c0ff42 Binary files /dev/null and b/Exp6-2/Exp6-2.runs/impl_1/slowClock_power_summary_routed.pb differ diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_route_status.pb b/Exp6-2/Exp6-2.runs/impl_1/slowClock_route_status.pb new file mode 100644 index 0000000..9c6e654 Binary files /dev/null and b/Exp6-2/Exp6-2.runs/impl_1/slowClock_route_status.pb differ diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_route_status.rpt b/Exp6-2/Exp6-2.runs/impl_1/slowClock_route_status.rpt new file mode 100644 index 0000000..fa58de0 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/slowClock_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 324 : + # of nets not needing routing.......... : 98 : + # of internally routed nets........ : 98 : + # of routable nets..................... : 226 : + # of fully routed nets............. : 226 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_routed.dcp b/Exp6-2/Exp6-2.runs/impl_1/slowClock_routed.dcp new file mode 100644 index 0000000..8e06b0a Binary files /dev/null and b/Exp6-2/Exp6-2.runs/impl_1/slowClock_routed.dcp differ diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_timing_summary_routed.pb b/Exp6-2/Exp6-2.runs/impl_1/slowClock_timing_summary_routed.pb new file mode 100644 index 0000000..4526e93 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/slowClock_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_timing_summary_routed.rpt b/Exp6-2/Exp6-2.runs/impl_1/slowClock_timing_summary_routed.rpt new file mode 100644 index 0000000..70cacb5 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/slowClock_timing_summary_routed.rpt @@ -0,0 +1,173 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 20:12:57 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file slowClock_timing_summary_routed.rpt -pb slowClock_timing_summary_routed.pb -rpx slowClock_timing_summary_routed.rpx -warn_on_violation +| Design : slowClock +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 93 register/latch pins with no clock driven by root clock pin: clk (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 186 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There is 1 input port with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 4 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_utilization_placed.pb b/Exp6-2/Exp6-2.runs/impl_1/slowClock_utilization_placed.pb new file mode 100644 index 0000000..63a4ef3 Binary files /dev/null and b/Exp6-2/Exp6-2.runs/impl_1/slowClock_utilization_placed.pb differ diff --git a/Exp6-2/Exp6-2.runs/impl_1/slowClock_utilization_placed.rpt b/Exp6-2/Exp6-2.runs/impl_1/slowClock_utilization_placed.rpt new file mode 100644 index 0000000..9e6a581 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/slowClock_utilization_placed.rpt @@ -0,0 +1,205 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 20:12:45 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file slowClock_utilization_placed.rpt -pb slowClock_utilization_placed.pb +| Design : slowClock +| Device : 7a35tcsg324-1 +| Design State : Fully Placed +--------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 90 | 0 | 20800 | 0.43 | +| LUT as Logic | 90 | 0 | 20800 | 0.43 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 93 | 0 | 41600 | 0.22 | +| Register as Flip Flop | 93 | 0 | 41600 | 0.22 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 93 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 52 | 0 | 8150 | 0.64 | +| SLICEL | 41 | 0 | | | +| SLICEM | 11 | 0 | | | +| LUT as Logic | 90 | 0 | 20800 | 0.43 | +| using O5 output only | 0 | | | | +| using O6 output only | 64 | | | | +| using O5 and O6 | 26 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 68 | 0 | 20800 | 0.33 | +| fully used LUT-FF pairs | 24 | | | | +| LUT-FF pairs with one unused LUT output | 43 | | | | +| LUT-FF pairs with one unused Flip Flop | 44 | | | | +| Unique Control Sets | 1 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 6 | 6 | 210 | 2.86 | +| IOB Master Pads | 4 | | | | +| IOB Slave Pads | 2 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDCE | 93 | Flop & Latch | +| LUT2 | 49 | LUT | +| LUT6 | 44 | LUT | +| CARRY4 | 23 | CarryLogic | +| LUT4 | 17 | LUT | +| OBUF | 4 | IO | +| LUT1 | 3 | LUT | +| LUT5 | 2 | LUT | +| IBUF | 2 | IO | +| LUT3 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp6-2/Exp6-2.runs/impl_1/usage_statistics_webtalk.xml b/Exp6-2/Exp6-2.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..8e92a09 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,616 @@ + + +
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+ diff --git a/Exp6-2/Exp6-2.runs/impl_1/vivado.jou b/Exp6-2/Exp6-2.runs/impl_1/vivado.jou new file mode 100644 index 0000000..d71641d --- /dev/null +++ b/Exp6-2/Exp6-2.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 20:12:20 2024 +# Process ID: 14488 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/impl_1 +# Command line: vivado.exe -log slowClock.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source slowClock.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/impl_1/slowClock.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source slowClock.tcl -notrace diff --git a/Exp6-2/Exp6-2.runs/impl_1/vivado.pb b/Exp6-2/Exp6-2.runs/impl_1/vivado.pb new file mode 100644 index 0000000..cfa1945 Binary files /dev/null and b/Exp6-2/Exp6-2.runs/impl_1/vivado.pb differ diff --git a/Exp6-2/Exp6-2.runs/impl_1/write_bitstream.pb b/Exp6-2/Exp6-2.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..09ec7b5 Binary files /dev/null and b/Exp6-2/Exp6-2.runs/impl_1/write_bitstream.pb differ diff --git a/Exp6-2/Exp6-2.runs/synth_1/.Xil/slowClock_propImpl.xdc b/Exp6-2/Exp6-2.runs/synth_1/.Xil/slowClock_propImpl.xdc new file mode 100644 index 0000000..dab8c3c --- /dev/null +++ b/Exp6-2/Exp6-2.runs/synth_1/.Xil/slowClock_propImpl.xdc @@ -0,0 +1,13 @@ +set_property SRC_FILE_INFO {cfile:F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc rfile:../../../Exp6-2.srcs/constrs_1/new/slowClock.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P17 [get_ports clk] +set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R1 [get_ports reset] +set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G3 [get_ports clk_1Hz] +set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J4 [get_ports clk_12Hz] +set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN H4 [get_ports clk_48Hz] +set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J3 [get_ports clk_190Hz] diff --git a/Exp6-2/Exp6-2.runs/synth_1/gen_run.xml b/Exp6-2/Exp6-2.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..4d2b221 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/synth_1/gen_run.xml @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp6-2/Exp6-2.runs/synth_1/htr.txt b/Exp6-2/Exp6-2.runs/synth_1/htr.txt new file mode 100644 index 0000000..892a763 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log slowClock.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source slowClock.tcl diff --git a/Exp6-2/Exp6-2.runs/synth_1/slowClock.dcp b/Exp6-2/Exp6-2.runs/synth_1/slowClock.dcp new file mode 100644 index 0000000..2ea02cc Binary files /dev/null and b/Exp6-2/Exp6-2.runs/synth_1/slowClock.dcp differ diff --git a/Exp6-2/Exp6-2.runs/synth_1/slowClock.tcl b/Exp6-2/Exp6-2.runs/synth_1/slowClock.tcl new file mode 100644 index 0000000..6cbc6ab --- /dev/null +++ b/Exp6-2/Exp6-2.runs/synth_1/slowClock.tcl @@ -0,0 +1,54 @@ +# +# Synthesis run script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param xicom.use_bs_reader 1 +create_project -in_memory -part xc7a35tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.cache/wt [current_project] +set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/sources_1/new/slowClock.v +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc +set_property used_in_implementation false [get_files F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc] + +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top slowClock -part xc7a35tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef slowClock.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file slowClock_utilization_synth.rpt -pb slowClock_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/Exp6-2/Exp6-2.runs/synth_1/slowClock.vds b/Exp6-2/Exp6-2.runs/synth_1/slowClock.vds new file mode 100644 index 0000000..c2c8328 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/synth_1/slowClock.vds @@ -0,0 +1,317 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 20:11:37 2024 +# Process ID: 23000 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1 +# Command line: vivado.exe -log slowClock.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source slowClock.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1/slowClock.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source slowClock.tcl -notrace +Command: synth_design -top slowClock -part xc7a35tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 21660 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 409.984 ; gain = 97.137 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'slowClock' [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/sources_1/new/slowClock.v:23] + Parameter sys_clk bound to: 100000000 - type: integer + Parameter clk_out1 bound to: 1 - type: integer + Parameter clk_out12 bound to: 12 - type: integer + Parameter clk_out48 bound to: 48 - type: integer + Parameter clk_out190 bound to: 190 - type: integer + Parameter max1 bound to: 49999999 - type: integer + Parameter max12 bound to: 4166665 - type: integer + Parameter max48 bound to: 1041665 - type: integer + Parameter max190 bound to: 263156 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'slowClock' (1#1) [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/sources_1/new/slowClock.v:23] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 464.465 ; gain = 151.617 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 464.465 ; gain = 151.617 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 464.465 ; gain = 151.617 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/slowClock_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/slowClock_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 789.797 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5545] ROM "clk_1Hz" won't be mapped to RAM because address size (26) is larger than maximum supported(25) +INFO: [Synth 8-5546] ROM "clk_12Hz" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "clk_48Hz" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "clk_190Hz" won't be mapped to RAM because it is too sparse +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 26 Bit Adders := 1 + 2 Input 23 Bit Adders := 1 + 2 Input 21 Bit Adders := 1 + 2 Input 19 Bit Adders := 1 ++---Registers : + 26 Bit Registers := 1 + 23 Bit Registers := 1 + 21 Bit Registers := 1 + 19 Bit Registers := 1 + 1 Bit Registers := 4 ++---Muxes : + 2 Input 26 Bit Muxes := 1 + 2 Input 23 Bit Muxes := 1 + 2 Input 21 Bit Muxes := 1 + 2 Input 19 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 4 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module slowClock +Detailed RTL Component Info : ++---Adders : + 2 Input 26 Bit Adders := 1 + 2 Input 23 Bit Adders := 1 + 2 Input 21 Bit Adders := 1 + 2 Input 19 Bit Adders := 1 ++---Registers : + 26 Bit Registers := 1 + 23 Bit Registers := 1 + 21 Bit Registers := 1 + 19 Bit Registers := 1 + 1 Bit Registers := 4 ++---Muxes : + 2 Input 26 Bit Muxes := 1 + 2 Input 23 Bit Muxes := 1 + 2 Input 21 Bit Muxes := 1 + 2 Input 19 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 4 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-5545] ROM "clk_1Hz" won't be mapped to RAM because address size (26) is larger than maximum supported(25) +INFO: [Synth 8-5546] ROM "clk_12Hz" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "clk_48Hz" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "clk_190Hz" won't be mapped to RAM because it is too sparse +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 789.797 ; gain = 476.949 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 789.797 ; gain = 476.949 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 789.797 ; gain = 476.949 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 797.371 ; gain = 484.523 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 23| +|3 |LUT1 | 3| +|4 |LUT2 | 49| +|5 |LUT3 | 1| +|6 |LUT4 | 17| +|7 |LUT5 | 2| +|8 |LUT6 | 44| +|9 |FDCE | 93| +|10 |IBUF | 2| +|11 |OBUF | 4| ++------+-------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 239| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 797.371 ; gain = 159.191 +Synthesis Optimization Complete : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 25 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 805.500 ; gain = 505.727 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1/slowClock.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file slowClock_utilization_synth.rpt -pb slowClock_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 805.500 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Thu Dec 12 20:12:13 2024... diff --git a/Exp6-2/Exp6-2.runs/synth_1/slowClock_utilization_synth.pb b/Exp6-2/Exp6-2.runs/synth_1/slowClock_utilization_synth.pb new file mode 100644 index 0000000..63a4ef3 Binary files /dev/null and b/Exp6-2/Exp6-2.runs/synth_1/slowClock_utilization_synth.pb differ diff --git a/Exp6-2/Exp6-2.runs/synth_1/slowClock_utilization_synth.rpt b/Exp6-2/Exp6-2.runs/synth_1/slowClock_utilization_synth.rpt new file mode 100644 index 0000000..f0bd185 --- /dev/null +++ b/Exp6-2/Exp6-2.runs/synth_1/slowClock_utilization_synth.rpt @@ -0,0 +1,178 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 12 20:12:13 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file slowClock_utilization_synth.rpt -pb slowClock_utilization_synth.pb +| Design : slowClock +| Device : 7a35tcsg324-1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 90 | 0 | 20800 | 0.43 | +| LUT as Logic | 90 | 0 | 20800 | 0.43 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 93 | 0 | 41600 | 0.22 | +| Register as Flip Flop | 93 | 0 | 41600 | 0.22 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 93 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 6 | 0 | 210 | 2.86 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDCE | 93 | Flop & Latch | +| LUT2 | 49 | LUT | +| LUT6 | 44 | LUT | +| CARRY4 | 23 | CarryLogic | +| LUT4 | 17 | LUT | +| OBUF | 4 | IO | +| LUT1 | 3 | LUT | +| LUT5 | 2 | LUT | +| IBUF | 2 | IO | +| LUT3 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp6-2/Exp6-2.runs/synth_1/vivado.jou b/Exp6-2/Exp6-2.runs/synth_1/vivado.jou new file mode 100644 index 0000000..3ba613f --- /dev/null +++ b/Exp6-2/Exp6-2.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 20:11:37 2024 +# Process ID: 23000 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1 +# Command line: vivado.exe -log slowClock.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source slowClock.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1/slowClock.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source slowClock.tcl -notrace diff --git a/Exp6-2/Exp6-2.runs/synth_1/vivado.pb b/Exp6-2/Exp6-2.runs/synth_1/vivado.pb new file mode 100644 index 0000000..a98f173 Binary files /dev/null and b/Exp6-2/Exp6-2.runs/synth_1/vivado.pb differ diff --git a/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/glbl.v b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/tb_slowClock.tcl b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/tb_slowClock.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/tb_slowClock.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/tb_slowClock_vlog.prj b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/tb_slowClock_vlog.prj new file mode 100644 index 0000000..c8908d8 --- /dev/null +++ b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/tb_slowClock_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp6-2.srcs/sources_1/new/slowClock.v" \ +"../../../../Exp6-2.srcs/sim_1/new/tb_slowClock.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk.jou b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..9183ddf --- /dev/null +++ b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 11:34:13 2024 +# Process ID: 70688 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk_11576.backup.jou b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk_11576.backup.jou new file mode 100644 index 0000000..10907a9 --- /dev/null +++ b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk_11576.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Dec 4 22:56:01 2024 +# Process ID: 11576 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk_30300.backup.jou b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk_30300.backup.jou new file mode 100644 index 0000000..3072f62 --- /dev/null +++ b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk_30300.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 5 10:20:54 2024 +# Process ID: 30300 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk_37912.backup.jou b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk_37912.backup.jou new file mode 100644 index 0000000..929a80c --- /dev/null +++ b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk_37912.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 11:33:54 2024 +# Process ID: 37912 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xelab.pb b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..ae00f72 Binary files /dev/null and b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/Compile_Options.txt b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/Compile_Options.txt new file mode 100644 index 0000000..469813c --- /dev/null +++ b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "4300d764479b496ebf4784ba09aabf1f" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_slowClock_behav" "xil_defaultlib.tb_slowClock" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/TempBreakPointFile.txt b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/obj/xsim_1.c b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/obj/xsim_1.c new file mode 100644 index 0000000..bfd02d7 --- /dev/null +++ b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/obj/xsim_1.c @@ -0,0 +1,113 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_3(char*, char *); +extern void execute_8(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[19] = {(funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_3, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 19; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/tb_slowClock_behav/xsim.reloc", (void **)funcTab, 19); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/tb_slowClock_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_slowClock_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/tb_slowClock_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/tb_slowClock_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/tb_slowClock_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..d9b79fe --- /dev/null +++ b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Thu Dec 12 14:36:26 2024" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.1 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2188600" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "78ec1a93-fd1a-4b14-8c4b-87f04256706b" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "4300d764479b496ebf4784ba09aabf1f" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "10" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "13th Gen Intel(R) Core(TM) i7-13700H" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2918 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "1" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.08_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6672_KB" -context "xsim\\usage" +webtalk_transmit -clientid 2415603722 -regid "" -xml F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/usage_statistics_ext_xsim.xml -html F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/usage_statistics_ext_xsim.html -wdm F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/xsim.mem b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/xsim.mem new file mode 100644 index 0000000..347768b Binary files /dev/null and b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xsim.dir/tb_slowClock_behav/xsim.mem differ diff --git a/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xvlog.pb b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..ab6689f Binary files /dev/null and b/Exp6-2/Exp6-2.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc b/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc new file mode 100644 index 0000000..6a57322 --- /dev/null +++ b/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc @@ -0,0 +1,13 @@ +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports clk_1Hz] +set_property IOSTANDARD LVCMOS33 [get_ports clk_12Hz] +set_property IOSTANDARD LVCMOS33 [get_ports clk_48Hz] +set_property IOSTANDARD LVCMOS33 [get_ports clk_190Hz] +set_property IOSTANDARD LVCMOS33 [get_ports reset] +set_property PACKAGE_PIN P17 [get_ports clk] +set_property PACKAGE_PIN R1 [get_ports reset] +set_property PACKAGE_PIN G3 [get_ports clk_1Hz] +set_property PACKAGE_PIN J4 [get_ports clk_12Hz] +set_property PACKAGE_PIN H4 [get_ports clk_48Hz] +set_property PACKAGE_PIN J3 [get_ports clk_190Hz] + diff --git a/Exp6-2/Exp6-2.srcs/sim_1/new/tb_slowClock.v b/Exp6-2/Exp6-2.srcs/sim_1/new/tb_slowClock.v new file mode 100644 index 0000000..97215d5 --- /dev/null +++ b/Exp6-2/Exp6-2.srcs/sim_1/new/tb_slowClock.v @@ -0,0 +1,51 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/04 22:55:01 +// Design Name: +// Module Name: tb_slowClock +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_slowClock; + reg clk; + reg reset; + wire clk_1Hz; + wire clk_12Hz; + wire clk_48Hz; + wire clk_190Hz; + slowClock uut ( + .clk(clk), + .reset(reset), + .clk_1Hz(clk_1Hz), + .clk_12Hz(clk_12Hz), + .clk_48Hz(clk_48Hz), + .clk_190Hz(clk_190Hz) + ); + initial begin + clk = 0; + forever #1 clk = ~clk; + end + initial begin + reset = 1; + #20; + reset = 0; + end + initial begin + #1000000000; + $finish; + end +endmodule diff --git a/Exp6-2/Exp6-2.srcs/sources_1/new/slowClock.v b/Exp6-2/Exp6-2.srcs/sources_1/new/slowClock.v new file mode 100644 index 0000000..ffc79f5 --- /dev/null +++ b/Exp6-2/Exp6-2.srcs/sources_1/new/slowClock.v @@ -0,0 +1,94 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/04 22:53:45 +// Design Name: +// Module Name: slowClock +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module slowClock( + input clk, + input reset, + output reg clk_1Hz, + output reg clk_12Hz, + output reg clk_48Hz, + output reg clk_190Hz +); + +parameter sys_clk = 100_000_000; // 100 MHz +parameter clk_out1 = 1; +parameter clk_out12 = 12; +parameter clk_out48 = 48; +parameter clk_out190 = 190; + +parameter max1 = sys_clk / (2 * clk_out1) - 1; +parameter max12 = sys_clk / (2 * clk_out12) - 1; +parameter max48 = sys_clk / (2 * clk_out48) - 1; +parameter max190 = sys_clk / (2 * clk_out190) - 1; + +reg [25:0] counter1Hz; +reg [22:0] counter12Hz; +reg [20:0] counter48Hz; +reg [18:0] counter190Hz; + +always @(posedge clk or posedge reset) begin + if (reset) begin + counter1Hz <= 0; + clk_1Hz <= 0; + counter12Hz <= 0; + clk_12Hz <= 0; + counter48Hz <= 0; + clk_48Hz <= 0; + counter190Hz <= 0; + clk_190Hz <= 0; + end + else begin + // 1 Hz + if (counter1Hz == max1) begin + counter1Hz <= 0; + clk_1Hz <= ~clk_1Hz; + end + else begin + counter1Hz <= counter1Hz + 1; + end + // 12 Hz + if (counter12Hz == max12) begin + counter12Hz <= 0; + clk_12Hz <= ~clk_12Hz; + end + else begin + counter12Hz <= counter12Hz + 1; + end + // 48 Hz + if (counter48Hz == max48) begin + counter48Hz <= 0; + clk_48Hz <= ~clk_48Hz; + end + else begin + counter48Hz <= counter48Hz + 1; + end + // 190 Hz + if (counter190Hz == max190) begin + counter190Hz <= 0; + clk_190Hz <= ~clk_190Hz; + end + else begin + counter190Hz <= counter190Hz + 1; + end + end +end +endmodule diff --git a/Exp6-2/Exp6-2.xpr b/Exp6-2/Exp6-2.xpr new file mode 100644 index 0000000..22030ea --- /dev/null +++ b/Exp6-2/Exp6-2.xpr @@ -0,0 +1,151 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp6-2/vivado.jou b/Exp6-2/vivado.jou new file mode 100644 index 0000000..d28ac44 --- /dev/null +++ b/Exp6-2/vivado.jou @@ -0,0 +1,14 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 5 12:41:53 2024 +# Process ID: 26256 +# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent6072 F:\Schoolwork\DigitalLogic\Exp6-2\Exp6-2.xpr +# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/vivado.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2\vivado.jou +#----------------------------------------------------------- +start_gui +open_project F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.xpr +update_compile_order -fileset sources_1 diff --git a/Exp7/Exp7.cache/wt/webtalk_pa.xml b/Exp7/Exp7.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..a860a51 --- /dev/null +++ b/Exp7/Exp7.cache/wt/webtalk_pa.xml @@ -0,0 +1,97 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp7/Exp7.hw/hw_1/hw.xml b/Exp7/Exp7.hw/hw_1/hw.xml new file mode 100644 index 0000000..387dc2f --- /dev/null +++ b/Exp7/Exp7.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/Exp7/Exp7.ip_user_files/README.txt b/Exp7/Exp7.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp7/Exp7.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp7/Exp7.runs/.jobs/vrs_config_1.xml b/Exp7/Exp7.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..a52a348 --- /dev/null +++ b/Exp7/Exp7.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp7/Exp7.runs/.jobs/vrs_config_2.xml b/Exp7/Exp7.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..a52a348 --- /dev/null +++ b/Exp7/Exp7.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp7/Exp7.runs/.jobs/vrs_config_3.xml b/Exp7/Exp7.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..a52a348 --- /dev/null +++ b/Exp7/Exp7.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp7/Exp7.runs/.jobs/vrs_config_4.xml b/Exp7/Exp7.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..a52a348 --- /dev/null +++ b/Exp7/Exp7.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp7/Exp7.runs/.jobs/vrs_config_5.xml b/Exp7/Exp7.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..a52a348 --- /dev/null +++ b/Exp7/Exp7.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp7/Exp7.runs/.jobs/vrs_config_6.xml b/Exp7/Exp7.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..dc57a5e --- /dev/null +++ b/Exp7/Exp7.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp7/Exp7.runs/.jobs/vrs_config_7.xml b/Exp7/Exp7.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..dc57a5e --- /dev/null +++ b/Exp7/Exp7.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp7/Exp7.runs/.jobs/vrs_config_8.xml b/Exp7/Exp7.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..dc57a5e --- /dev/null +++ b/Exp7/Exp7.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Exp7/Exp7.runs/impl_1/gen_run.xml b/Exp7/Exp7.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..fea2e6f --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/gen_run.xml @@ -0,0 +1,104 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp7/Exp7.runs/impl_1/htr.txt b/Exp7/Exp7.runs/impl_1/htr.txt new file mode 100644 index 0000000..6b86820 --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log led_chasing.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source led_chasing.tcl -notrace diff --git a/Exp7/Exp7.runs/impl_1/init_design.pb b/Exp7/Exp7.runs/impl_1/init_design.pb new file mode 100644 index 0000000..700b923 Binary files /dev/null and b/Exp7/Exp7.runs/impl_1/init_design.pb differ diff --git a/Exp7/Exp7.runs/impl_1/led_chasing.tcl b/Exp7/Exp7.runs/impl_1/led_chasing.tcl new file mode 100644 index 0000000..3c1e08a --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/led_chasing.tcl @@ -0,0 +1,170 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param xicom.use_bs_reader 1 + create_project -in_memory -part xc7a35tcsg324-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp7/Exp7.cache/wt [current_project] + set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp7/Exp7.xpr [current_project] + set_property ip_output_repo F:/Schoolwork/DigitalLogic/Exp7/Exp7.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/synth_1/led_chasing.dcp + read_xdc F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/constrs_1/new/led_chasing.xdc + link_design -top led_chasing -part xc7a35tcsg324-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force led_chasing_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file led_chasing_drc_opted.rpt -pb led_chasing_drc_opted.pb -rpx led_chasing_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force led_chasing_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file led_chasing_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file led_chasing_utilization_placed.rpt -pb led_chasing_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file led_chasing_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force led_chasing_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file led_chasing_drc_routed.rpt -pb led_chasing_drc_routed.pb -rpx led_chasing_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file led_chasing_methodology_drc_routed.rpt -pb led_chasing_methodology_drc_routed.pb -rpx led_chasing_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file led_chasing_power_routed.rpt -pb led_chasing_power_summary_routed.pb -rpx led_chasing_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file led_chasing_route_status.rpt -pb led_chasing_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file led_chasing_timing_summary_routed.rpt -pb led_chasing_timing_summary_routed.pb -rpx led_chasing_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file led_chasing_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file led_chasing_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force led_chasing_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force led_chasing.mmi } + write_bitstream -force led_chasing.bit + catch {write_debug_probes -quiet -force led_chasing} + catch {file copy -force led_chasing.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/Exp7/Exp7.runs/impl_1/led_chasing.vdi b/Exp7/Exp7.runs/impl_1/led_chasing.vdi new file mode 100644 index 0000000..872d90f --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/led_chasing.vdi @@ -0,0 +1,447 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 5 14:54:57 2024 +# Process ID: 5000 +# Current directory: F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/impl_1 +# Command line: vivado.exe -log led_chasing.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source led_chasing.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/impl_1/led_chasing.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source led_chasing.tcl -notrace +Command: link_design -top led_chasing -part xc7a35tcsg324-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/constrs_1/new/led_chasing.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/constrs_1/new/led_chasing.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 609.758 ; gain = 302.652 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.413 . Memory (MB): peak = 623.668 ; gain = 13.910 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 18a23878a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1165.664 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 18a23878a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1165.664 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 164506296 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1165.664 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 164506296 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1165.664 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 164506296 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1165.664 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 164506296 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1165.664 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1165.664 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 164506296 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1165.664 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1373e1acc + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1165.664 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1165.664 ; gain = 555.906 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1165.664 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/impl_1/led_chasing_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file led_chasing_drc_opted.rpt -pb led_chasing_drc_opted.pb -rpx led_chasing_drc_opted.rpx +Command: report_drc -file led_chasing_drc_opted.rpt -pb led_chasing_drc_opted.pb -rpx led_chasing_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/impl_1/led_chasing_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1165.664 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12c7dc12c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1165.664 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1181.859 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d8eab32b + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.438 . Memory (MB): peak = 1182.141 ; gain = 16.477 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 10ab2faef + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.450 . Memory (MB): peak = 1182.141 ; gain = 16.477 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 10ab2faef + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.451 . Memory (MB): peak = 1182.141 ; gain = 16.477 +Phase 1 Placer Initialization | Checksum: 10ab2faef + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.451 . Memory (MB): peak = 1182.141 ; gain = 16.477 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 152ba7538 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.635 . Memory (MB): peak = 1182.141 ; gain = 16.477 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 152ba7538 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.636 . Memory (MB): peak = 1182.141 ; gain = 16.477 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 284fa30d5 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.645 . Memory (MB): peak = 1182.141 ; gain = 16.477 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1b143bfa4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.649 . Memory (MB): peak = 1182.141 ; gain = 16.477 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1b143bfa4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.649 . Memory (MB): peak = 1182.141 ; gain = 16.477 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 26ca45b64 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.712 . Memory (MB): peak = 1182.141 ; gain = 16.477 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 26ca45b64 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.715 . Memory (MB): peak = 1182.141 ; gain = 16.477 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 26ca45b64 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.716 . Memory (MB): peak = 1182.141 ; gain = 16.477 +Phase 3 Detail Placement | Checksum: 26ca45b64 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.716 . Memory (MB): peak = 1182.141 ; gain = 16.477 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 26ca45b64 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.718 . Memory (MB): peak = 1182.141 ; gain = 16.477 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 26ca45b64 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.720 . Memory (MB): peak = 1182.141 ; gain = 16.477 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 26ca45b64 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.721 . Memory (MB): peak = 1182.141 ; gain = 16.477 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 2034dd7a3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.721 . Memory (MB): peak = 1182.141 ; gain = 16.477 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2034dd7a3 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1182.141 ; gain = 16.477 +Ending Placer Task | Checksum: 123f60845 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.724 . Memory (MB): peak = 1182.141 ; gain = 16.477 +INFO: [Common 17-83] Releasing license: Implementation +43 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1182.141 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/impl_1/led_chasing_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file led_chasing_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1188.375 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file led_chasing_utilization_placed.rpt -pb led_chasing_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1188.375 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file led_chasing_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1188.375 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: eb6f30b3 ConstDB: 0 ShapeSum: 3886d792 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: baaf6ec3 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1301.742 ; gain = 113.367 +Post Restoration Checksum: NetGraph: 41b3ffb2 NumContArr: 78fb6f11 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: baaf6ec3 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1307.770 ; gain = 119.395 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: baaf6ec3 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1307.770 ; gain = 119.395 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 1043f30ef + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1314.625 ; gain = 126.250 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 106b27279 + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1314.625 ; gain = 126.250 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: dd18f52e + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1314.625 ; gain = 126.250 +Phase 4 Rip-up And Reroute | Checksum: dd18f52e + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1314.625 ; gain = 126.250 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: dd18f52e + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1314.625 ; gain = 126.250 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: dd18f52e + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1314.625 ; gain = 126.250 +Phase 6 Post Hold Fix | Checksum: dd18f52e + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1314.625 ; gain = 126.250 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0250339 % + Global Horizontal Routing Utilization = 0.0140552 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 21.6216%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 16.1765%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 10.2941%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: dd18f52e + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1314.625 ; gain = 126.250 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: dd18f52e + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1314.625 ; gain = 126.250 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 6f9cc6ac + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1314.625 ; gain = 126.250 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1314.625 ; gain = 126.250 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1314.625 ; gain = 126.250 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1314.625 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/impl_1/led_chasing_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file led_chasing_drc_routed.rpt -pb led_chasing_drc_routed.pb -rpx led_chasing_drc_routed.rpx +Command: report_drc -file led_chasing_drc_routed.rpt -pb led_chasing_drc_routed.pb -rpx led_chasing_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/impl_1/led_chasing_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file led_chasing_methodology_drc_routed.rpt -pb led_chasing_methodology_drc_routed.pb -rpx led_chasing_methodology_drc_routed.rpx +Command: report_methodology -file led_chasing_methodology_drc_routed.rpt -pb led_chasing_methodology_drc_routed.pb -rpx led_chasing_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/impl_1/led_chasing_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file led_chasing_power_routed.rpt -pb led_chasing_power_summary_routed.pb -rpx led_chasing_power_routed.rpx +Command: report_power -file led_chasing_power_routed.rpt -pb led_chasing_power_summary_routed.pb -rpx led_chasing_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +68 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file led_chasing_route_status.rpt -pb led_chasing_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file led_chasing_timing_summary_routed.rpt -pb led_chasing_timing_summary_routed.pb -rpx led_chasing_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file led_chasing_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file led_chasing_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force led_chasing.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./led_chasing.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +86 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1756.219 ; gain = 411.730 +INFO: [Common 17-206] Exiting Vivado at Thu Dec 5 14:55:45 2024... diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_clock_utilization_routed.rpt b/Exp7/Exp7.runs/impl_1/led_chasing_clock_utilization_routed.rpt new file mode 100644 index 0000000..cfc3604 --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/led_chasing_clock_utilization_routed.rpt @@ -0,0 +1,173 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 5 14:55:36 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file led_chasing_clock_utilization_routed.rpt +| Design : led_chasing +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Local Clock Details +5. Clock Regions: Key Resource Utilization +6. Clock Regions : Global Clock Summary +7. Device Cell Placement Summary for Global Clock g0 +8. Clock Region Cell Placement per Global Clock: Region X1Y0 +9. Clock Region Cell Placement per Global Clock: Region X1Y1 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 2 | 27 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | IOB_X0Y26 | IOB_X0Y26 | X0Y0 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Local Clock Details +---------------------- + ++----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+------------------------+----------------------+ +| Local Id | Driver Type/Pin | Constraint | Site/BEL | Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+------------------------+----------------------|| +| 0 | FDCE/Q | None | SLICE_X61Y49/BFF | X1Y0 | 16 | 1 | | | getclock/clk_out_reg/Q | getclock/cnt_reg[15] - Static - ++----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+------------------------+----------------------|| +* Local Clocks in this context represents only clocks driven by non-global buffers +** Clock Loads column represents the clock pin loads (pin count) +*** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +5. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 18 | 1500 | 2 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 25 | 1500 | 4 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +6. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 1 | +| Y0 | 0 | 1 | ++----+----+----+ + + +7. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | | | | 27 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+-----+ +| | X0 | X1 | ++----+----+-----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 9 | +| Y0 | 0 | 18 | ++----+----+-----+ + + +8. Clock Region Cell Placement per Global Clock: Region X1Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 18 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +9. Clock Region Cell Placement per Global Clock: Region X1Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 9 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y26 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} +#endgroup diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_control_sets_placed.rpt b/Exp7/Exp7.runs/impl_1/led_chasing_control_sets_placed.rpt new file mode 100644 index 0000000..8edf40d --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/led_chasing_control_sets_placed.rpt @@ -0,0 +1,66 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 5 14:55:21 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file led_chasing_control_sets_placed.rpt +| Design : led_chasing +| Device : xc7a35t +---------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 2 | +| Unused register locations in slices containing registers | 5 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ +| 16+ | 2 | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 27 | 8 | +| No | Yes | No | 16 | 4 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++-----------------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++-----------------------+---------------+------------------+------------------+----------------+ +| getclock/cnt_reg[15] | | reset_IBUF | 4 | 16 | +| clk_IBUF_BUFG | | reset_IBUF | 8 | 27 | ++-----------------------+---------------+------------------+------------------+----------------+ + + diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_drc_opted.pb b/Exp7/Exp7.runs/impl_1/led_chasing_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp7/Exp7.runs/impl_1/led_chasing_drc_opted.pb differ diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_drc_opted.rpt b/Exp7/Exp7.runs/impl_1/led_chasing_drc_opted.rpt new file mode 100644 index 0000000..b809741 --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/led_chasing_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 5 14:55:20 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file led_chasing_drc_opted.rpt -pb led_chasing_drc_opted.pb -rpx led_chasing_drc_opted.rpx +| Design : led_chasing +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_drc_routed.pb b/Exp7/Exp7.runs/impl_1/led_chasing_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Exp7/Exp7.runs/impl_1/led_chasing_drc_routed.pb differ diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_drc_routed.rpt b/Exp7/Exp7.runs/impl_1/led_chasing_drc_routed.rpt new file mode 100644 index 0000000..5820bdd --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/led_chasing_drc_routed.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 5 14:55:35 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_drc -file led_chasing_drc_routed.rpt -pb led_chasing_drc_routed.pb -rpx led_chasing_drc_routed.rpx +| Design : led_chasing +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_io_placed.rpt b/Exp7/Exp7.runs/impl_1/led_chasing_io_placed.rpt new file mode 100644 index 0000000..e881372 --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/led_chasing_io_placed.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 5 14:55:21 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_io -file led_chasing_io_placed.rpt +| Design : led_chasing +| Device : xc7a35t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2013-12-19 +| Package Pin Delay Version : VERS. 2.0 2013-12-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 20 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+----------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+----------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | led[15] | High Range | IO_L19N_T3_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | led[13] | High Range | IO_L20N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G4 | led[14] | High Range | IO_L20P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | led[11] | High Range | IO_L21N_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| H5 | led[5] | High Range | IO_L24N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| H6 | led[6] | High Range | IO_L24P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | led[9] | High Range | IO_L22N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J3 | led[10] | High Range | IO_L22P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J4 | led[12] | High Range | IO_L21P_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J5 | led[4] | High Range | IO_25_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | led[7] | High Range | IO_L23N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K2 | led[8] | High Range | IO_L23P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K3 | led[0] | High Range | IO_L2P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K6 | led[3] | High Range | IO_0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | led[2] | High Range | IO_L1P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | led[1] | High Range | IO_L1N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N4 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| P3 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P4 | direction_ctrl | High Range | IO_L14P_T2_SRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P5 | speed_ctrl | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P17 | clk | High Range | IO_L12P_T1_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | reset | High Range | IO_L17P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | | +| R2 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | ++------------+----------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_methodology_drc_routed.pb b/Exp7/Exp7.runs/impl_1/led_chasing_methodology_drc_routed.pb new file mode 100644 index 0000000..62770bf Binary files /dev/null and b/Exp7/Exp7.runs/impl_1/led_chasing_methodology_drc_routed.pb differ diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_methodology_drc_routed.rpt b/Exp7/Exp7.runs/impl_1/led_chasing_methodology_drc_routed.rpt new file mode 100644 index 0000000..660ab8c --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/led_chasing_methodology_drc_routed.rpt @@ -0,0 +1,250 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 5 14:55:35 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_methodology -file led_chasing_methodology_drc_routed.rpt -pb led_chasing_methodology_drc_routed.pb -rpx led_chasing_methodology_drc_routed.rpx +| Design : led_chasing +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +----------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 43 ++-----------+----------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------+------------+ +| TIMING-17 | Warning | Non-clocked sequential cell | 43 | ++-----------+----------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Warning +Non-clocked sequential cell +The clock pin getclock/clk_out_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#5 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#6 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#7 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#8 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#9 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#10 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#11 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#12 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#13 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#14 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#15 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#16 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#17 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#18 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#19 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#20 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#21 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#22 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#23 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#24 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#25 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#26 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#27 Warning +Non-clocked sequential cell +The clock pin getclock/counter_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#28 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#29 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#30 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#31 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#32 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#33 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#34 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#35 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#36 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#37 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#38 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#39 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#40 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#41 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#42 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#43 Warning +Non-clocked sequential cell +The clock pin run/cnt_reg[9]/C is not reached by a timing clock +Related violations: + + diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_opt.dcp b/Exp7/Exp7.runs/impl_1/led_chasing_opt.dcp new file mode 100644 index 0000000..1159e76 Binary files /dev/null and b/Exp7/Exp7.runs/impl_1/led_chasing_opt.dcp differ diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_placed.dcp b/Exp7/Exp7.runs/impl_1/led_chasing_placed.dcp new file mode 100644 index 0000000..30d4bee Binary files /dev/null and b/Exp7/Exp7.runs/impl_1/led_chasing_placed.dcp differ diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_power_routed.rpt b/Exp7/Exp7.runs/impl_1/led_chasing_power_routed.rpt new file mode 100644 index 0000000..522a884 --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/led_chasing_power_routed.rpt @@ -0,0 +1,146 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 5 14:55:36 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_power -file led_chasing_power_routed.rpt -pb led_chasing_power_summary_routed.pb -rpx led_chasing_power_routed.rpx +| Design : led_chasing +| Device : xc7a35tcsg324-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.423 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.354 | +| Device Static (W) | 0.069 | +| Effective TJA (C/W) | 4.8 | +| Max Ambient (C) | 83.0 | +| Junction Temperature (C) | 27.0 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.162 | 109 | --- | --- | +| LUT as Logic | 0.126 | 35 | 20800 | 0.17 | +| CARRY4 | 0.017 | 7 | 8150 | 0.09 | +| Register | 0.013 | 43 | 41600 | 0.10 | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| Others | 0.000 | 3 | --- | --- | +| Signals | 0.180 | 91 | --- | --- | +| I/O | 0.012 | 20 | 210 | 9.52 | +| Static Power | 0.069 | | | | +| Total | 0.423 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.364 | 0.354 | 0.010 | +| Vccaux | 1.800 | 0.013 | 0.000 | 0.013 | +| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.8 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++-------------+-----------+ +| Name | Power (W) | ++-------------+-----------+ +| led_chasing | 0.354 | +| getclock | 0.299 | +| run | 0.015 | ++-------------+-----------+ + + diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_power_summary_routed.pb b/Exp7/Exp7.runs/impl_1/led_chasing_power_summary_routed.pb new file mode 100644 index 0000000..6d64e9c Binary files /dev/null and b/Exp7/Exp7.runs/impl_1/led_chasing_power_summary_routed.pb differ diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_route_status.pb b/Exp7/Exp7.runs/impl_1/led_chasing_route_status.pb new file mode 100644 index 0000000..6109368 Binary files /dev/null and b/Exp7/Exp7.runs/impl_1/led_chasing_route_status.pb differ diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_route_status.rpt b/Exp7/Exp7.runs/impl_1/led_chasing_route_status.rpt new file mode 100644 index 0000000..cf77c07 --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/led_chasing_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 156 : + # of nets not needing routing.......... : 63 : + # of internally routed nets........ : 63 : + # of routable nets..................... : 93 : + # of fully routed nets............. : 93 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_routed.dcp b/Exp7/Exp7.runs/impl_1/led_chasing_routed.dcp new file mode 100644 index 0000000..910ca1c Binary files /dev/null and b/Exp7/Exp7.runs/impl_1/led_chasing_routed.dcp differ diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_timing_summary_routed.pb b/Exp7/Exp7.runs/impl_1/led_chasing_timing_summary_routed.pb new file mode 100644 index 0000000..4526e93 --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/led_chasing_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_timing_summary_routed.rpt b/Exp7/Exp7.runs/impl_1/led_chasing_timing_summary_routed.rpt new file mode 100644 index 0000000..7c76a8b --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/led_chasing_timing_summary_routed.rpt @@ -0,0 +1,175 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 5 14:55:36 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file led_chasing_timing_summary_routed.rpt -pb led_chasing_timing_summary_routed.pb -rpx led_chasing_timing_summary_routed.rpx -warn_on_violation +| Design : led_chasing +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 27 register/latch pins with no clock driven by root clock pin: clk (HIGH) + + There are 16 register/latch pins with no clock driven by root clock pin: getclock/clk_out_reg/Q (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 86 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 3 input ports with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 16 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_utilization_placed.pb b/Exp7/Exp7.runs/impl_1/led_chasing_utilization_placed.pb new file mode 100644 index 0000000..2451ab0 Binary files /dev/null and b/Exp7/Exp7.runs/impl_1/led_chasing_utilization_placed.pb differ diff --git a/Exp7/Exp7.runs/impl_1/led_chasing_utilization_placed.rpt b/Exp7/Exp7.runs/impl_1/led_chasing_utilization_placed.rpt new file mode 100644 index 0000000..e2e1c37 --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/led_chasing_utilization_placed.rpt @@ -0,0 +1,207 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 5 14:55:21 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file led_chasing_utilization_placed.rpt -pb led_chasing_utilization_placed.pb +| Design : led_chasing +| Device : 7a35tcsg324-1 +| Design State : Fully Placed +------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 35 | 0 | 20800 | 0.17 | +| LUT as Logic | 35 | 0 | 20800 | 0.17 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 43 | 0 | 41600 | 0.10 | +| Register as Flip Flop | 43 | 0 | 41600 | 0.10 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 27 | Yes | - | Reset | +| 1 | Yes | Set | - | +| 15 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 19 | 0 | 8150 | 0.23 | +| SLICEL | 16 | 0 | | | +| SLICEM | 3 | 0 | | | +| LUT as Logic | 35 | 0 | 20800 | 0.17 | +| using O5 output only | 0 | | | | +| using O6 output only | 15 | | | | +| using O5 and O6 | 20 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 24 | 0 | 20800 | 0.12 | +| fully used LUT-FF pairs | 19 | | | | +| LUT-FF pairs with one unused LUT output | 5 | | | | +| LUT-FF pairs with one unused Flip Flop | 5 | | | | +| Unique Control Sets | 2 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 20 | 20 | 210 | 9.52 | +| IOB Master Pads | 10 | | | | +| IOB Slave Pads | 8 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDCE | 27 | Flop & Latch | +| LUT2 | 25 | LUT | +| OBUF | 16 | IO | +| LUT3 | 16 | LUT | +| FDRE | 15 | Flop & Latch | +| LUT4 | 7 | LUT | +| CARRY4 | 7 | CarryLogic | +| LUT6 | 4 | LUT | +| IBUF | 4 | IO | +| LUT5 | 2 | LUT | +| LUT1 | 1 | LUT | +| FDSE | 1 | Flop & Latch | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp7/Exp7.runs/impl_1/opt_design.pb b/Exp7/Exp7.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..4cc851f Binary files /dev/null and b/Exp7/Exp7.runs/impl_1/opt_design.pb differ diff --git a/Exp7/Exp7.runs/impl_1/place_design.pb b/Exp7/Exp7.runs/impl_1/place_design.pb new file mode 100644 index 0000000..38c3d7c Binary files /dev/null and b/Exp7/Exp7.runs/impl_1/place_design.pb differ diff --git a/Exp7/Exp7.runs/impl_1/route_design.pb b/Exp7/Exp7.runs/impl_1/route_design.pb new file mode 100644 index 0000000..93e6015 Binary files /dev/null and b/Exp7/Exp7.runs/impl_1/route_design.pb differ diff --git a/Exp7/Exp7.runs/impl_1/route_report_bus_skew_0.rpt b/Exp7/Exp7.runs/impl_1/route_report_bus_skew_0.rpt new file mode 100644 index 0000000..a3d8a7e --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/route_report_bus_skew_0.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 5 14:55:36 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +| Design : led_chasing +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/Exp7/Exp7.runs/impl_1/usage_statistics_webtalk.xml b/Exp7/Exp7.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..37ea743 --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,618 @@ + + +
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+ diff --git a/Exp7/Exp7.runs/impl_1/vivado.jou b/Exp7/Exp7.runs/impl_1/vivado.jou new file mode 100644 index 0000000..661a0c8 --- /dev/null +++ b/Exp7/Exp7.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 5 14:54:57 2024 +# Process ID: 5000 +# Current directory: F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/impl_1 +# Command line: vivado.exe -log led_chasing.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source led_chasing.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/impl_1/led_chasing.vdi +# Journal file: F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source led_chasing.tcl -notrace diff --git a/Exp7/Exp7.runs/impl_1/vivado.pb b/Exp7/Exp7.runs/impl_1/vivado.pb new file mode 100644 index 0000000..0365905 Binary files /dev/null and b/Exp7/Exp7.runs/impl_1/vivado.pb differ diff --git a/Exp7/Exp7.runs/impl_1/write_bitstream.pb b/Exp7/Exp7.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..d737234 Binary files /dev/null and b/Exp7/Exp7.runs/impl_1/write_bitstream.pb differ diff --git a/Exp7/Exp7.runs/synth_1/.Xil/led_chasing_propImpl.xdc b/Exp7/Exp7.runs/synth_1/.Xil/led_chasing_propImpl.xdc new file mode 100644 index 0000000..a27f211 --- /dev/null +++ b/Exp7/Exp7.runs/synth_1/.Xil/led_chasing_propImpl.xdc @@ -0,0 +1,41 @@ +set_property SRC_FILE_INFO {cfile:F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/constrs_1/new/led_chasing.xdc rfile:../../../Exp7.srcs/constrs_1/new/led_chasing.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P17 [get_ports clk] +set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F6 [get_ports {led[15]}] +set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G4 [get_ports {led[14]}] +set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G3 [get_ports {led[13]}] +set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J4 [get_ports {led[12]}] +set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN H4 [get_ports {led[11]}] +set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J3 [get_ports {led[10]}] +set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J2 [get_ports {led[9]}] +set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN K2 [get_ports {led[8]}] +set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN K1 [get_ports {led[7]}] +set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN H6 [get_ports {led[6]}] +set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN H5 [get_ports {led[5]}] +set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN J5 [get_ports {led[4]}] +set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN K6 [get_ports {led[3]}] +set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN L1 [get_ports {led[2]}] +set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN M1 [get_ports {led[1]}] +set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN K3 [get_ports {led[0]}] +set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P4 [get_ports direction_ctrl] +set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R1 [get_ports reset] +set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P5 [get_ports speed_ctrl] diff --git a/Exp7/Exp7.runs/synth_1/gen_run.xml b/Exp7/Exp7.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..e8e1b74 --- /dev/null +++ b/Exp7/Exp7.runs/synth_1/gen_run.xml @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp7/Exp7.runs/synth_1/htr.txt b/Exp7/Exp7.runs/synth_1/htr.txt new file mode 100644 index 0000000..492220b --- /dev/null +++ b/Exp7/Exp7.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log led_chasing.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source led_chasing.tcl diff --git a/Exp7/Exp7.runs/synth_1/led_chasing.dcp b/Exp7/Exp7.runs/synth_1/led_chasing.dcp new file mode 100644 index 0000000..938057a Binary files /dev/null and b/Exp7/Exp7.runs/synth_1/led_chasing.dcp differ diff --git a/Exp7/Exp7.runs/synth_1/led_chasing.tcl b/Exp7/Exp7.runs/synth_1/led_chasing.tcl new file mode 100644 index 0000000..ef3f7df --- /dev/null +++ b/Exp7/Exp7.runs/synth_1/led_chasing.tcl @@ -0,0 +1,58 @@ +# +# Synthesis run script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param xicom.use_bs_reader 1 +create_project -in_memory -part xc7a35tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp7/Exp7.cache/wt [current_project] +set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp7/Exp7.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp7/Exp7.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib { + F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/sources_1/new/shift_reg.v + F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/sources_1/new/slow_clock.v + F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/sources_1/new/led_chasing.v +} +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/constrs_1/new/led_chasing.xdc +set_property used_in_implementation false [get_files F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/constrs_1/new/led_chasing.xdc] + +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top led_chasing -part xc7a35tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef led_chasing.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file led_chasing_utilization_synth.rpt -pb led_chasing_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/Exp7/Exp7.runs/synth_1/led_chasing.vds b/Exp7/Exp7.runs/synth_1/led_chasing.vds new file mode 100644 index 0000000..550f21e --- /dev/null +++ b/Exp7/Exp7.runs/synth_1/led_chasing.vds @@ -0,0 +1,309 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 5 14:54:22 2024 +# Process ID: 27264 +# Current directory: F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/synth_1 +# Command line: vivado.exe -log led_chasing.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source led_chasing.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/synth_1/led_chasing.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source led_chasing.tcl -notrace +Command: synth_design -top led_chasing -part xc7a35tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 21800 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 411.520 ; gain = 97.734 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'led_chasing' [F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/sources_1/new/led_chasing.v:23] +INFO: [Synth 8-6157] synthesizing module 'slow_clock' [F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/sources_1/new/slow_clock.v:23] + Parameter sys_clk bound to: 100000000 - type: integer + Parameter clk_slow bound to: 1 - type: integer + Parameter clk_fast bound to: 5 - type: integer + Parameter max_slow bound to: 49999999 - type: integer + Parameter max_fast bound to: 9999999 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'slow_clock' (1#1) [F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/sources_1/new/slow_clock.v:23] +INFO: [Synth 8-6157] synthesizing module 'shift_reg' [F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/sources_1/new/shift_reg.v:23] + Parameter CNT_SIZE bound to: 16 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'shift_reg' (2#1) [F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/sources_1/new/shift_reg.v:23] +INFO: [Synth 8-6155] done synthesizing module 'led_chasing' (3#1) [F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/sources_1/new/led_chasing.v:23] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 466.504 ; gain = 152.719 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 466.504 ; gain = 152.719 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 466.504 ; gain = 152.719 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/constrs_1/new/led_chasing.xdc] +Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/constrs_1/new/led_chasing.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp7/Exp7.srcs/constrs_1/new/led_chasing.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/led_chasing_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/led_chasing_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 790.121 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 790.121 ; gain = 476.336 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 790.121 ; gain = 476.336 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 790.121 ; gain = 476.336 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5545] ROM "clk_out" won't be mapped to RAM because address size (26) is larger than maximum supported(25) +INFO: [Synth 8-5545] ROM "clk_out" won't be mapped to RAM because address size (26) is larger than maximum supported(25) +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 790.121 ; gain = 476.336 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 26 Bit Adders := 1 ++---Registers : + 26 Bit Registers := 1 + 16 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 26 Bit Muxes := 3 + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 + 4 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module slow_clock +Detailed RTL Component Info : ++---Adders : + 2 Input 26 Bit Adders := 1 ++---Registers : + 26 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 26 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 1 + 4 Input 1 Bit Muxes := 1 +Module shift_reg +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-5545] ROM "getclock/clk_out" won't be mapped to RAM because address size (26) is larger than maximum supported(25) +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 790.121 ; gain = 476.336 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 790.121 ; gain = 476.336 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 790.121 ; gain = 476.336 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 798.871 ; gain = 485.086 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 798.871 ; gain = 485.086 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 798.871 ; gain = 485.086 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 798.871 ; gain = 485.086 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 798.871 ; gain = 485.086 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 798.871 ; gain = 485.086 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 798.871 ; gain = 485.086 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 7| +|3 |LUT1 | 1| +|4 |LUT2 | 25| +|5 |LUT3 | 16| +|6 |LUT4 | 7| +|7 |LUT5 | 2| +|8 |LUT6 | 4| +|9 |FDCE | 27| +|10 |FDRE | 15| +|11 |FDSE | 1| +|12 |IBUF | 4| +|13 |OBUF | 16| ++------+-------+------+ + +Report Instance Areas: ++------+-----------+-----------+------+ +| |Instance |Module |Cells | ++------+-----------+-----------+------+ +|1 |top | | 126| +|2 | getclock |slow_clock | 73| +|3 | run |shift_reg | 32| ++------+-----------+-----------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 798.871 ; gain = 485.086 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 798.871 ; gain = 161.469 +Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 798.871 ; gain = 485.086 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 811.102 ; gain = 510.246 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/synth_1/led_chasing.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file led_chasing_utilization_synth.rpt -pb led_chasing_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 811.102 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Thu Dec 5 14:54:50 2024... diff --git a/Exp7/Exp7.runs/synth_1/led_chasing_utilization_synth.pb b/Exp7/Exp7.runs/synth_1/led_chasing_utilization_synth.pb new file mode 100644 index 0000000..2451ab0 Binary files /dev/null and b/Exp7/Exp7.runs/synth_1/led_chasing_utilization_synth.pb differ diff --git a/Exp7/Exp7.runs/synth_1/led_chasing_utilization_synth.rpt b/Exp7/Exp7.runs/synth_1/led_chasing_utilization_synth.rpt new file mode 100644 index 0000000..3238358 --- /dev/null +++ b/Exp7/Exp7.runs/synth_1/led_chasing_utilization_synth.rpt @@ -0,0 +1,180 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 5 14:54:50 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file led_chasing_utilization_synth.rpt -pb led_chasing_utilization_synth.pb +| Design : led_chasing +| Device : 7a35tcsg324-1 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 35 | 0 | 20800 | 0.17 | +| LUT as Logic | 35 | 0 | 20800 | 0.17 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 43 | 0 | 41600 | 0.10 | +| Register as Flip Flop | 43 | 0 | 41600 | 0.10 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 27 | Yes | - | Reset | +| 1 | Yes | Set | - | +| 15 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 20 | 0 | 210 | 9.52 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDCE | 27 | Flop & Latch | +| LUT2 | 25 | LUT | +| OBUF | 16 | IO | +| LUT3 | 16 | LUT | +| FDRE | 15 | Flop & Latch | +| LUT4 | 7 | LUT | +| CARRY4 | 7 | CarryLogic | +| LUT6 | 4 | LUT | +| IBUF | 4 | IO | +| LUT5 | 2 | LUT | +| LUT1 | 1 | LUT | +| FDSE | 1 | Flop & Latch | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp7/Exp7.runs/synth_1/vivado.jou b/Exp7/Exp7.runs/synth_1/vivado.jou new file mode 100644 index 0000000..44a6912 --- /dev/null +++ b/Exp7/Exp7.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 5 14:54:22 2024 +# Process ID: 27264 +# Current directory: F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/synth_1 +# Command line: vivado.exe -log led_chasing.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source led_chasing.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/synth_1/led_chasing.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp7/Exp7.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source led_chasing.tcl -notrace diff --git a/Exp7/Exp7.runs/synth_1/vivado.pb b/Exp7/Exp7.runs/synth_1/vivado.pb new file mode 100644 index 0000000..fc42425 Binary files /dev/null and b/Exp7/Exp7.runs/synth_1/vivado.pb differ diff --git a/Exp7/Exp7.sim/sim_1/behav/xsim/glbl.v b/Exp7/Exp7.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp7/Exp7.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp7/Exp7.sim/sim_1/behav/xsim/led_chasing_tb.tcl b/Exp7/Exp7.sim/sim_1/behav/xsim/led_chasing_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp7/Exp7.sim/sim_1/behav/xsim/led_chasing_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp7/Exp7.sim/sim_1/behav/xsim/led_chasing_tb_vlog.prj b/Exp7/Exp7.sim/sim_1/behav/xsim/led_chasing_tb_vlog.prj new file mode 100644 index 0000000..5fa3492 --- /dev/null +++ b/Exp7/Exp7.sim/sim_1/behav/xsim/led_chasing_tb_vlog.prj @@ -0,0 +1,12 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp7.srcs/sources_1/new/led_chasing.v" \ +"../../../../Exp7.srcs/sources_1/new/shift_reg.v" \ +"../../../../Exp7.srcs/sources_1/new/slow_clock.v" \ +"../../../../Exp7.srcs/sim_1/new/led_chasing_tb.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp7/Exp7.sim/sim_1/behav/xsim/led_chasing_vlog.prj b/Exp7/Exp7.sim/sim_1/behav/xsim/led_chasing_vlog.prj new file mode 100644 index 0000000..ed0c9e4 --- /dev/null +++ b/Exp7/Exp7.sim/sim_1/behav/xsim/led_chasing_vlog.prj @@ -0,0 +1,11 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp7.srcs/sources_1/new/shift_reg.v" \ +"../../../../Exp7.srcs/sources_1/new/slow_clock.v" \ +"../../../../Exp7.srcs/sources_1/new/led_chasing.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp7/Exp7.sim/sim_1/behav/xsim/webtalk.jou b/Exp7/Exp7.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..5b34dfd --- /dev/null +++ b/Exp7/Exp7.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 10:19:07 2024 +# Process ID: 8624 +# Current directory: F:/Schoolwork/DigitalLogic/Exp7/Exp7.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp7/Exp7.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp7/Exp7.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp7/Exp7.sim/sim_1/behav/xsim/webtalk_59100.backup.jou b/Exp7/Exp7.sim/sim_1/behav/xsim/webtalk_59100.backup.jou new file mode 100644 index 0000000..2c33c38 --- /dev/null +++ b/Exp7/Exp7.sim/sim_1/behav/xsim/webtalk_59100.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 10:14:42 2024 +# Process ID: 59100 +# Current directory: F:/Schoolwork/DigitalLogic/Exp7/Exp7.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp7/Exp7.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp7/Exp7.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp7/Exp7.sim/sim_1/behav/xsim/xelab.pb b/Exp7/Exp7.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..f060208 Binary files /dev/null and b/Exp7/Exp7.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/Compile_Options.txt b/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..f31f978 --- /dev/null +++ b/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "eccce0952ecf46b28fc03ab5fbdbb8b1" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "led_chasing_tb_behav" "xil_defaultlib.led_chasing_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/TempBreakPointFile.txt b/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/obj/xsim_1.c b/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..bdabaa6 --- /dev/null +++ b/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/obj/xsim_1.c @@ -0,0 +1,113 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_4(char*, char *); +extern void execute_6(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[19] = {(funcp)execute_7, (funcp)execute_8, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_13, (funcp)execute_14, (funcp)execute_4, (funcp)execute_6, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 19; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/led_chasing_tb_behav/xsim.reloc", (void **)funcTab, 19); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/led_chasing_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/led_chasing_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/led_chasing_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/led_chasing_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/led_chasing_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/webtalk/xsim_webtalk.tcl b/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..06594a4 --- /dev/null +++ b/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,33 @@ +webtalk_init -webtalk_dir F:/Schoolwork/DigitalLogic/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Thu Dec 12 14:36:35 2024" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.1 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2188600" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "78ec1a93-fd1a-4b14-8c4b-87f04256706b" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "eccce0952ecf46b28fc03ab5fbdbb8b1" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "14" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "13th Gen Intel(R) Core(TM) i7-13700H" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2918 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key runall -value "true" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "4100 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6748_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1557009044 -regid "" -xml F:/Schoolwork/DigitalLogic/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html F:/Schoolwork/DigitalLogic/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm F:/Schoolwork/DigitalLogic/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/xsim.mem b/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/xsim.mem new file mode 100644 index 0000000..8c44ffe Binary files /dev/null and b/Exp7/Exp7.sim/sim_1/behav/xsim/xsim.dir/led_chasing_tb_behav/xsim.mem differ diff --git a/Exp7/Exp7.sim/sim_1/behav/xsim/xvlog.pb b/Exp7/Exp7.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..5b6a5f4 Binary files /dev/null and b/Exp7/Exp7.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Exp7/Exp7.srcs/constrs_1/new/led_chasing.xdc b/Exp7/Exp7.srcs/constrs_1/new/led_chasing.xdc new file mode 100644 index 0000000..a078e56 --- /dev/null +++ b/Exp7/Exp7.srcs/constrs_1/new/led_chasing.xdc @@ -0,0 +1,40 @@ +set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports direction_ctrl] +set_property IOSTANDARD LVCMOS33 [get_ports reset] +set_property IOSTANDARD LVCMOS33 [get_ports speed_ctrl] +set_property PACKAGE_PIN P17 [get_ports clk] +set_property PACKAGE_PIN F6 [get_ports {led[15]}] +set_property PACKAGE_PIN G4 [get_ports {led[14]}] +set_property PACKAGE_PIN G3 [get_ports {led[13]}] +set_property PACKAGE_PIN J4 [get_ports {led[12]}] +set_property PACKAGE_PIN H4 [get_ports {led[11]}] +set_property PACKAGE_PIN J3 [get_ports {led[10]}] +set_property PACKAGE_PIN J2 [get_ports {led[9]}] +set_property PACKAGE_PIN K2 [get_ports {led[8]}] +set_property PACKAGE_PIN K1 [get_ports {led[7]}] +set_property PACKAGE_PIN H6 [get_ports {led[6]}] +set_property PACKAGE_PIN H5 [get_ports {led[5]}] +set_property PACKAGE_PIN J5 [get_ports {led[4]}] +set_property PACKAGE_PIN K6 [get_ports {led[3]}] +set_property PACKAGE_PIN L1 [get_ports {led[2]}] +set_property PACKAGE_PIN M1 [get_ports {led[1]}] +set_property PACKAGE_PIN K3 [get_ports {led[0]}] +set_property PACKAGE_PIN P4 [get_ports direction_ctrl] +set_property PACKAGE_PIN R1 [get_ports reset] +set_property PACKAGE_PIN P5 [get_ports speed_ctrl] diff --git a/Exp7/Exp7.srcs/sim_1/new/led_chasing_tb.v b/Exp7/Exp7.srcs/sim_1/new/led_chasing_tb.v new file mode 100644 index 0000000..327bbbb --- /dev/null +++ b/Exp7/Exp7.srcs/sim_1/new/led_chasing_tb.v @@ -0,0 +1,54 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/12 10:11:33 +// Design Name: +// Module Name: led_chasing_tb +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module led_chasing_tb(); + reg clk; + reg reset; + reg speed_ctrl; + reg direction_ctrl; + wire [15:0] led; + led_chasing dut( + .clk(clk), + .reset(reset), + .speed_ctrl(speed_ctrl), + .direction_ctrl(direction_ctrl), + .led(led) + ); + initial begin + clk = 0; + forever #1 clk = ~clk; + end + initial begin + reset = 1; + speed_ctrl = 0; + direction_ctrl = 0; + #100 reset = 0; + #1000; + speed_ctrl = 1; + #1000; + direction_ctrl = 1; + #1000; + speed_ctrl = 0; + #1000; + $finish; + end +endmodule diff --git a/Exp7/Exp7.srcs/sources_1/new/led_chasing.v b/Exp7/Exp7.srcs/sources_1/new/led_chasing.v new file mode 100644 index 0000000..e76f9f0 --- /dev/null +++ b/Exp7/Exp7.srcs/sources_1/new/led_chasing.v @@ -0,0 +1,29 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/05 11:15:53 +// Design Name: +// Module Name: led_chasing +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module led_chasing(clk, reset, speed_ctrl, direction_ctrl, led); +input clk, reset, speed_ctrl, direction_ctrl; +output [15:0] led; +wire clk_out; +slow_clock getclock (.clk(clk), .reset(reset), .speed_ctrl(speed_ctrl), .clk_out(clk_out)); +shift_reg run (.reset(reset), .clk(clk_out), .direction_ctrl(direction_ctrl), .cnt(led)); +endmodule diff --git a/Exp7/Exp7.srcs/sources_1/new/shift_reg.v b/Exp7/Exp7.srcs/sources_1/new/shift_reg.v new file mode 100644 index 0000000..9be95bd --- /dev/null +++ b/Exp7/Exp7.srcs/sources_1/new/shift_reg.v @@ -0,0 +1,37 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/05 11:33:38 +// Design Name: +// Module Name: shift_reg +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module shift_reg(reset, clk, direction_ctrl, cnt); +parameter CNT_SIZE = 16; +input reset, clk, direction_ctrl; +output reg [CNT_SIZE-1 : 0] cnt; +always @(posedge clk or posedge reset) begin + if (reset) + cnt <= 16'b0000000000000001; + else begin + if (direction_ctrl == 0) + cnt <= {cnt[0], cnt[CNT_SIZE-1 : 1]}; + else + cnt <= {cnt[CNT_SIZE-2 : 0], cnt[CNT_SIZE-1]}; + end +end +endmodule diff --git a/Exp7/Exp7.srcs/sources_1/new/slow_clock.v b/Exp7/Exp7.srcs/sources_1/new/slow_clock.v new file mode 100644 index 0000000..5a6f12b --- /dev/null +++ b/Exp7/Exp7.srcs/sources_1/new/slow_clock.v @@ -0,0 +1,60 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/05 11:21:41 +// Design Name: +// Module Name: slow_clock +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module slow_clock(clk, reset, speed_ctrl, clk_out); + input clk, reset, speed_ctrl; + output reg clk_out; + parameter sys_clk = 100_000_000; + parameter clk_slow = 1; + parameter clk_fast = 5; + parameter max_slow = sys_clk / (2 * clk_slow) - 1; +// parameter max_slow = 10 - 1; // for simulation + parameter max_fast = sys_clk / (2 * clk_fast) - 1; +// parameter max_fast = 5 - 1; // for simulation + reg [25:0] counter; + always @(posedge clk or posedge reset) begin + if (reset) begin + counter <= 0; + clk_out <= 0; + end + else begin + if (speed_ctrl == 0) begin + if (counter == max_slow) begin + counter <= 0; + clk_out <= ~clk_out; + end + else begin + counter <= counter + 1; + end + end + else if (speed_ctrl == 1) begin + if (counter == max_fast) begin + counter <= 0; + clk_out <= ~clk_out; + end + else begin + counter <= counter + 1; + end + end + end + end +endmodule diff --git a/Exp7/Exp7.xpr b/Exp7/Exp7.xpr new file mode 100644 index 0000000..5be79f3 --- /dev/null +++ b/Exp7/Exp7.xpr @@ -0,0 +1,165 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp8-1/Exp8-1.cache/wt/webtalk_pa.xml b/Exp8-1/Exp8-1.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..dae24bc --- /dev/null +++ b/Exp8-1/Exp8-1.cache/wt/webtalk_pa.xml @@ -0,0 +1,54 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp8-1/Exp8-1.ip_user_files/README.txt b/Exp8-1/Exp8-1.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/Exp8-1/Exp8-1.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/glbl.v b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/tb_sequence_detector_11001.tcl b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/tb_sequence_detector_11001.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/tb_sequence_detector_11001.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/tb_sequence_detector_11001_vlog.prj b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/tb_sequence_detector_11001_vlog.prj new file mode 100644 index 0000000..3603a23 --- /dev/null +++ b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/tb_sequence_detector_11001_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../Exp8-1.srcs/sources_1/new/sequence_detector_11001.v" \ +"../../../../Exp8-1.srcs/sim_1/new/tb_sequence_detector_11001.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/webtalk.jou b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..34e1c18 --- /dev/null +++ b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 02:13:40 2024 +# Process ID: 17992 +# Current directory: F:/Schoolwork/DigitalLogic/Exp8-1/Exp8-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp8-1/Exp8-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/webtalk_25784.backup.jou b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/webtalk_25784.backup.jou new file mode 100644 index 0000000..0988471 --- /dev/null +++ b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/webtalk_25784.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 12 02:12:37 2024 +# Process ID: 25784 +# Current directory: F:/Schoolwork/DigitalLogic/Exp8-1/Exp8-1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source F:/Schoolwork/DigitalLogic/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: F:/Schoolwork/DigitalLogic/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: F:/Schoolwork/DigitalLogic/Exp8-1/Exp8-1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source F:/Schoolwork/DigitalLogic/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xelab.pb b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..1ca440c Binary files /dev/null and b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/Compile_Options.txt b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/Compile_Options.txt new file mode 100644 index 0000000..522e4b2 --- /dev/null +++ b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "64543e9995df4818a6ba432c776b143d" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_sequence_detector_11001_behav" "xil_defaultlib.tb_sequence_detector_11001" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/TempBreakPointFile.txt b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/obj/xsim_1.c b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/obj/xsim_1.c new file mode 100644 index 0000000..8ae4a42 --- /dev/null +++ b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/obj/xsim_1.c @@ -0,0 +1,112 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_3(char*, char *); +extern void execute_4(char*, char *); +extern void execute_5(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[18] = {(funcp)execute_6, (funcp)execute_7, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 18; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/tb_sequence_detector_11001_behav/xsim.reloc", (void **)funcTab, 18); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/tb_sequence_detector_11001_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_sequence_detector_11001_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern int xsim_argc_copy ; +extern char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/tb_sequence_detector_11001_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/tb_sequence_detector_11001_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/tb_sequence_detector_11001_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/xsim.mem b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/xsim.mem new file mode 100644 index 0000000..48d07a6 Binary files /dev/null and b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xsim.dir/tb_sequence_detector_11001_behav/xsim.mem differ diff --git a/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xvlog.pb b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..c4d3908 Binary files /dev/null and b/Exp8-1/Exp8-1.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/Exp8-1/Exp8-1.srcs/sim_1/new/tb_sequence_detector_11001.v b/Exp8-1/Exp8-1.srcs/sim_1/new/tb_sequence_detector_11001.v new file mode 100644 index 0000000..7245330 --- /dev/null +++ b/Exp8-1/Exp8-1.srcs/sim_1/new/tb_sequence_detector_11001.v @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/12 01:59:18 +// Design Name: +// Module Name: tb_sequence_detector_11001 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_sequence_detector_11001(); +reg clk; +reg reset; +reg x; +wire z; +sequence_detector_11001 uut ( + .clk(clk), + .reset(reset), + .x(x), + .z(z) +); +always #5 clk = ~clk; +initial begin + // Init signal + clk = 0; + reset = 1; + x = 0; + // Undo reset + #10 reset = 0; + // Test sequences + #10 x = 1; // S0 -> S1 + #10 x = 1; // S1 -> S2 + #10 x = 0; // S2 -> S3 + #10 x = 0; // S3 -> S4 + #10 x = 1; // S4 -> S5 (11001) + // Reset + #10 reset = 1; + #10 reset = 0; + // Test multiple sequences + #10 x = 1; // S0 -> S1 + #10 x = 1; // S1 -> S2 + #10 x = 0; // S2 -> S3 + #10 x = 0; // S3 -> S4 + #10 x = 1; // S4 -> S5 (11001) + #10 x = 0; // No operation + #10 x = 1; // S0 -> S1 + #20 $finish; +end +endmodule \ No newline at end of file diff --git a/Exp8-1/Exp8-1.srcs/sources_1/new/sequence_detector_11001.v b/Exp8-1/Exp8-1.srcs/sources_1/new/sequence_detector_11001.v new file mode 100644 index 0000000..7fd999b --- /dev/null +++ b/Exp8-1/Exp8-1.srcs/sources_1/new/sequence_detector_11001.v @@ -0,0 +1,92 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/12 00:12:11 +// Design Name: +// Module Name: sequence_detector_11001 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module sequence_detector_11001( + input wire clk, + input wire reset, + input wire x, + output reg z +); +parameter S0 = 3'b000, // Initial + S1 = 3'b001, // 1 + S2 = 3'b010, // 1-1 + S3 = 3'b011, // 1-1-0 + S4 = 3'b100, // 1-1-0-0 + S5 = 3'b101; // 11001 +reg [2:0] state_c, state_n; // Current state & next state +// Part 1 +always @(posedge clk) begin + if (reset) + state_c <= S0; // Reset + else + state_c <= state_n; // Update current state +end +// Part 2 +always @(*) begin + // Keep current state by default + state_n = state_c; + case(state_c) + S0: begin + if (x) + state_n = S1; // If 1 go to S1 + else + state_n = S0; // If 0 keep S0 + end + S1: begin + if (x) + state_n = S2; // If 1 go to S2 + else + state_n = S0; // If 0 back to S0 + end + S2: begin + if (!x) + state_n = S3; // If 0 go to S3 + else + state_n = S2; // If 1 keep S2 + end + S3: begin + if (!x) + state_n = S4; // If 0 go to S4 + else + state_n = S1; // If 1 back to S1 + end + S4: begin + if (x) + state_n = S5; // If 1 go to S5 (11001) + else + state_n = S0; // If 0 back to S0 + end + S5: begin + state_n = S0; // Back to initial state + end + default: state_n = S0; + endcase +end +// Part 3 +always @(posedge clk) begin + if (reset) + z <= 0; // Reset output 0 + else + // S5 output 1 + z <= (state_c == S5); +end +endmodule diff --git a/Exp8-1/Exp8-1.xpr b/Exp8-1/Exp8-1.xpr new file mode 100644 index 0000000..14568de --- /dev/null +++ b/Exp8-1/Exp8-1.xpr @@ -0,0 +1,145 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + diff --git a/Exp8-2/Exp8-2.cache/wt/webtalk_pa.xml b/Exp8-2/Exp8-2.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..378c70f --- /dev/null +++ b/Exp8-2/Exp8-2.cache/wt/webtalk_pa.xml @@ -0,0 +1,57 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/Exp8-2/Exp8-2.runs/.jobs/vrs_config_1.xml b/Exp8-2/Exp8-2.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..3dd8923 --- /dev/null +++ b/Exp8-2/Exp8-2.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp8-2/Exp8-2.runs/.jobs/vrs_config_2.xml b/Exp8-2/Exp8-2.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..3dd8923 --- /dev/null +++ b/Exp8-2/Exp8-2.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Exp8-2/Exp8-2.runs/synth_1/date_display.dcp b/Exp8-2/Exp8-2.runs/synth_1/date_display.dcp new file mode 100644 index 0000000..9895899 Binary files /dev/null and b/Exp8-2/Exp8-2.runs/synth_1/date_display.dcp differ diff --git a/Exp8-2/Exp8-2.runs/synth_1/date_display.tcl b/Exp8-2/Exp8-2.runs/synth_1/date_display.tcl new file mode 100644 index 0000000..8478d63 --- /dev/null +++ b/Exp8-2/Exp8-2.runs/synth_1/date_display.tcl @@ -0,0 +1,50 @@ +# +# Synthesis run script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +create_project -in_memory -part xc7a35tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.cache/wt [current_project] +set_property parent.project_path F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo f:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top date_display -part xc7a35tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef date_display.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file date_display_utilization_synth.rpt -pb date_display_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/Exp8-2/Exp8-2.runs/synth_1/date_display.vds b/Exp8-2/Exp8-2.runs/synth_1/date_display.vds new file mode 100644 index 0000000..6818710 --- /dev/null +++ b/Exp8-2/Exp8-2.runs/synth_1/date_display.vds @@ -0,0 +1,319 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Mon Dec 16 19:20:39 2024 +# Process ID: 20280 +# Current directory: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1 +# Command line: vivado.exe -log date_display.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source date_display.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1/date_display.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source date_display.tcl -notrace +Command: synth_design -top date_display -part xc7a35tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 28272 +--------------------------------------------------------------------------------- +Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 412.238 ; gain = 98.691 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'date_display' [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:23] + Parameter S0 bound to: 4'b0000 + Parameter S1 bound to: 4'b0001 + Parameter S2 bound to: 4'b0010 + Parameter S3 bound to: 4'b0011 + Parameter S4 bound to: 4'b0100 + Parameter S5 bound to: 4'b0101 + Parameter S6 bound to: 4'b0110 + Parameter S7 bound to: 4'b0111 + Parameter S8 bound to: 4'b1000 + Parameter S9 bound to: 4'b1001 + Parameter S10 bound to: 4'b1010 + Parameter S11 bound to: 4'b1011 + Parameter S12 bound to: 4'b1100 + Parameter S13 bound to: 4'b1101 + Parameter S14 bound to: 4'b1110 + Parameter S15 bound to: 4'b1111 + Parameter SEG_0 bound to: 8'b11111101 + Parameter SEG_1 bound to: 8'b01100001 + Parameter SEG_2 bound to: 8'b11011011 + Parameter SEG_3 bound to: 8'b11110011 + Parameter SEG_4 bound to: 8'b01100111 + Parameter SEG_5 bound to: 8'b10110111 + Parameter SEG_6 bound to: 8'b10111111 + Parameter SEG_7 bound to: 8'b11100001 + Parameter SEG_8 bound to: 8'b11111111 + Parameter SEG_9 bound to: 8'b11110111 + Parameter SEG_DP bound to: 8'b00000001 +INFO: [Synth 8-226] default block is never used [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:93] +WARNING: [Synth 8-6014] Unused sequential element seg_temp_reg was removed. [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:121] +INFO: [Synth 8-6155] done synthesizing module 'date_display' (1#1) [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:23] +--------------------------------------------------------------------------------- +Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Synth 8-5546] ROM "clk_1hz" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5544] ROM "sequence" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 20 Bit Adders := 1 ++---Registers : + 20 Bit Registers := 1 + 8 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 17 Input 56 Bit Muxes := 1 + 2 Input 20 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module date_display +Detailed RTL Component Info : ++---Adders : + 2 Input 20 Bit Adders := 1 ++---Registers : + 20 Bit Registers := 1 + 8 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 17 Input 56 Bit Muxes := 1 + 2 Input 20 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-5546] ROM "clk_1hz" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-3886] merging instance 'an_reg[0]' (FDP) to 'seg_reg[7]' +INFO: [Synth 8-3886] merging instance 'an_reg[1]' (FDP) to 'an_reg[2]' +INFO: [Synth 8-3886] merging instance 'an_reg[2]' (FDP) to 'an_reg[3]' +INFO: [Synth 8-3886] merging instance 'an_reg[3]' (FDP) to 'an_reg[4]' +INFO: [Synth 8-3886] merging instance 'an_reg[4]' (FDP) to 'an_reg[5]' +INFO: [Synth 8-3886] merging instance 'an_reg[5]' (FDP) to 'an_reg[6]' +INFO: [Synth 8-3886] merging instance 'an_reg[6]' (FDP) to 'an_reg[7]' +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\an_reg[7] ) +INFO: [Synth 8-3886] merging instance 'seg_reg[0]' (FDP) to 'seg_reg[7]' +INFO: [Synth 8-3886] merging instance 'seg_reg[1]' (FDP) to 'seg_reg[7]' +INFO: [Synth 8-3886] merging instance 'seg_reg[2]' (FDP) to 'seg_reg[7]' +INFO: [Synth 8-3886] merging instance 'seg_reg[3]' (FDP) to 'seg_reg[7]' +INFO: [Synth 8-3886] merging instance 'seg_reg[4]' (FDP) to 'seg_reg[7]' +INFO: [Synth 8-3886] merging instance 'seg_reg[5]' (FDP) to 'seg_reg[7]' +INFO: [Synth 8-3886] merging instance 'seg_reg[6]' (FDP) to 'seg_reg[7]' +WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[3]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[2]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[1]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[0]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (an_reg[7]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[19]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[18]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[17]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[16]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[15]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[14]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[13]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[12]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[11]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[10]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[9]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[8]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[7]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[6]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[5]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[4]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[3]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[2]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[1]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (counter_reg[0]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (clk_1hz_reg) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (state_c_reg[3]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (state_c_reg[2]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (state_c_reg[1]) is unused and will be removed from module date_display. +WARNING: [Synth 8-3332] Sequential element (state_c_reg[0]) is unused and will be removed from module date_display. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |BUFG | 1| +|2 |FDPE | 1| +|3 |IBUF | 2| +|4 |OBUF | 16| ++------+-----+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 20| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 31 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 +Synthesis Optimization Complete : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +30 Infos, 31 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 692.234 ; gain = 391.566 +INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1/date_display.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file date_display_utilization_synth.rpt -pb date_display_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 692.234 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Mon Dec 16 19:20:53 2024... diff --git a/Exp8-2/Exp8-2.runs/synth_1/date_display_utilization_synth.pb b/Exp8-2/Exp8-2.runs/synth_1/date_display_utilization_synth.pb new file mode 100644 index 0000000..a0703f5 Binary files /dev/null and b/Exp8-2/Exp8-2.runs/synth_1/date_display_utilization_synth.pb differ diff --git a/Exp8-2/Exp8-2.runs/synth_1/date_display_utilization_synth.rpt b/Exp8-2/Exp8-2.runs/synth_1/date_display_utilization_synth.rpt new file mode 100644 index 0000000..b99cde2 --- /dev/null +++ b/Exp8-2/Exp8-2.runs/synth_1/date_display_utilization_synth.rpt @@ -0,0 +1,171 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Mon Dec 16 19:20:53 2024 +| Host : W10-20240912132 running 64-bit major release (build 9200) +| Command : report_utilization -file date_display_utilization_synth.rpt -pb date_display_utilization_synth.pb +| Design : date_display +| Device : 7a35tcsg324-1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 0 | 0 | 20800 | 0.00 | +| LUT as Logic | 0 | 0 | 20800 | 0.00 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 1 | 0 | 41600 | <0.01 | +| Register as Flip Flop | 1 | 0 | 41600 | <0.01 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 1 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 18 | 0 | 210 | 8.57 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 16 | IO | +| IBUF | 2 | IO | +| FDPE | 1 | Flop & Latch | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Exp8-2/Exp8-2.runs/synth_1/gen_run.xml b/Exp8-2/Exp8-2.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..3c8d7a3 --- /dev/null +++ b/Exp8-2/Exp8-2.runs/synth_1/gen_run.xml @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp8-2/Exp8-2.runs/synth_1/htr.txt b/Exp8-2/Exp8-2.runs/synth_1/htr.txt new file mode 100644 index 0000000..ed808b9 --- /dev/null +++ b/Exp8-2/Exp8-2.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log date_display.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source date_display.tcl diff --git a/Exp8-2/Exp8-2.runs/synth_1/vivado.jou b/Exp8-2/Exp8-2.runs/synth_1/vivado.jou new file mode 100644 index 0000000..48e9f9f --- /dev/null +++ b/Exp8-2/Exp8-2.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Mon Dec 16 19:20:39 2024 +# Process ID: 20280 +# Current directory: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1 +# Command line: vivado.exe -log date_display.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source date_display.tcl +# Log file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1/date_display.vds +# Journal file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source date_display.tcl -notrace diff --git a/Exp8-2/Exp8-2.runs/synth_1/vivado.pb b/Exp8-2/Exp8-2.runs/synth_1/vivado.pb new file mode 100644 index 0000000..11eabc7 Binary files /dev/null and b/Exp8-2/Exp8-2.runs/synth_1/vivado.pb differ diff --git a/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v b/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v new file mode 100644 index 0000000..ecb63a9 --- /dev/null +++ b/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v @@ -0,0 +1,127 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/16 18:24:15 +// Design Name: +// Module Name: date_display +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module date_display ( + input wire clk, // 100 MHz clock input + input wire reset, // Reset signal + output reg [7:0] seg, // Segment control for 7-segment display + output reg [7:0] an // Anode control for dynamic display +); + +// State definitions +parameter S0 = 4'd0, S1 = 4'd1, S2 = 4'd2, S3 = 4'd3, + S4 = 4'd4, S5 = 4'd5, S6 = 4'd6, S7 = 4'd7, + S8 = 4'd8, S9 = 4'd9, S10 = 4'd10, S11 = 4'd11, + S12 = 4'd12, S13 = 4'd13, S14 = 4'd14, S15 = 4'd15; + +reg [3:0] state_c, state_n; // Current state and next state +reg [19:0] counter; // Counter for clock division +reg clk_1hz; // 1 Hz clock + +// Segment encoding with dot (decimal point) +parameter [7:0] SEG_0 = 8'b11111101, SEG_1 = 8'b01100001, SEG_2 = 8'b11011011, + SEG_3 = 8'b11110011, SEG_4 = 8'b01100111, SEG_5 = 8'b10110111, + SEG_6 = 8'b10111111, SEG_7 = 8'b11100001, SEG_8 = 8'b11111111, + SEG_9 = 8'b11110111, SEG_DP = 8'b00000001; + +// Time sequence for display +reg [55:0] sequence [15:0]; +initial begin + sequence[S0] = 56'b00000000_00000000_00000000_00000000_00000000_11111101; // 2 + sequence[S1] = 56'b00000000_00000000_00000000_00000000_00000011_01100001; // 20 + sequence[S2] = 56'b00000000_00000000_00000000_00000000_11011011_11110011; // 202 + sequence[S3] = 56'b00000000_00000000_00000000_00000001_11011011_01100001; // 2024. + sequence[S4] = 56'b00000000_00000000_00000000_00001101_10110111_11011011; // 2024.1 + sequence[S5] = 56'b00000000_00000000_00000110_11011011_10111111_10110111; // 2024.12. + sequence[S6] = 56'b00000000_00000000_00001100_11100001_11110011_01100001; // 2024.12.1 + sequence[S7] = 56'b00000000_00000000_11100001_10111111_11011011_11011011; // 2024.12.16 + sequence[S8] = 56'b00000000_00000001_11011011_11011011_11011011_10110111; // 024.12.16 + sequence[S9] = 56'b00000000_00000110_01100001_11100001_11110011_10111111; // 24.12.16 + sequence[S10] = 56'b00000000_00001111_11110111_11111111_01100001_10111111; // 4.12.16 + sequence[S11] = 56'b00000000_11111111_11111111_01100111_11111101_01100001; // 12.16 + sequence[S12] = 56'b11111101_01100001_11111101_01100001_11110111_01100111; // 2.16 + sequence[S13] = 56'b11110111_11111101_11111111_01100001_01100001_01100001; // 16 + sequence[S14] = 56'b00000000_11111101_01100001_00000000_00000000_00000000; // 6 + sequence[S15] = 56'b00000000_00000000_00000000_00000000_00000000_00000000; // Blank +end + +// Clock division to generate 1 Hz clock +always @(posedge clk or posedge reset) begin + if (reset) begin + counter <= 0; + clk_1hz <= 0; + end else begin + if (counter == 20'd999_999) begin + clk_1hz <= ~clk_1hz; + counter <= 0; + end else begin + counter <= counter + 1; + end + end +end + +// State transition logic +always @(posedge clk_1hz or posedge reset) begin + if (reset) begin + state_c <= S0; + end else begin + state_c <= state_n; + end +end + +// Next state logic +always @(*) begin + case (state_c) + S0: state_n = S1; + S1: state_n = S2; + S2: state_n = S3; + S3: state_n = S4; + S4: state_n = S5; + S5: state_n = S6; + S6: state_n = S7; + S7: state_n = S8; + S8: state_n = S9; + S9: state_n = S10; + S10: state_n = S11; + S11: state_n = S12; + S12: state_n = S13; + S13: state_n = S14; + S14: state_n = S15; + S15: state_n = S0; + default: state_n = S0; + endcase +end + +// Output logic for 7-segment display +reg [7:0] seg_temp; +always @(posedge clk or posedge reset) begin + if (reset) begin + seg <= 8'b11111111; + an <= 8'b11111111; + end else begin + seg_temp = sequence[state_c][55:48]; + an <= 8'b11111110; // Activate only one digit (dynamic display) + seg <= seg_temp; + end +end + +endmodule diff --git a/Exp8-2/Exp8-2.xpr b/Exp8-2/Exp8-2.xpr new file mode 100644 index 0000000..390bd52 --- /dev/null +++ b/Exp8-2/Exp8-2.xpr @@ -0,0 +1,136 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Exp8-2/vivado.jou b/Exp8-2/vivado.jou new file mode 100644 index 0000000..b428a7d --- /dev/null +++ b/Exp8-2/vivado.jou @@ -0,0 +1,14 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Wed Dec 18 21:40:31 2024 +# Process ID: 888 +# Current directory: E:/Schoolwork/DigitalLogic/Exp8-2 +# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14032 E:\Schoolwork\DigitalLogic\Exp8-2\Exp8-2.xpr +# Log file: E:/Schoolwork/DigitalLogic/Exp8-2/vivado.log +# Journal file: E:/Schoolwork/DigitalLogic/Exp8-2\vivado.jou +#----------------------------------------------------------- +start_gui +open_project E:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.xpr +update_compile_order -fileset sources_1 diff --git a/Experiment Requirements/绗1娆″疄楠.pdf b/Experiment Requirements/绗1娆″疄楠.pdf new file mode 100644 index 0000000..dcb64cc Binary files /dev/null and b/Experiment Requirements/绗1娆″疄楠.pdf differ diff --git a/Experiment Requirements/绗2娆″疄楠.pdf b/Experiment Requirements/绗2娆″疄楠.pdf new file mode 100644 index 0000000..1ed71d1 Binary files /dev/null and b/Experiment Requirements/绗2娆″疄楠.pdf differ diff --git a/Experiment Requirements/绗3娆″疄楠.pdf b/Experiment Requirements/绗3娆″疄楠.pdf new file mode 100644 index 0000000..c04c129 Binary files /dev/null and b/Experiment Requirements/绗3娆″疄楠.pdf differ diff --git a/Experiment Requirements/绗4娆″疄楠.pdf b/Experiment Requirements/绗4娆″疄楠.pdf new file mode 100644 index 0000000..205f442 Binary files /dev/null and b/Experiment Requirements/绗4娆″疄楠.pdf differ diff --git a/Experiment Requirements/绗5娆 鏃跺簭鐢佃矾璁捐鈥斺旇Е鍙戝櫒.pdf b/Experiment Requirements/绗5娆 鏃跺簭鐢佃矾璁捐鈥斺旇Е鍙戝櫒.pdf new file mode 100644 index 0000000..d8c5913 Binary files /dev/null and b/Experiment Requirements/绗5娆 鏃跺簭鐢佃矾璁捐鈥斺旇Е鍙戝櫒.pdf differ diff --git a/Experiment Requirements/绗6娆 鏃跺簭鐢佃矾璁捐鈥斺旇鏁板櫒涓庡垎棰戝櫒.pdf b/Experiment Requirements/绗6娆 鏃跺簭鐢佃矾璁捐鈥斺旇鏁板櫒涓庡垎棰戝櫒.pdf new file mode 100644 index 0000000..529628b Binary files /dev/null and b/Experiment Requirements/绗6娆 鏃跺簭鐢佃矾璁捐鈥斺旇鏁板櫒涓庡垎棰戝櫒.pdf differ diff --git a/Experiment Requirements/绗7娆 鏃跺簭鐢佃矾璁捐鈥斺旂Щ浣嶅瘎瀛樺櫒.pdf b/Experiment Requirements/绗7娆 鏃跺簭鐢佃矾璁捐鈥斺旂Щ浣嶅瘎瀛樺櫒.pdf new file mode 100644 index 0000000..e7e6006 Binary files /dev/null and b/Experiment Requirements/绗7娆 鏃跺簭鐢佃矾璁捐鈥斺旂Щ浣嶅瘎瀛樺櫒.pdf differ diff --git a/Experiment Requirements/绗8娆 鏃跺簭鐢佃矾璁捐鈥斺旂姸鎬佹満鍙婂叾搴旂敤.pdf b/Experiment Requirements/绗8娆 鏃跺簭鐢佃矾璁捐鈥斺旂姸鎬佹満鍙婂叾搴旂敤.pdf new file mode 100644 index 0000000..23599ca Binary files /dev/null and b/Experiment Requirements/绗8娆 鏃跺簭鐢佃矾璁捐鈥斺旂姸鎬佹満鍙婂叾搴旂敤.pdf differ diff --git a/Reports/2330110900锛堝疄楠1锛夌墿鑱旂綉234-寮犻【鐨.docx b/Reports/2330110900锛堝疄楠1锛夌墿鑱旂綉234-寮犻【鐨.docx new file mode 100644 index 0000000..6652560 Binary files /dev/null and b/Reports/2330110900锛堝疄楠1锛夌墿鑱旂綉234-寮犻【鐨.docx differ diff --git a/Reports/2330110900锛堝疄楠2锛夌墿鑱旂綉234-寮犻【鐨.docx b/Reports/2330110900锛堝疄楠2锛夌墿鑱旂綉234-寮犻【鐨.docx new file mode 100644 index 0000000..b6d97cf Binary files /dev/null and b/Reports/2330110900锛堝疄楠2锛夌墿鑱旂綉234-寮犻【鐨.docx differ diff --git a/Reports/2330110900锛堝疄楠3锛夌墿鑱旂綉234-寮犻【鐨.docx b/Reports/2330110900锛堝疄楠3锛夌墿鑱旂綉234-寮犻【鐨.docx new file mode 100644 index 0000000..dfa920f Binary files /dev/null and b/Reports/2330110900锛堝疄楠3锛夌墿鑱旂綉234-寮犻【鐨.docx differ diff --git a/Reports/2330110900锛堝疄楠4锛夌墿鑱旂綉234-寮犻【鐨.docx b/Reports/2330110900锛堝疄楠4锛夌墿鑱旂綉234-寮犻【鐨.docx new file mode 100644 index 0000000..161080a Binary files /dev/null and b/Reports/2330110900锛堝疄楠4锛夌墿鑱旂綉234-寮犻【鐨.docx differ diff --git a/Reports/2330110900锛堝疄楠6锛夌墿鑱旂綉234-寮犻【鐨.docx b/Reports/2330110900锛堝疄楠6锛夌墿鑱旂綉234-寮犻【鐨.docx new file mode 100644 index 0000000..14b9ddd Binary files /dev/null and b/Reports/2330110900锛堝疄楠6锛夌墿鑱旂綉234-寮犻【鐨.docx differ diff --git a/Reports/2330110900锛堝疄楠7锛夌墿鑱旂綉234-寮犻【鐨.docx b/Reports/2330110900锛堝疄楠7锛夌墿鑱旂綉234-寮犻【鐨.docx new file mode 100644 index 0000000..161080a Binary files /dev/null and b/Reports/2330110900锛堝疄楠7锛夌墿鑱旂綉234-寮犻【鐨.docx differ diff --git a/test/test.cache/wt/webtalk_pa.xml b/test/test.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..b21b30e --- /dev/null +++ b/test/test.cache/wt/webtalk_pa.xml @@ -0,0 +1,91 @@ + + + + +
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+ + diff --git a/test/test.hw/hw_1/hw.xml b/test/test.hw/hw_1/hw.xml new file mode 100644 index 0000000..677839c --- /dev/null +++ b/test/test.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/test/test.runs/.jobs/vrs_config_1.xml b/test/test.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..26a4daa --- /dev/null +++ b/test/test.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/test/test.runs/.jobs/vrs_config_10.xml b/test/test.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..bc8a57c --- /dev/null +++ b/test/test.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/test/test.runs/.jobs/vrs_config_2.xml b/test/test.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..26a4daa --- /dev/null +++ b/test/test.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/test/test.runs/.jobs/vrs_config_3.xml b/test/test.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..bc8a57c --- /dev/null +++ b/test/test.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/test/test.runs/.jobs/vrs_config_4.xml b/test/test.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..bc8a57c --- /dev/null +++ b/test/test.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/test/test.runs/.jobs/vrs_config_5.xml b/test/test.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..bc8a57c --- /dev/null +++ b/test/test.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/test/test.runs/.jobs/vrs_config_6.xml b/test/test.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..bc8a57c --- /dev/null +++ b/test/test.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/test/test.runs/.jobs/vrs_config_7.xml b/test/test.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..bc8a57c --- /dev/null +++ b/test/test.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/test/test.runs/.jobs/vrs_config_8.xml b/test/test.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..bc8a57c --- /dev/null +++ b/test/test.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/test/test.runs/.jobs/vrs_config_9.xml b/test/test.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..bc8a57c --- /dev/null +++ b/test/test.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/test/test.runs/impl_1/gen_run.xml b/test/test.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..0acabec --- /dev/null +++ b/test/test.runs/impl_1/gen_run.xml @@ -0,0 +1,128 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/test/test.runs/impl_1/htr.txt b/test/test.runs/impl_1/htr.txt new file mode 100644 index 0000000..c3cebaa --- /dev/null +++ b/test/test.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log t_date.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source t_date.tcl -notrace diff --git a/test/test.runs/impl_1/init_design.pb b/test/test.runs/impl_1/init_design.pb new file mode 100644 index 0000000..f8fd237 Binary files /dev/null and b/test/test.runs/impl_1/init_design.pb differ diff --git a/test/test.runs/impl_1/opt_design.pb b/test/test.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..637421e Binary files /dev/null and b/test/test.runs/impl_1/opt_design.pb differ diff --git a/test/test.runs/impl_1/place_design.pb b/test/test.runs/impl_1/place_design.pb new file mode 100644 index 0000000..a85e09e Binary files /dev/null and b/test/test.runs/impl_1/place_design.pb differ diff --git a/test/test.runs/impl_1/route_design.pb b/test/test.runs/impl_1/route_design.pb new file mode 100644 index 0000000..70f4867 Binary files /dev/null and b/test/test.runs/impl_1/route_design.pb differ diff --git a/test/test.runs/impl_1/route_report_bus_skew_0.rpt b/test/test.runs/impl_1/route_report_bus_skew_0.rpt new file mode 100644 index 0000000..43b991d --- /dev/null +++ b/test/test.runs/impl_1/route_report_bus_skew_0.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 19 03:43:36 2024 +| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +| Design : t_date +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/test/test.runs/impl_1/t_date.tcl b/test/test.runs/impl_1/t_date.tcl new file mode 100644 index 0000000..4f9f0cb --- /dev/null +++ b/test/test.runs/impl_1/t_date.tcl @@ -0,0 +1,170 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param xicom.use_bs_reader 1 + create_project -in_memory -part xc7a35tcsg324-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir Z:/Storage/Schoolwork/DigitalLogic/test/test.cache/wt [current_project] + set_property parent.project_path Z:/Storage/Schoolwork/DigitalLogic/test/test.xpr [current_project] + set_property ip_output_repo Z:/Storage/Schoolwork/DigitalLogic/test/test.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1/t_date.dcp + read_xdc Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc + link_design -top t_date -part xc7a35tcsg324-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force t_date_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file t_date_drc_opted.rpt -pb t_date_drc_opted.pb -rpx t_date_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force t_date_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file t_date_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file t_date_utilization_placed.rpt -pb t_date_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file t_date_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force t_date_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file t_date_drc_routed.rpt -pb t_date_drc_routed.pb -rpx t_date_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file t_date_methodology_drc_routed.rpt -pb t_date_methodology_drc_routed.pb -rpx t_date_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file t_date_power_routed.rpt -pb t_date_power_summary_routed.pb -rpx t_date_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file t_date_route_status.rpt -pb t_date_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file t_date_timing_summary_routed.rpt -pb t_date_timing_summary_routed.pb -rpx t_date_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file t_date_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file t_date_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force t_date_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force t_date.mmi } + write_bitstream -force t_date.bit + catch {write_debug_probes -quiet -force t_date} + catch {file copy -force t_date.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/test/test.runs/impl_1/t_date.vdi b/test/test.runs/impl_1/t_date.vdi new file mode 100644 index 0000000..4f9001b --- /dev/null +++ b/test/test.runs/impl_1/t_date.vdi @@ -0,0 +1,448 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 19 03:42:56 2024 +# Process ID: 4648 +# Current directory: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1 +# Command line: vivado.exe -log t_date.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source t_date.tcl -notrace +# Log file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date.vdi +# Journal file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source t_date.tcl -notrace +Command: link_design -top t_date -part xc7a35tcsg324-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc] +Finished Parsing XDC File [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 607.418 ; gain = 303.824 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.400 . Memory (MB): peak = 620.312 ; gain = 12.895 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 18d814d52 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1176.613 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 18d814d52 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1176.613 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 17c495346 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1176.613 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 4 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 17c495346 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1176.613 ; gain = 0.000 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 17c495346 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1176.613 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 17c495346 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1176.613 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1176.613 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 17c495346 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1176.613 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1aa1fde4e + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1176.613 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1176.613 ; gain = 569.195 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 1176.613 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file t_date_drc_opted.rpt -pb t_date_drc_opted.pb -rpx t_date_drc_opted.rpx +Command: report_drc -file t_date_drc_opted.rpt -pb t_date_drc_opted.pb -rpx t_date_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1176.613 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11bcdb05b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1176.613 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1186.355 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 132ecb1d1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.428 . Memory (MB): peak = 1186.641 ; gain = 10.027 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1e29ea11a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.444 . Memory (MB): peak = 1186.641 ; gain = 10.027 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1e29ea11a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.447 . Memory (MB): peak = 1186.641 ; gain = 10.027 +Phase 1 Placer Initialization | Checksum: 1e29ea11a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.448 . Memory (MB): peak = 1186.641 ; gain = 10.027 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 1e28c9cd9 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.900 . Memory (MB): peak = 1186.641 ; gain = 10.027 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1e28c9cd9 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.904 . Memory (MB): peak = 1186.641 ; gain = 10.027 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 190206097 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.915 . Memory (MB): peak = 1186.641 ; gain = 10.027 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1c28d7624 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.921 . Memory (MB): peak = 1186.641 ; gain = 10.027 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1c28d7624 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.923 . Memory (MB): peak = 1186.641 ; gain = 10.027 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: f59e06de + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.998 . Memory (MB): peak = 1186.641 ; gain = 10.027 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: f59e06de + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: f59e06de + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027 +Phase 3 Detail Placement | Checksum: f59e06de + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: f59e06de + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: f59e06de + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: f59e06de + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1328a0f4c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1328a0f4c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027 +Ending Placer Task | Checksum: 112c44b50 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1186.641 ; gain = 10.027 +INFO: [Common 17-83] Releasing license: Implementation +43 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.083 . Memory (MB): peak = 1186.641 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file t_date_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1189.730 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file t_date_utilization_placed.rpt -pb t_date_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1189.730 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file t_date_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1189.730 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 853bba8c ConstDB: 0 ShapeSum: 8d8890c4 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 153020e02 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1304.508 ; gain = 114.777 +Post Restoration Checksum: NetGraph: 60f072d5 NumContArr: f2119b2d Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 153020e02 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1310.535 ; gain = 120.805 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 153020e02 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1310.535 ; gain = 120.805 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: e28d9f17 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: c4b27c83 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 5960c0ac + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684 +Phase 4 Rip-up And Reroute | Checksum: 5960c0ac + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 5960c0ac + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 5960c0ac + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684 +Phase 6 Post Hold Fix | Checksum: 5960c0ac + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0249542 % + Global Horizontal Routing Utilization = 0.0217335 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 18.018%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 33.3333%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 19.1176%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 7.35294%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 5960c0ac + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1315.414 ; gain = 125.684 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 5960c0ac + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1316.297 ; gain = 126.566 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 12e8767c6 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1316.297 ; gain = 126.566 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1316.297 ; gain = 126.566 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1316.297 ; gain = 126.566 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.081 . Memory (MB): peak = 1316.535 ; gain = 0.238 +INFO: [Common 17-1381] The checkpoint 'Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file t_date_drc_routed.rpt -pb t_date_drc_routed.pb -rpx t_date_drc_routed.rpx +Command: report_drc -file t_date_drc_routed.rpt -pb t_date_drc_routed.pb -rpx t_date_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file t_date_methodology_drc_routed.rpt -pb t_date_methodology_drc_routed.pb -rpx t_date_methodology_drc_routed.rpx +Command: report_methodology -file t_date_methodology_drc_routed.rpt -pb t_date_methodology_drc_routed.pb -rpx t_date_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file t_date_power_routed.rpt -pb t_date_power_summary_routed.pb -rpx t_date_power_routed.rpx +Command: report_power -file t_date_power_routed.rpt -pb t_date_power_summary_routed.pb -rpx t_date_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +68 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file t_date_route_status.rpt -pb t_date_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file t_date_timing_summary_routed.rpt -pb t_date_timing_summary_routed.pb -rpx t_date_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file t_date_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file t_date_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force t_date.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./t_date.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +86 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1750.367 ; gain = 399.805 +INFO: [Common 17-206] Exiting Vivado at Thu Dec 19 03:43:44 2024... diff --git a/test/test.runs/impl_1/t_date_clock_utilization_routed.rpt b/test/test.runs/impl_1/t_date_clock_utilization_routed.rpt new file mode 100644 index 0000000..5efd2e8 --- /dev/null +++ b/test/test.runs/impl_1/t_date_clock_utilization_routed.rpt @@ -0,0 +1,160 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 19 03:43:36 2024 +| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file t_date_clock_utilization_routed.rpt +| Design : t_date +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +------------------------------------------------------------------------------------ + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Local Clock Details +5. Clock Regions: Key Resource Utilization +6. Clock Regions : Global Clock Summary +7. Device Cell Placement Summary for Global Clock g0 +8. Clock Region Cell Placement per Global Clock: Region X1Y1 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 40 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | IOB_X0Y26 | IOB_X0Y26 | X0Y0 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Local Clock Details +---------------------- + ++----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+--------------------+----------------------------------+ +| Local Id | Driver Type/Pin | Constraint | Site/BEL | Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+--------------------+----------------------------------|| +| 0 | FDCE/Q | None | SLICE_X60Y70/AFF | X1Y1 | 22 | 1 | | | U1/clk_20kHZ_reg/Q | U1/CLK - Static - +| 1 | FDCE/Q | None | SLICE_X62Y68/AFF | X1Y1 | 3 | 1 | | | U1/clk_1HZ_reg/Q | U1/FSM_sequential_state_c_reg[2] - Static - ++----------+-----------------+------------+------------------+--------------+-------------+-----------------+--------------+-------+--------------------+----------------------------------|| +* Local Clocks in this context represents only clocks driven by non-global buffers +** Clock Loads column represents the clock pin loads (pin count) +*** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +5. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 65 | 1500 | 34 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +6. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 1 | +| Y0 | 0 | 0 | ++----+----+----+ + + +7. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | | | | 40 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+-----+ +| | X0 | X1 | ++----+----+-----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 40 | +| Y0 | 0 | 0 | ++----+----+-----+ + + +8. Clock Region Cell Placement per Global Clock: Region X1Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 40 | 0 | 40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y26 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} +#endgroup diff --git a/test/test.runs/impl_1/t_date_control_sets_placed.rpt b/test/test.runs/impl_1/t_date_control_sets_placed.rpt new file mode 100644 index 0000000..993edb7 --- /dev/null +++ b/test/test.runs/impl_1/t_date_control_sets_placed.rpt @@ -0,0 +1,72 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 19 03:43:21 2024 +| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file t_date_control_sets_placed.rpt +| Design : t_date +| Device : xc7a35t +------------------------------------------------------------------------------------ + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 5 | +| Unused register locations in slices containing registers | 7 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ +| 3 | 1 | +| 6 | 1 | +| 8 | 2 | +| 16+ | 1 | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 43 | 12 | +| No | Yes | No | 8 | 3 | +| Yes | No | No | 14 | 4 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++-----------------------------------+-----------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++-----------------------------------+-----------------+------------------+------------------+----------------+ +| U1/FSM_sequential_state_c_reg[2] | | rst_IBUF | 2 | 3 | +| U1/CLK | a_h1[7]_i_1_n_0 | | 1 | 6 | +| U1/CLK | | rst_IBUF | 3 | 8 | +| U1/CLK | a_h2[7]_i_1_n_0 | | 3 | 8 | +| clk_IBUF_BUFG | | rst_IBUF | 10 | 40 | ++-----------------------------------+-----------------+------------------+------------------+----------------+ + + diff --git a/test/test.runs/impl_1/t_date_drc_opted.pb b/test/test.runs/impl_1/t_date_drc_opted.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/test/test.runs/impl_1/t_date_drc_opted.pb differ diff --git a/test/test.runs/impl_1/t_date_drc_opted.rpt b/test/test.runs/impl_1/t_date_drc_opted.rpt new file mode 100644 index 0000000..a7a99a2 --- /dev/null +++ b/test/test.runs/impl_1/t_date_drc_opted.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 19 03:43:19 2024 +| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200) +| Command : report_drc -file t_date_drc_opted.rpt -pb t_date_drc_opted.pb -rpx t_date_drc_opted.rpx +| Design : t_date +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/test/test.runs/impl_1/t_date_drc_routed.pb b/test/test.runs/impl_1/t_date_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/test/test.runs/impl_1/t_date_drc_routed.pb differ diff --git a/test/test.runs/impl_1/t_date_drc_routed.rpt b/test/test.runs/impl_1/t_date_drc_routed.rpt new file mode 100644 index 0000000..c037d11 --- /dev/null +++ b/test/test.runs/impl_1/t_date_drc_routed.rpt @@ -0,0 +1,49 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 19 03:43:35 2024 +| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200) +| Command : report_drc -file t_date_drc_routed.rpt -pb t_date_drc_routed.pb -rpx t_date_drc_routed.rpx +| Design : t_date +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/test/test.runs/impl_1/t_date_io_placed.rpt b/test/test.runs/impl_1/t_date_io_placed.rpt new file mode 100644 index 0000000..3c3805a --- /dev/null +++ b/test/test.runs/impl_1/t_date_io_placed.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 19 03:43:21 2024 +| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200) +| Command : report_io -file t_date_io_placed.rpt +| Design : t_date +| Device : xc7a35t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2013-12-19 +| Package Pin Delay Version : VERS. 2.0 2013-12-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 26 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | a_h1[3] | High Range | IO_L9N_T1_DQS_AD7N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | a_h1[5] | High Range | IO_L8N_T1_AD14N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A4 | a_h1[6] | High Range | IO_L8P_T1_AD14P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | a_h1[4] | High Range | IO_L9P_T1_DQS_AD7P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B2 | a_h1[1] | High Range | IO_L10N_T1_AD15N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B3 | a_h1[2] | High Range | IO_L10P_T1_AD15P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B4 | a_h1[7] | High Range | IO_L7N_T1_AD6N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | an[5] | High Range | IO_L16N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C2 | an[6] | High Range | IO_L16P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | a_h2[1] | High Range | IO_L14N_T2_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D3 | a_h2[5] | High Range | IO_L12N_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D4 | a_h2[7] | High Range | IO_L11N_T1_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D5 | a_h1[0] | High Range | IO_L11P_T1_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | an[1] | High Range | IO_L18N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E2 | a_h2[2] | High Range | IO_L14P_T2_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E3 | a_h2[6] | High Range | IO_L12P_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | an[2] | High Range | IO_L18P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | a_h2[3] | High Range | IO_L13N_T2_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F4 | a_h2[4] | High Range | IO_L13P_T2_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | an[3] | High Range | IO_L17N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G2 | an[7] | High Range | IO_L15N_T2_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | an[0] | High Range | IO_L19P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | an[4] | High Range | IO_L17P_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| H2 | a_h2[0] | High Range | IO_L15P_T2_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| N4 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| P3 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P4 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P5 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P17 | clk | High Range | IO_L12P_T1_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R2 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | rst | High Range | IO_L13N_T2_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/test/test.runs/impl_1/t_date_methodology_drc_routed.pb b/test/test.runs/impl_1/t_date_methodology_drc_routed.pb new file mode 100644 index 0000000..184b98b Binary files /dev/null and b/test/test.runs/impl_1/t_date_methodology_drc_routed.pb differ diff --git a/test/test.runs/impl_1/t_date_methodology_drc_routed.rpt b/test/test.runs/impl_1/t_date_methodology_drc_routed.rpt new file mode 100644 index 0000000..63c18a1 --- /dev/null +++ b/test/test.runs/impl_1/t_date_methodology_drc_routed.rpt @@ -0,0 +1,360 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 19 03:43:35 2024 +| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200) +| Command : report_methodology -file t_date_methodology_drc_routed.rpt -pb t_date_methodology_drc_routed.pb -rpx t_date_methodology_drc_routed.rpx +| Design : t_date +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 65 ++-----------+----------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------+------------+ +| TIMING-17 | Warning | Non-clocked sequential cell | 65 | ++-----------+----------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Warning +Non-clocked sequential cell +The clock pin FSM_sequential_state_c_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Warning +Non-clocked sequential cell +The clock pin FSM_sequential_state_c_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Warning +Non-clocked sequential cell +The clock pin FSM_sequential_state_c_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Warning +Non-clocked sequential cell +The clock pin U1/clk_1HZ_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#5 Warning +Non-clocked sequential cell +The clock pin U1/clk_20kHZ_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#6 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#7 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#8 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#9 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#10 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[13]/C is not reached by a timing clock +Related violations: + +TIMING-17#11 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[14]/C is not reached by a timing clock +Related violations: + +TIMING-17#12 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[15]/C is not reached by a timing clock +Related violations: + +TIMING-17#13 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[16]/C is not reached by a timing clock +Related violations: + +TIMING-17#14 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[17]/C is not reached by a timing clock +Related violations: + +TIMING-17#15 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[18]/C is not reached by a timing clock +Related violations: + +TIMING-17#16 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[19]/C is not reached by a timing clock +Related violations: + +TIMING-17#17 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#18 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[20]/C is not reached by a timing clock +Related violations: + +TIMING-17#19 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[21]/C is not reached by a timing clock +Related violations: + +TIMING-17#20 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[22]/C is not reached by a timing clock +Related violations: + +TIMING-17#21 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[23]/C is not reached by a timing clock +Related violations: + +TIMING-17#22 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#23 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#24 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#25 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#26 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#27 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#28 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#29 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#30 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#31 Warning +Non-clocked sequential cell +The clock pin U1/counter1_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#32 Warning +Non-clocked sequential cell +The clock pin U1/counter20k_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#33 Warning +Non-clocked sequential cell +The clock pin U1/counter20k_reg[10]/C is not reached by a timing clock +Related violations: + +TIMING-17#34 Warning +Non-clocked sequential cell +The clock pin U1/counter20k_reg[11]/C is not reached by a timing clock +Related violations: + +TIMING-17#35 Warning +Non-clocked sequential cell +The clock pin U1/counter20k_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#36 Warning +Non-clocked sequential cell +The clock pin U1/counter20k_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#37 Warning +Non-clocked sequential cell +The clock pin U1/counter20k_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#38 Warning +Non-clocked sequential cell +The clock pin U1/counter20k_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#39 Warning +Non-clocked sequential cell +The clock pin U1/counter20k_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#40 Warning +Non-clocked sequential cell +The clock pin U1/counter20k_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#41 Warning +Non-clocked sequential cell +The clock pin U1/counter20k_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#42 Warning +Non-clocked sequential cell +The clock pin U1/counter20k_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#43 Warning +Non-clocked sequential cell +The clock pin U1/counter20k_reg[9]/C is not reached by a timing clock +Related violations: + +TIMING-17#44 Warning +Non-clocked sequential cell +The clock pin a_h1_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#45 Warning +Non-clocked sequential cell +The clock pin a_h1_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#46 Warning +Non-clocked sequential cell +The clock pin a_h1_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#47 Warning +Non-clocked sequential cell +The clock pin a_h1_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#48 Warning +Non-clocked sequential cell +The clock pin a_h1_reg[7]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#49 Warning +Non-clocked sequential cell +The clock pin a_h1_reg[7]_lopt_replica_2/C is not reached by a timing clock +Related violations: + +TIMING-17#50 Warning +Non-clocked sequential cell +The clock pin a_h2_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#51 Warning +Non-clocked sequential cell +The clock pin a_h2_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#52 Warning +Non-clocked sequential cell +The clock pin a_h2_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#53 Warning +Non-clocked sequential cell +The clock pin a_h2_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#54 Warning +Non-clocked sequential cell +The clock pin a_h2_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#55 Warning +Non-clocked sequential cell +The clock pin a_h2_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#56 Warning +Non-clocked sequential cell +The clock pin a_h2_reg[7]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#57 Warning +Non-clocked sequential cell +The clock pin a_h2_reg[7]_lopt_replica_2/C is not reached by a timing clock +Related violations: + +TIMING-17#58 Warning +Non-clocked sequential cell +The clock pin an_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#59 Warning +Non-clocked sequential cell +The clock pin an_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#60 Warning +Non-clocked sequential cell +The clock pin an_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#61 Warning +Non-clocked sequential cell +The clock pin an_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#62 Warning +Non-clocked sequential cell +The clock pin an_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#63 Warning +Non-clocked sequential cell +The clock pin an_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#64 Warning +Non-clocked sequential cell +The clock pin an_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#65 Warning +Non-clocked sequential cell +The clock pin an_reg[7]/C is not reached by a timing clock +Related violations: + + diff --git a/test/test.runs/impl_1/t_date_opt.dcp b/test/test.runs/impl_1/t_date_opt.dcp new file mode 100644 index 0000000..1b25dd4 Binary files /dev/null and b/test/test.runs/impl_1/t_date_opt.dcp differ diff --git a/test/test.runs/impl_1/t_date_placed.dcp b/test/test.runs/impl_1/t_date_placed.dcp new file mode 100644 index 0000000..6685924 Binary files /dev/null and b/test/test.runs/impl_1/t_date_placed.dcp differ diff --git a/test/test.runs/impl_1/t_date_power_routed.rpt b/test/test.runs/impl_1/t_date_power_routed.rpt new file mode 100644 index 0000000..d12f561 --- /dev/null +++ b/test/test.runs/impl_1/t_date_power_routed.rpt @@ -0,0 +1,145 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 19 03:43:36 2024 +| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200) +| Command : report_power -file t_date_power_routed.rpt -pb t_date_power_summary_routed.pb -rpx t_date_power_routed.rpx +| Design : t_date +| Device : xc7a35tcsg324-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 10.151 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 10.016 | +| Device Static (W) | 0.136 | +| Effective TJA (C/W) | 4.8 | +| Max Ambient (C) | 36.5 | +| Junction Temperature (C) | 73.5 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.617 | 163 | --- | --- | +| LUT as Logic | 0.552 | 63 | 20800 | 0.30 | +| Register | 0.030 | 65 | 41600 | 0.16 | +| CARRY4 | 0.029 | 10 | 8150 | 0.12 | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| Others | 0.000 | 4 | --- | --- | +| Signals | 0.505 | 137 | --- | --- | +| I/O | 8.894 | 26 | 210 | 12.38 | +| Static Power | 0.136 | | | | +| Total | 10.151 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 1.188 | 1.126 | 0.062 | +| Vccaux | 1.800 | 0.344 | 0.326 | 0.018 | +| Vcco33 | 3.300 | 2.517 | 2.516 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.8 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++--------+-----------+ +| Name | Power (W) | ++--------+-----------+ +| t_date | 10.016 | +| U1 | 0.473 | ++--------+-----------+ + + diff --git a/test/test.runs/impl_1/t_date_power_summary_routed.pb b/test/test.runs/impl_1/t_date_power_summary_routed.pb new file mode 100644 index 0000000..ced49c9 Binary files /dev/null and b/test/test.runs/impl_1/t_date_power_summary_routed.pb differ diff --git a/test/test.runs/impl_1/t_date_route_status.pb b/test/test.runs/impl_1/t_date_route_status.pb new file mode 100644 index 0000000..8c5ef58 Binary files /dev/null and b/test/test.runs/impl_1/t_date_route_status.pb differ diff --git a/test/test.runs/impl_1/t_date_route_status.rpt b/test/test.runs/impl_1/t_date_route_status.rpt new file mode 100644 index 0000000..2374393 --- /dev/null +++ b/test/test.runs/impl_1/t_date_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 223 : + # of nets not needing routing.......... : 84 : + # of internally routed nets........ : 84 : + # of routable nets..................... : 139 : + # of fully routed nets............. : 139 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/test/test.runs/impl_1/t_date_routed.dcp b/test/test.runs/impl_1/t_date_routed.dcp new file mode 100644 index 0000000..58d8562 Binary files /dev/null and b/test/test.runs/impl_1/t_date_routed.dcp differ diff --git a/test/test.runs/impl_1/t_date_timing_summary_routed.pb b/test/test.runs/impl_1/t_date_timing_summary_routed.pb new file mode 100644 index 0000000..4526e93 --- /dev/null +++ b/test/test.runs/impl_1/t_date_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/test/test.runs/impl_1/t_date_timing_summary_routed.rpt b/test/test.runs/impl_1/t_date_timing_summary_routed.rpt new file mode 100644 index 0000000..fce0745 --- /dev/null +++ b/test/test.runs/impl_1/t_date_timing_summary_routed.rpt @@ -0,0 +1,177 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 19 03:43:36 2024 +| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file t_date_timing_summary_routed.rpt -pb t_date_timing_summary_routed.pb -rpx t_date_timing_summary_routed.rpx -warn_on_violation +| Design : t_date +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.21 2018-02-08 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 40 register/latch pins with no clock driven by root clock pin: clk (HIGH) + + There are 3 register/latch pins with no clock driven by root clock pin: U1/clk_1HZ_reg/Q (HIGH) + + There are 22 register/latch pins with no clock driven by root clock pin: U1/clk_20kHZ_reg/Q (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 130 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There is 1 input port with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 22 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/test/test.runs/impl_1/t_date_utilization_placed.pb b/test/test.runs/impl_1/t_date_utilization_placed.pb new file mode 100644 index 0000000..a48827f Binary files /dev/null and b/test/test.runs/impl_1/t_date_utilization_placed.pb differ diff --git a/test/test.runs/impl_1/t_date_utilization_placed.rpt b/test/test.runs/impl_1/t_date_utilization_placed.rpt new file mode 100644 index 0000000..62d6849 --- /dev/null +++ b/test/test.runs/impl_1/t_date_utilization_placed.rpt @@ -0,0 +1,207 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 19 03:43:21 2024 +| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200) +| Command : report_utilization -file t_date_utilization_placed.rpt -pb t_date_utilization_placed.pb +| Design : t_date +| Device : 7a35tcsg324-1 +| Design State : Fully Placed +--------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 63 | 0 | 20800 | 0.30 | +| LUT as Logic | 63 | 0 | 20800 | 0.30 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 65 | 0 | 41600 | 0.16 | +| Register as Flip Flop | 65 | 0 | 41600 | 0.16 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 43 | Yes | - | Reset | +| 1 | Yes | Set | - | +| 21 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 29 | 0 | 8150 | 0.36 | +| SLICEL | 20 | 0 | | | +| SLICEM | 9 | 0 | | | +| LUT as Logic | 63 | 0 | 20800 | 0.30 | +| using O5 output only | 0 | | | | +| using O6 output only | 43 | | | | +| using O5 and O6 | 20 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 39 | 0 | 20800 | 0.19 | +| fully used LUT-FF pairs | 19 | | | | +| LUT-FF pairs with one unused LUT output | 20 | | | | +| LUT-FF pairs with one unused Flip Flop | 15 | | | | +| Unique Control Sets | 5 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 26 | 26 | 210 | 12.38 | +| IOB Master Pads | 13 | | | | +| IOB Slave Pads | 13 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDCE | 43 | Flop & Latch | +| LUT2 | 41 | LUT | +| OBUF | 24 | IO | +| FDRE | 21 | Flop & Latch | +| LUT6 | 18 | LUT | +| CARRY4 | 10 | CarryLogic | +| LUT4 | 9 | LUT | +| LUT5 | 7 | LUT | +| LUT3 | 5 | LUT | +| LUT1 | 3 | LUT | +| IBUF | 2 | IO | +| FDSE | 1 | Flop & Latch | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/test/test.runs/impl_1/usage_statistics_webtalk.xml b/test/test.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..9237471 --- /dev/null +++ b/test/test.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,631 @@ + + +
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+ diff --git a/test/test.runs/impl_1/vivado.jou b/test/test.runs/impl_1/vivado.jou new file mode 100644 index 0000000..cfa0a27 --- /dev/null +++ b/test/test.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 19 03:42:56 2024 +# Process ID: 4648 +# Current directory: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1 +# Command line: vivado.exe -log t_date.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source t_date.tcl -notrace +# Log file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1/t_date.vdi +# Journal file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source t_date.tcl -notrace diff --git a/test/test.runs/impl_1/vivado.pb b/test/test.runs/impl_1/vivado.pb new file mode 100644 index 0000000..7c34215 Binary files /dev/null and b/test/test.runs/impl_1/vivado.pb differ diff --git a/test/test.runs/impl_1/write_bitstream.pb b/test/test.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..104720c Binary files /dev/null and b/test/test.runs/impl_1/write_bitstream.pb differ diff --git a/test/test.runs/synth_1/.Xil/t_date_propImpl.xdc b/test/test.runs/synth_1/.Xil/t_date_propImpl.xdc new file mode 100644 index 0000000..336ace6 --- /dev/null +++ b/test/test.runs/synth_1/.Xil/t_date_propImpl.xdc @@ -0,0 +1,53 @@ +set_property SRC_FILE_INFO {cfile:Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc rfile:../../../test.srcs/constrs_1/imports/Downloads/EX1.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN P17 [get_ports clk] +set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN R15 [get_ports rst] +set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B4 [get_ports {a_h1[7]}] +set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN A4 [get_ports {a_h1[6]}] +set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN A3 [get_ports {a_h1[5]}] +set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B1 [get_ports {a_h1[4]}] +set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN A1 [get_ports {a_h1[3]}] +set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B3 [get_ports {a_h1[2]}] +set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN B2 [get_ports {a_h1[1]}] +set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D5 [get_ports {a_h1[0]}] +set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D4 [get_ports {a_h2[7]}] +set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E3 [get_ports {a_h2[6]}] +set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D3 [get_ports {a_h2[5]}] +set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F4 [get_ports {a_h2[4]}] +set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F3 [get_ports {a_h2[3]}] +set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E2 [get_ports {a_h2[2]}] +set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN D2 [get_ports {a_h2[1]}] +set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN H2 [get_ports {a_h2[0]}] +set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G2 [get_ports {an[7]}] +set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN C2 [get_ports {an[6]}] +set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN C1 [get_ports {an[5]}] +set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN H1 [get_ports {an[4]}] +set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G1 [get_ports {an[3]}] +set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN F1 [get_ports {an[2]}] +set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN E1 [get_ports {an[1]}] +set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN G6 [get_ports {an[0]}] diff --git a/test/test.runs/synth_1/gen_run.xml b/test/test.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..7699e18 --- /dev/null +++ b/test/test.runs/synth_1/gen_run.xml @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/test/test.runs/synth_1/htr.txt b/test/test.runs/synth_1/htr.txt new file mode 100644 index 0000000..acae085 --- /dev/null +++ b/test/test.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log t_date.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source t_date.tcl diff --git a/test/test.runs/synth_1/t_date.dcp b/test/test.runs/synth_1/t_date.dcp new file mode 100644 index 0000000..dd9d6cc Binary files /dev/null and b/test/test.runs/synth_1/t_date.dcp differ diff --git a/test/test.runs/synth_1/t_date.tcl b/test/test.runs/synth_1/t_date.tcl new file mode 100644 index 0000000..7a4464b --- /dev/null +++ b/test/test.runs/synth_1/t_date.tcl @@ -0,0 +1,57 @@ +# +# Synthesis run script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param xicom.use_bs_reader 1 +create_project -in_memory -part xc7a35tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir Z:/Storage/Schoolwork/DigitalLogic/test/test.cache/wt [current_project] +set_property parent.project_path Z:/Storage/Schoolwork/DigitalLogic/test/test.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo z:/Storage/Schoolwork/DigitalLogic/test/test.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib { + Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/slow.v + Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v +} +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc +set_property used_in_implementation false [get_files Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc] + +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top t_date -part xc7a35tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef t_date.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file t_date_utilization_synth.rpt -pb t_date_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/test/test.runs/synth_1/t_date.vds b/test/test.runs/synth_1/t_date.vds new file mode 100644 index 0000000..9bca4b1 --- /dev/null +++ b/test/test.runs/synth_1/t_date.vds @@ -0,0 +1,403 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 19 03:42:19 2024 +# Process ID: 3132 +# Current directory: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1 +# Command line: vivado.exe -log t_date.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source t_date.tcl +# Log file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1/t_date.vds +# Journal file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source t_date.tcl -notrace +Command: synth_design -top t_date -part xc7a35tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 692 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 407.832 ; gain = 96.258 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 't_date' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:23] + Parameter y0 bound to: 4'b0000 + Parameter y1 bound to: 4'b0001 + Parameter y2 bound to: 4'b0010 + Parameter y3 bound to: 4'b0011 + Parameter y4 bound to: 4'b0100 + Parameter y5 bound to: 4'b0101 + Parameter y6 bound to: 4'b0110 + Parameter y7 bound to: 4'b0111 +INFO: [Synth 8-6157] synthesizing module 'clk' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/slow.v:23] + Parameter sys_clk bound to: 100000000 - type: integer + Parameter clk_out1 bound to: 1 - type: integer + Parameter clk_out20k bound to: 20000 - type: integer + Parameter max1 bound to: 49999999 - type: integer + Parameter max20k bound to: 2499 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'clk' (1#1) [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/slow.v:23] +INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:38] +INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:57] +INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:63] +INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:70] +INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:78] +INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:87] +INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:97] +INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:108] +INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:52] +INFO: [Synth 8-6155] done synthesizing module 't_date' (2#1) [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:23] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 463.461 ; gain = 151.887 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 463.461 ; gain = 151.887 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 463.461 ; gain = 151.887 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc] +Finished Parsing XDC File [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/t_date_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/t_date_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 788.133 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5545] ROM "clk_1HZ" won't be mapped to RAM because address size (26) is larger than maximum supported(25) +INFO: [Synth 8-5546] ROM "clk_20kHZ" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-802] inferred FSM for state register 'state_c_reg' in module 't_date' +INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5544] ROM "an" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +INFO: [Synth 8-5544] ROM "state_n" won't be mapped to Block RAM because address size (4) smaller than threshold (5) +WARNING: [Synth 8-327] inferring latch for variable 'FSM_sequential_state_n_reg' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:39] +WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_state_n_reg' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:39] +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + iSTATE | 000 | 0000 + iSTATE0 | 001 | 0001 + iSTATE1 | 010 | 0010 + iSTATE2 | 011 | 0011 + iSTATE3 | 100 | 0100 + iSTATE4 | 101 | 0101 + iSTATE5 | 110 | 0110 + iSTATE6 | 111 | 0111 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_c_reg' using encoding 'sequential' in module 't_date' +WARNING: [Synth 8-327] inferring latch for variable 'FSM_sequential_state_n_reg' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:39] +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 26 Bit Adders := 1 + 2 Input 12 Bit Adders := 1 ++---Registers : + 26 Bit Registers := 1 + 12 Bit Registers := 1 + 8 Bit Registers := 3 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 26 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 6 + 7 Input 8 Bit Muxes := 2 + 8 Input 8 Bit Muxes := 6 + 9 Input 8 Bit Muxes := 2 + 3 Input 8 Bit Muxes := 1 + 4 Input 8 Bit Muxes := 1 + 5 Input 8 Bit Muxes := 1 + 6 Input 8 Bit Muxes := 1 + 8 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 11 + 6 Input 1 Bit Muxes := 2 + 7 Input 1 Bit Muxes := 2 + 8 Input 1 Bit Muxes := 4 + 9 Input 1 Bit Muxes := 2 + 3 Input 1 Bit Muxes := 1 + 4 Input 1 Bit Muxes := 1 + 5 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module t_date +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 3 ++---Muxes : + 2 Input 8 Bit Muxes := 6 + 7 Input 8 Bit Muxes := 2 + 8 Input 8 Bit Muxes := 6 + 9 Input 8 Bit Muxes := 2 + 3 Input 8 Bit Muxes := 1 + 4 Input 8 Bit Muxes := 1 + 5 Input 8 Bit Muxes := 1 + 6 Input 8 Bit Muxes := 1 + 8 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 9 + 6 Input 1 Bit Muxes := 2 + 7 Input 1 Bit Muxes := 2 + 8 Input 1 Bit Muxes := 4 + 9 Input 1 Bit Muxes := 2 + 3 Input 1 Bit Muxes := 1 + 4 Input 1 Bit Muxes := 1 + 5 Input 1 Bit Muxes := 1 +Module clk +Detailed RTL Component Info : ++---Adders : + 2 Input 26 Bit Adders := 1 + 2 Input 12 Bit Adders := 1 ++---Registers : + 26 Bit Registers := 1 + 12 Bit Registers := 1 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 26 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 2 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-5545] ROM "U1/clk_1HZ" won't be mapped to RAM because address size (26) is larger than maximum supported(25) +INFO: [Synth 8-5546] ROM "U1/clk_20kHZ" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-3886] merging instance 'a_h2_reg[3]' (FDE) to 'a_h2_reg[7]' +INFO: [Synth 8-3886] merging instance 'a_h2_reg[4]' (FDE) to 'a_h2_reg[7]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\a_h1_reg[0] ) +INFO: [Synth 8-3886] merging instance 'a_h1_reg[3]' (FDE) to 'a_h1_reg[7]' +INFO: [Synth 8-3886] merging instance 'a_h1_reg[4]' (FDE) to 'a_h1_reg[7]' +INFO: [Synth 8-3333] propagating constant 1 across sequential element (\a_h1_reg[6] ) +WARNING: [Synth 8-3332] Sequential element (FSM_sequential_state_n_reg[2]) is unused and will be removed from module t_date. +WARNING: [Synth 8-3332] Sequential element (FSM_sequential_state_n_reg[1]) is unused and will be removed from module t_date. +WARNING: [Synth 8-3332] Sequential element (FSM_sequential_state_n_reg[0]) is unused and will be removed from module t_date. +WARNING: [Synth 8-3332] Sequential element (a_h1_reg[6]) is unused and will be removed from module t_date. +WARNING: [Synth 8-3332] Sequential element (a_h1_reg[0]) is unused and will be removed from module t_date. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 788.133 ; gain = 476.559 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 788.133 ; gain = 476.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 788.133 ; gain = 476.559 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 807.078 ; gain = 495.504 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 10| +|3 |LUT1 | 3| +|4 |LUT2 | 41| +|5 |LUT3 | 5| +|6 |LUT4 | 9| +|7 |LUT5 | 7| +|8 |LUT6 | 18| +|9 |FDCE | 43| +|10 |FDRE | 17| +|11 |FDSE | 1| +|12 |IBUF | 2| +|13 |OBUF | 24| ++------+-------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 181| +|2 | U1 |clk | 100| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 8 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:06 ; elapsed = 00:00:17 . Memory (MB): peak = 807.078 ; gain = 170.832 +Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +54 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 807.078 ; gain = 508.328 +INFO: [Common 17-1381] The checkpoint 'Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1/t_date.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file t_date_utilization_synth.rpt -pb t_date_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 807.078 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Thu Dec 19 03:42:49 2024... diff --git a/test/test.runs/synth_1/t_date_utilization_synth.pb b/test/test.runs/synth_1/t_date_utilization_synth.pb new file mode 100644 index 0000000..abd1346 Binary files /dev/null and b/test/test.runs/synth_1/t_date_utilization_synth.pb differ diff --git a/test/test.runs/synth_1/t_date_utilization_synth.rpt b/test/test.runs/synth_1/t_date_utilization_synth.rpt new file mode 100644 index 0000000..07027fc --- /dev/null +++ b/test/test.runs/synth_1/t_date_utilization_synth.rpt @@ -0,0 +1,180 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018 +| Date : Thu Dec 19 03:42:49 2024 +| Host : WIN-P8FUKGQFPK3 running 64-bit major release (build 9200) +| Command : report_utilization -file t_date_utilization_synth.rpt -pb t_date_utilization_synth.pb +| Design : t_date +| Device : 7a35tcsg324-1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 63 | 0 | 20800 | 0.30 | +| LUT as Logic | 63 | 0 | 20800 | 0.30 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 61 | 0 | 41600 | 0.15 | +| Register as Flip Flop | 61 | 0 | 41600 | 0.15 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 43 | Yes | - | Reset | +| 1 | Yes | Set | - | +| 17 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 26 | 0 | 210 | 12.38 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDCE | 43 | Flop & Latch | +| LUT2 | 41 | LUT | +| OBUF | 24 | IO | +| LUT6 | 18 | LUT | +| FDRE | 17 | Flop & Latch | +| CARRY4 | 10 | CarryLogic | +| LUT4 | 9 | LUT | +| LUT5 | 7 | LUT | +| LUT3 | 5 | LUT | +| LUT1 | 3 | LUT | +| IBUF | 2 | IO | +| FDSE | 1 | Flop & Latch | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/test/test.runs/synth_1/vivado.jou b/test/test.runs/synth_1/vivado.jou new file mode 100644 index 0000000..eb840f6 --- /dev/null +++ b/test/test.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.1 (64-bit) +# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 +# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 +# Start of session at: Thu Dec 19 03:42:19 2024 +# Process ID: 3132 +# Current directory: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1 +# Command line: vivado.exe -log t_date.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source t_date.tcl +# Log file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1/t_date.vds +# Journal file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source t_date.tcl -notrace diff --git a/test/test.runs/synth_1/vivado.pb b/test/test.runs/synth_1/vivado.pb new file mode 100644 index 0000000..c531567 Binary files /dev/null and b/test/test.runs/synth_1/vivado.pb differ diff --git a/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc b/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc new file mode 100644 index 0000000..f59aa6a --- /dev/null +++ b/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc @@ -0,0 +1,52 @@ +set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {a_h1[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {a_h2[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports rst] +set_property PACKAGE_PIN P17 [get_ports clk] +set_property PACKAGE_PIN R15 [get_ports rst] +set_property PACKAGE_PIN B4 [get_ports {a_h1[7]}] +set_property PACKAGE_PIN A4 [get_ports {a_h1[6]}] +set_property PACKAGE_PIN A3 [get_ports {a_h1[5]}] +set_property PACKAGE_PIN B1 [get_ports {a_h1[4]}] +set_property PACKAGE_PIN A1 [get_ports {a_h1[3]}] +set_property PACKAGE_PIN B3 [get_ports {a_h1[2]}] +set_property PACKAGE_PIN B2 [get_ports {a_h1[1]}] +set_property PACKAGE_PIN D5 [get_ports {a_h1[0]}] +set_property PACKAGE_PIN D4 [get_ports {a_h2[7]}] +set_property PACKAGE_PIN E3 [get_ports {a_h2[6]}] +set_property PACKAGE_PIN D3 [get_ports {a_h2[5]}] +set_property PACKAGE_PIN F4 [get_ports {a_h2[4]}] +set_property PACKAGE_PIN F3 [get_ports {a_h2[3]}] +set_property PACKAGE_PIN E2 [get_ports {a_h2[2]}] +set_property PACKAGE_PIN D2 [get_ports {a_h2[1]}] +set_property PACKAGE_PIN H2 [get_ports {a_h2[0]}] +set_property PACKAGE_PIN G2 [get_ports {an[7]}] +set_property PACKAGE_PIN C2 [get_ports {an[6]}] +set_property PACKAGE_PIN C1 [get_ports {an[5]}] +set_property PACKAGE_PIN H1 [get_ports {an[4]}] +set_property PACKAGE_PIN G1 [get_ports {an[3]}] +set_property PACKAGE_PIN F1 [get_ports {an[2]}] +set_property PACKAGE_PIN E1 [get_ports {an[1]}] +set_property PACKAGE_PIN G6 [get_ports {an[0]}] diff --git a/test/test.srcs/sources_1/imports/Downloads/OUT.v b/test/test.srcs/sources_1/imports/Downloads/OUT.v new file mode 100644 index 0000000..7bf6388 --- /dev/null +++ b/test/test.srcs/sources_1/imports/Downloads/OUT.v @@ -0,0 +1,102 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/16 18:19:13 +// Design Name: +// Module Name: OUT +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module OUT(clk,rst,y,an,a_h1,a_h2); +input clk; +input rst; +input [3:0]y; +output reg[7:0]an; +output reg[7:0]a_h1,a_h2; +always @(posedge clk) + if(rst) + an<=0000_0001; + else begin + case(y) + 4'b0000:begin an<=0000_0001; + a_h2<=8'b1101_1010; + end + 4'b0001:begin an<={an[7:2],an[0],an[1]}; + case(an) + 1:a_h2<=8'b1111_1100; + 2:a_h2<=8'b1101_1010; + endcase + end + 4'b0010:begin an<={an[7:3],an[0],an[2:1]}; + case(an) + 1:a_h2<=8'b1101_1010; + 2:a_h2<=8'b1111_1100; + 4:a_h2<=8'b1101_1010; + endcase + end + 4'b0011:begin an<={an[7:4],an[0],an[3:1]}; + case(an) + 1:a_h2<=8'b0110_0111; + 2:a_h2<=8'b1101_1010; + 4:a_h2<=8'b1111_1100; + 8:a_h2<=8'b1101_1010; + endcase + end + 4'b0100:begin an<={an[7:5],an[0],an[4:1]}; + case(an) + 1:a_h2<=8'b0110_0000; + 2:a_h2<=8'b0110_0111; + 4:a_h2<=8'b1101_1010; + 8:a_h2<=8'b1111_1100; + 16:a_h1<=8'b1101_1010; + endcase + end + 4'b0101:begin an<={an[7:6],an[0],an[5:1]}; + case(an) + 1:a_h2<=8'b1101_1011; + 2:a_h2<=8'b0110_0000; + 4:a_h2<=8'b0110_0111; + 8:a_h2<=8'b1101_1010; + 16:a_h1<=8'b1111_1100; + 32:a_h1<=8'b1101_1010; + endcase + end + 4'b0110:begin an<={an[7],an[0],an[6:1]}; + case(an) + 1:a_h2<=8'b0110_0000; + 2:a_h2<=8'b1101_1011; + 4:a_h2<=8'b0110_0000; + 8:a_h2<=8'b0110_0111; + 16:a_h1<=8'b1101_1010; + 32:a_h1<=8'b1111_1100; + 64:a_h1<=8'b1101_1010; + endcase + end + 4'b0111:begin an<={an[0],an[7:1]}; + case(an) + 1:a_h2<=8'b1011_1110; + 2:a_h2<=8'b0110_0000; + 4:a_h2<=8'b1101_1011; + 8:a_h2<=8'b0110_0000; + 16:a_h1<=8'b0110_0111; + 32:a_h1<=8'b1101_1010; + 64:a_h1<=8'b1111_1100; + 128:a_h1<=8'b1101_1010; + endcase + end + endcase + end +endmodule diff --git a/test/test.srcs/sources_1/imports/Downloads/slow.v b/test/test.srcs/sources_1/imports/Downloads/slow.v new file mode 100644 index 0000000..217377b --- /dev/null +++ b/test/test.srcs/sources_1/imports/Downloads/slow.v @@ -0,0 +1,57 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/16 15:44:41 +// Design Name: +// Module Name: slow +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module clk(clk,rst,clk_1HZ,clk_20kHZ); +input clk,rst; +output clk_1HZ,clk_20kHZ; +reg clk_1HZ,clk_20kHZ; +reg [25:0]counter1; +reg [11:0]counter20k; +parameter sys_clk=100_000_000; +parameter clk_out1=1; +parameter clk_out20k=20_000; +parameter max1=sys_clk/(2*clk_out1)-1; +parameter max20k=sys_clk/(2*clk_out20k)-1; +always@(posedge clk or posedge rst) begin +if(rst)begin +clk_1HZ<=0; +clk_20kHZ<=0; +counter1<=0; +counter20k<=0; +end +else +begin + if(counter20k==max20k)begin + clk_20kHZ<=~clk_20kHZ; + counter20k<=0; + end + else + counter20k<=(counter20k)+1; + if(counter1==max1)begin + clk_1HZ<=~clk_1HZ; + counter1<=0; + end + else + counter1<=(counter1)+1; + end +end +endmodule diff --git a/test/test.srcs/sources_1/imports/Downloads/t_date.v b/test/test.srcs/sources_1/imports/Downloads/t_date.v new file mode 100644 index 0000000..261ab26 --- /dev/null +++ b/test/test.srcs/sources_1/imports/Downloads/t_date.v @@ -0,0 +1,137 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/12/16 15:53:27 +// Design Name: +// Module Name: t_date +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module t_date ( + clk, + rst, + an, + a_h1, + a_h2 +); + input clk, rst; + output reg [7:0] a_h1, a_h2; + output reg [7:0] an; + parameter y0=4'b0000,y1=4'b0001,y2=4'b0010,y3=4'b0011, + y4=4'b0100,y5=4'b0101,y6=4'b0110,y7=4'b0111; + reg [3:0] state_c, state_n; + wire clk_1HZ, clk_20kHZ; + clk U1 ( + .clk(clk), + .rst(rst), + .clk_1HZ(clk_1HZ), + .clk_20kHZ(clk_20kHZ) + ); + always @(posedge clk_1HZ or posedge rst) + if (rst) state_c <= y0; + else state_c <= state_n; + always @(state_c) + case (state_c) + y0: state_n = y1; + y1: state_n = y2; + y2: state_n = y3; + y3: state_n = y4; + y4: state_n = y5; + y5: state_n = y6; + y6: state_n = y7; + y7: state_n = y0; + endcase + always @(posedge clk_20kHZ) + if (rst) an <= 0000_0001; + else begin + case (state_c) + 4'b0000: begin + an <= 0000_0001; + a_h2 <= 8'b1101_1010; + end + 4'b0001: begin + an <= {an[7:2], an[0], an[1]}; + case (an) + 1: a_h2 <= 8'b1101_1010; + 2: a_h2 <= 8'b1111_1100; + endcase + end + 4'b0010: begin + an <= {an[7:3], an[0], an[2:1]}; + case (an) + 1: a_h2 <= 8'b1101_1010; + 2: a_h2 <= 8'b1101_1010; + 4: a_h2 <= 8'b1111_1100; + endcase + end + 4'b0011: begin + an <= {an[7:4], an[0], an[3:1]}; + case (an) + 1: a_h2 <= 8'b1101_1010; + 2: a_h2 <= 8'b0110_0111; + 4: a_h2 <= 8'b1101_1010; + 8: a_h2 <= 8'b1111_1100; + endcase + end + 4'b0100: begin + an <= {an[7:5], an[0], an[4:1]}; + case (an) + 1: a_h2 <= 8'b1111_1100; + 2: a_h2 <= 8'b0110_0000; + 4: a_h2 <= 8'b0110_0111; + 8: a_h2 <= 8'b1101_1010; + 16: a_h1 <= 8'b1101_1010; + endcase + end + 4'b0101: begin + an <= {an[7:6], an[0], an[5:1]}; + case (an) + 1: a_h2 <= 8'b1101_1010; + 2: a_h2 <= 8'b1101_1011; + 4: a_h2 <= 8'b0110_0000; + 8: a_h2 <= 8'b0110_0111; + 16: a_h1 <= 8'b1101_1010; + 32: a_h1 <= 8'b1111_1100; + endcase + end + 4'b0110: begin + an <= {an[7], an[0], an[6:1]}; + case (an) + 1: a_h2 <= 8'b0110_0111; + 2: a_h2 <= 8'b0110_0000; + 4: a_h2 <= 8'b1101_1011; + 8: a_h2 <= 8'b0110_0000; + 16: a_h1 <= 8'b1101_1010; + 32: a_h1 <= 8'b1101_1010; + 64: a_h1 <= 8'b1111_1100; + endcase + end + 4'b0111: begin + an <= {an[0], an[7:1]}; + case (an) + 1: a_h2 <= 8'b0110_0000; + 2: a_h2 <= 8'b1011_1110; + 4: a_h2 <= 8'b0110_0000; + 8: a_h2 <= 8'b1101_1011; + 16: a_h1 <= 8'b1101_1010; + 32: a_h1 <= 8'b0110_0000; + 64: a_h1 <= 8'b1101_1010; + 128: a_h1 <= 8'b1111_1100; + endcase + end + endcase + end +endmodule diff --git a/test/test.xpr b/test/test.xpr new file mode 100644 index 0000000..f394924 --- /dev/null +++ b/test/test.xpr @@ -0,0 +1,166 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/water_level_control/water_level_control.cache/wt/webtalk_pa.xml b/water_level_control/water_level_control.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..bbd3e5e --- /dev/null +++ b/water_level_control/water_level_control.cache/wt/webtalk_pa.xml @@ -0,0 +1,37 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/water_level_control/water_level_control.srcs/sources_1/new/water_level_control.v b/water_level_control/water_level_control.srcs/sources_1/new/water_level_control.v new file mode 100644 index 0000000..74281fa --- /dev/null +++ b/water_level_control/water_level_control.srcs/sources_1/new/water_level_control.v @@ -0,0 +1,40 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2024/10/26 00:24:32 +// Design Name: +// Module Name: water_level_control +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module water_level_control( + input A, // 最高位电极 + input B, // 中间电极 + input C, // 最低位电极 + output G, // 绿灯（正常状态） + output Y, // 黄灯（水位过高或过低） + output R // 红灯（缺水） +); + // G = A·B·C （正常水位） + assign G = A & B & C; + + // Y = (A + ~B)·B·C + ~C·B （水位过高或过低） + assign Y = ((A | ~B) & B & C) | (~C & B); + + // R = ~C （缺水） + assign R = ~C & ~B; + +endmodule \ No newline at end of file diff --git a/water_level_control/water_level_control.xpr b/water_level_control/water_level_control.xpr new file mode 100644 index 0000000..560121e --- /dev/null +++ b/water_level_control/water_level_control.xpr @@ -0,0 +1,138 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + +