`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 2024/09/24 15:10:13
// Design Name: 
// Module Name: sim4mux21
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
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module sim4mux21();
reg a, b, c;
wire y;
mux21 uut(.a(a), .b(b), .c(c), .y(y));
    always begin
    a = 0; b = 0; c = 0; #100;
    a = 0; b = 0; c = 1; #100;
    a = 0; b = 1; c = 0; #100;
    a = 0; b = 1; c = 1; #100;
    a = 1; b = 0; c = 0; #100;
    a = 1; b = 0; c = 1; #100;
    a = 1; b = 1; c = 0; #100;
    a = 1; b = 1; c = 1; #100;
    end
endmodule