`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/10/18 21:44:02
// Design Name: 
// Module Name: VotingMachine
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module VotingMachine(
    input wire [4:0] votes,
    output wire [6:0] seg1,
    output wire [6:0] seg2,
    output reg [3:0] seg_cs1,
    output reg [3:0] seg_cs2
);
    wire [2:0] count;
    wire pass;
CoreModule u1 (
    .votes(votes),
    .count(count),
    .pass(pass)
);
SegDisplayCtrl u2 (
    .count(count),
    .pass(pass),
    .seg1(seg1),
    .seg2(seg2)
);
always @(*) begin
    seg_cs1 = 4'b0001;
    seg_cs2 = 4'b0001;
end
endmodule