#----------------------------------------------------------- # Vivado v2018.1 (64-bit) # SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 # Start of session at: Wed Nov 6 20:19:40 2024 # Process ID: 27608 # Current directory: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1 # Command line: vivado.exe -log encoder.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source encoder.tcl # Log file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1/encoder.vds # Journal file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1\vivado.jou #----------------------------------------------------------- source encoder.tcl -notrace Command: synth_design -top encoder -part xc7a35tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26504 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 409.770 ; gain = 97.609 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'encoder' [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v:23] INFO: [Synth 8-6157] synthesizing module 'SegDisplayCtrl' [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/SegDisplayCtrl.v:22] INFO: [Synth 8-226] default block is never used [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/SegDisplayCtrl.v:29] INFO: [Synth 8-6155] done synthesizing module 'SegDisplayCtrl' (1#1) [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/SegDisplayCtrl.v:22] INFO: [Synth 8-6155] done synthesizing module 'encoder' (2#1) [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v:23] WARNING: [Synth 8-3917] design encoder has port seg_cs1[3] driven by constant 0 WARNING: [Synth 8-3917] design encoder has port seg_cs1[2] driven by constant 0 WARNING: [Synth 8-3917] design encoder has port seg_cs1[1] driven by constant 0 WARNING: [Synth 8-3917] design encoder has port seg_cs1[0] driven by constant 1 WARNING: [Synth 8-3917] design encoder has port seg_cs2[3] driven by constant 0 WARNING: [Synth 8-3917] design encoder has port seg_cs2[2] driven by constant 0 WARNING: [Synth 8-3917] design encoder has port seg_cs2[1] driven by constant 0 WARNING: [Synth 8-3917] design encoder has port seg_cs2[0] driven by constant 1 --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 464.227 ; gain = 152.066 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 464.227 ; gain = 152.066 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 464.227 ; gain = 152.066 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7a35tcsg324-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc] Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/encoder_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/encoder_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 745.281 ; gain = 0.000 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 745.281 ; gain = 433.121 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 745.281 ; gain = 433.121 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 745.281 ; gain = 433.121 --------------------------------------------------------------------------------- INFO: [Synth 8-5546] ROM "out" won't be mapped to RAM because it is too sparse WARNING: [Synth 8-327] inferring latch for variable 'i_sig_reg' [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v:40] WARNING: [Synth 8-327] inferring latch for variable 'Y_reg' [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v:40] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 745.281 ; gain = 433.121 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Muxes : 2 Input 8 Bit Muxes := 1 9 Input 8 Bit Muxes := 1 8 Input 7 Bit Muxes := 1 9 Input 3 Bit Muxes := 2 9 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module encoder Detailed RTL Component Info : +---Muxes : 9 Input 8 Bit Muxes := 1 9 Input 3 Bit Muxes := 2 9 Input 1 Bit Muxes := 1 Module SegDisplayCtrl Detailed RTL Component Info : +---Muxes : 2 Input 8 Bit Muxes := 1 8 Input 7 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 90 (col length:60) BRAMs: 100 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met INFO: [Synth 8-5546] ROM "out" won't be mapped to RAM because it is too sparse WARNING: [Synth 8-3917] design encoder has port seg2[6] driven by constant 0 WARNING: [Synth 8-3917] design encoder has port seg2[5] driven by constant 0 WARNING: [Synth 8-3917] design encoder has port seg_cs1[3] driven by constant 0 WARNING: [Synth 8-3917] design encoder has port seg_cs1[2] driven by constant 0 WARNING: [Synth 8-3917] design encoder has port seg_cs1[1] driven by constant 0 WARNING: [Synth 8-3917] design encoder has port seg_cs1[0] driven by constant 1 WARNING: [Synth 8-3917] design encoder has port seg_cs2[3] driven by constant 0 WARNING: [Synth 8-3917] design encoder has port seg_cs2[2] driven by constant 0 WARNING: [Synth 8-3917] design encoder has port seg_cs2[1] driven by constant 0 WARNING: [Synth 8-3917] design encoder has port seg_cs2[0] driven by constant 1 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 745.281 ; gain = 433.121 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 784.875 ; gain = 472.715 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 784.875 ; gain = 472.715 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 784.949 ; gain = 472.789 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |LUT1 | 7| |2 |LUT2 | 1| |3 |LUT3 | 7| |4 |LUT4 | 3| |5 |LUT5 | 2| |6 |LUT6 | 3| |7 |LD | 11| |8 |IBUF | 9| |9 |OBUF | 31| +------+-----+------+ Report Instance Areas: +------+---------+---------------+------+ | |Instance |Module |Cells | +------+---------+---------------+------+ |1 |top | | 74| |2 | unit |SegDisplayCtrl | 5| +------+---------+---------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 12 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 786.082 ; gain = 192.867 Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.082 ; gain = 473.922 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 20 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 11 instances were transformed. LD => LDCE: 11 instances INFO: [Common 17-83] Releasing license: Synthesis 19 Infos, 20 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 807.133 ; gain = 507.688 INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1/encoder.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file encoder_utilization_synth.rpt -pb encoder_utilization_synth.pb report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 807.133 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Wed Nov 6 20:20:03 2024...