#----------------------------------------------------------- # Vivado v2018.1 (64-bit) # SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 # Start of session at: Thu Nov 7 02:28:12 2024 # Process ID: 21720 # Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1 # Command line: vivado.exe -log calc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source calc.tcl # Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1/calc.vds # Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1\vivado.jou #----------------------------------------------------------- source calc.tcl -notrace Command: synth_design -top calc -part xc7a35tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 28152 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 410.371 ; gain = 97.773 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'calc' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/calc.v:23] INFO: [Synth 8-6157] synthesizing module 'judge' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/judge.v:23] INFO: [Synth 8-6155] done synthesizing module 'judge' (1#1) [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/judge.v:23] INFO: [Synth 8-6157] synthesizing module 'SegDisplayCtrl' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v:23] INFO: [Synth 8-6155] done synthesizing module 'SegDisplayCtrl' (2#1) [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/SegDisplayCtrl.v:23] INFO: [Synth 8-6155] done synthesizing module 'calc' (3#1) [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/calc.v:23] WARNING: [Synth 8-3917] design calc has port seg_cs[3] driven by constant 0 WARNING: [Synth 8-3917] design calc has port seg_cs[2] driven by constant 0 --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 465.418 ; gain = 152.820 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 465.418 ; gain = 152.820 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 465.418 ; gain = 152.820 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7a35tcsg324-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc] Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/calc_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/calc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 770.922 ; gain = 0.000 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324 --------------------------------------------------------------------------------- INFO: [Synth 8-5587] ROM size for "seg" is below threshold of ROM address width. It will be mapped to LUTs WARNING: [Synth 8-327] inferring latch for variable 'result_reg' [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/sources_1/new/judge.v:29] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 770.922 ; gain = 458.324 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 +---XORs : 2 Input 5 Bit XORs := 1 +---Registers : 5 Bit Registers := 1 +---Muxes : 6 Input 7 Bit Muxes := 1 3 Input 5 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module calc Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 +---XORs : 2 Input 5 Bit XORs := 1 +---Registers : 5 Bit Registers := 1 Module judge Detailed RTL Component Info : +---Muxes : 3 Input 5 Bit Muxes := 1 Module SegDisplayCtrl Detailed RTL Component Info : +---Muxes : 6 Input 7 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 90 (col length:60) BRAMs: 100 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met WARNING: [Synth 8-3917] design calc has port seg_cs[3] driven by constant 0 WARNING: [Synth 8-3917] design calc has port seg_cs[2] driven by constant 0 WARNING: [Synth 8-3917] design calc has port seg_cs[1] driven by constant 0 INFO: [Synth 8-3886] merging instance 'run/result_reg[0]' (LDC) to 'run/result_reg[4]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\run/result_reg[4] ) WARNING: [Synth 8-3332] Sequential element (run/result_reg[4]) is unused and will be removed from module calc. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 770.922 ; gain = 458.324 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 786.383 ; gain = 473.785 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 786.383 ; gain = 473.785 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 786.754 ; gain = 474.156 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |BUFG | 1| |2 |LUT2 | 4| |3 |LUT3 | 4| |4 |LUT4 | 2| |5 |LUT5 | 11| |6 |LUT6 | 12| |7 |FDRE | 5| |8 |LDC | 1| |9 |LDCP | 2| |10 |IBUF | 14| |11 |OBUF | 16| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 72| |2 | run |judge | 18| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.883 ; gain = 475.285 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 5 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 787.938 ; gain = 169.836 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 787.938 ; gain = 475.340 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 17 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 3 instances were transformed. LDC => LDCE: 1 instances LDCP => LDCP (GND, LUT3, LUT3, LDCE, VCC): 2 instances INFO: [Common 17-83] Releasing license: Synthesis 21 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 804.738 ; gain = 504.793 INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/synth_1/calc.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file calc_utilization_synth.rpt -pb calc_utilization_synth.pb report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 804.738 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Thu Nov 7 02:28:37 2024...