`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 2024/10/31 10:43:01
// Design Name: 
// Module Name: calc
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module calc(
    input [3:0] data1,
    input [3:0] data2,
    input [4:0] type,
    input clk,
    output reg [4:0] result,
    output wire [6:0] seg,
    output reg [3:0] seg_cs
);
reg [4:0] stored_type = 5'b00000;
wire [4:0] judge_result;
wire [4:0] operation_result;
judge run (.data1(data1), .data2(data2), .result(judge_result));
always @(posedge clk) begin
    if (type != 5'b00000) stored_type <= type;
end
always @(*) begin
    case (stored_type)
        5'b10000: result = data1 + data2;
        5'b01000: result = data1 & data2;
        5'b00100: result = data1 | data2;
        5'b00010: result = data1 ^ data2;
        5'b00001: result = judge_result;
        default: result = 5'b00000;
    endcase
    seg_cs = (stored_type != 5'b00000) ? 4'b0001 : 4'b0000;
end
SegDisplayCtrl unit (.type(stored_type), .seg(seg));
endmodule