#----------------------------------------------------------- # Vivado v2018.1 (64-bit) # SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 # Start of session at: Mon Dec 16 19:20:39 2024 # Process ID: 20280 # Current directory: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1 # Command line: vivado.exe -log date_display.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source date_display.tcl # Log file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1/date_display.vds # Journal file: F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1\vivado.jou #----------------------------------------------------------- source date_display.tcl -notrace Command: synth_design -top date_display -part xc7a35tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 28272 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 412.238 ; gain = 98.691 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'date_display' [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:23] Parameter S0 bound to: 4'b0000 Parameter S1 bound to: 4'b0001 Parameter S2 bound to: 4'b0010 Parameter S3 bound to: 4'b0011 Parameter S4 bound to: 4'b0100 Parameter S5 bound to: 4'b0101 Parameter S6 bound to: 4'b0110 Parameter S7 bound to: 4'b0111 Parameter S8 bound to: 4'b1000 Parameter S9 bound to: 4'b1001 Parameter S10 bound to: 4'b1010 Parameter S11 bound to: 4'b1011 Parameter S12 bound to: 4'b1100 Parameter S13 bound to: 4'b1101 Parameter S14 bound to: 4'b1110 Parameter S15 bound to: 4'b1111 Parameter SEG_0 bound to: 8'b11111101 Parameter SEG_1 bound to: 8'b01100001 Parameter SEG_2 bound to: 8'b11011011 Parameter SEG_3 bound to: 8'b11110011 Parameter SEG_4 bound to: 8'b01100111 Parameter SEG_5 bound to: 8'b10110111 Parameter SEG_6 bound to: 8'b10111111 Parameter SEG_7 bound to: 8'b11100001 Parameter SEG_8 bound to: 8'b11111111 Parameter SEG_9 bound to: 8'b11110111 Parameter SEG_DP bound to: 8'b00000001 INFO: [Synth 8-226] default block is never used [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:93] WARNING: [Synth 8-6014] Unused sequential element seg_temp_reg was removed. [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:121] INFO: [Synth 8-6155] done synthesizing module 'date_display' (1#1) [F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.srcs/sources_1/new/date_display.v:23] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7a35tcsg324-1 INFO: [Synth 8-5546] ROM "clk_1hz" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "sequence" won't be mapped to Block RAM because address size (4) smaller than threshold (5) --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 466.418 ; gain = 152.871 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 20 Bit Adders := 1 +---Registers : 20 Bit Registers := 1 8 Bit Registers := 2 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 17 Input 56 Bit Muxes := 1 2 Input 20 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module date_display Detailed RTL Component Info : +---Adders : 2 Input 20 Bit Adders := 1 +---Registers : 20 Bit Registers := 1 8 Bit Registers := 2 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 17 Input 56 Bit Muxes := 1 2 Input 20 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 90 (col length:60) BRAMs: 100 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met INFO: [Synth 8-5546] ROM "clk_1hz" won't be mapped to RAM because it is too sparse INFO: [Synth 8-3886] merging instance 'an_reg[0]' (FDP) to 'seg_reg[7]' INFO: [Synth 8-3886] merging instance 'an_reg[1]' (FDP) to 'an_reg[2]' INFO: [Synth 8-3886] merging instance 'an_reg[2]' (FDP) to 'an_reg[3]' INFO: [Synth 8-3886] merging instance 'an_reg[3]' (FDP) to 'an_reg[4]' INFO: [Synth 8-3886] merging instance 'an_reg[4]' (FDP) to 'an_reg[5]' INFO: [Synth 8-3886] merging instance 'an_reg[5]' (FDP) to 'an_reg[6]' INFO: [Synth 8-3886] merging instance 'an_reg[6]' (FDP) to 'an_reg[7]' INFO: [Synth 8-3333] propagating constant 1 across sequential element (\an_reg[7] ) INFO: [Synth 8-3886] merging instance 'seg_reg[0]' (FDP) to 'seg_reg[7]' INFO: [Synth 8-3886] merging instance 'seg_reg[1]' (FDP) to 'seg_reg[7]' INFO: [Synth 8-3886] merging instance 'seg_reg[2]' (FDP) to 'seg_reg[7]' INFO: [Synth 8-3886] merging instance 'seg_reg[3]' (FDP) to 'seg_reg[7]' INFO: [Synth 8-3886] merging instance 'seg_reg[4]' (FDP) to 'seg_reg[7]' INFO: [Synth 8-3886] merging instance 'seg_reg[5]' (FDP) to 'seg_reg[7]' INFO: [Synth 8-3886] merging instance 'seg_reg[6]' (FDP) to 'seg_reg[7]' WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[3]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[2]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[1]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (state_c_reg_rep[0]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (an_reg[7]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[19]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[18]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[17]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[16]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[15]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[14]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[13]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[12]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[11]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[10]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[9]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[8]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[7]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[6]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[5]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[4]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[3]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[2]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[1]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (counter_reg[0]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (clk_1hz_reg) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (state_c_reg[3]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (state_c_reg[2]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (state_c_reg[1]) is unused and will be removed from module date_display. WARNING: [Synth 8-3332] Sequential element (state_c_reg[0]) is unused and will be removed from module date_display. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |BUFG | 1| |2 |FDPE | 1| |3 |IBUF | 2| |4 |OBUF | 16| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 20| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 31 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 Synthesis Optimization Complete : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 586.379 ; gain = 272.832 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 30 Infos, 31 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 692.234 ; gain = 391.566 INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp8-2/Exp8-2.runs/synth_1/date_display.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file date_display_utilization_synth.rpt -pb date_display_utilization_synth.pb report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 692.234 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Mon Dec 16 19:20:53 2024...