`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 2024/09/23 23:58:54
// Design Name: 
// Module Name: sim4First
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module sim4First( );
reg a;
reg b;
wire [2:0] z;
First uut( .a(a), .b(b), .z(z) );
always begin
a = 0; b = 0; #100;
a = 0; b = 1; #100;
a = 1; b = 0; #100;
a = 1; b = 1; #100;
end
endmodule