`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 2024/09/25 20:35:36
// Design Name: 
// Module Name: sim4mux41
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
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module sim4mux41();
reg [3:0] I;
reg [1:0] S;
wire Y;
integer i, s;
mux41 uut (.I(I), .S(S), .Y(Y));
initial begin
    for (i = 0; i < 16; i = i + 1) begin
        for (s = 0; s < 4; s = s + 1) begin
            I = i;
            S = s;
            #10;
        end
    end
end
endmodule