#----------------------------------------------------------- # Vivado v2018.1 (64-bit) # SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 # Start of session at: Wed Oct 30 22:07:18 2024 # Process ID: 5816 # Current directory: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/synth_1 # Command line: vivado.exe -log VotingMachine.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source VotingMachine.tcl # Log file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/synth_1/VotingMachine.vds # Journal file: F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/synth_1\vivado.jou #----------------------------------------------------------- source VotingMachine.tcl -notrace Command: synth_design -top VotingMachine -part xc7a35tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 8088 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 409.586 ; gain = 97.223 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'VotingMachine' [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/sources_1/new/VotingMachine.v:23] INFO: [Synth 8-6157] synthesizing module 'CoreModule' [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/sources_1/new/CoreModule.v:23] INFO: [Synth 8-6155] done synthesizing module 'CoreModule' (1#1) [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/sources_1/new/CoreModule.v:23] INFO: [Synth 8-6157] synthesizing module 'SegDisplayCtrl' [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/sources_1/new/SegDisplayCtrl.v:23] INFO: [Synth 8-6155] done synthesizing module 'SegDisplayCtrl' (2#1) [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/sources_1/new/SegDisplayCtrl.v:23] INFO: [Synth 8-6155] done synthesizing module 'VotingMachine' (3#1) [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/sources_1/new/VotingMachine.v:23] WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[3] driven by constant 0 WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[2] driven by constant 0 WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[1] driven by constant 0 WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[0] driven by constant 1 WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[3] driven by constant 0 WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[2] driven by constant 0 WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[1] driven by constant 0 WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[0] driven by constant 1 --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 465.242 ; gain = 152.879 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 465.242 ; gain = 152.879 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 465.242 ; gain = 152.879 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7a35tcsg324-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/constrs_1/new/VotingMachine.xdc] Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/constrs_1/new/VotingMachine.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp2/Exp2.srcs/constrs_1/new/VotingMachine.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/VotingMachine_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/VotingMachine_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 739.375 ; gain = 0.000 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 739.375 ; gain = 427.012 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 739.375 ; gain = 427.012 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 739.375 ; gain = 427.012 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 739.375 ; gain = 427.012 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 5 Input 3 Bit Adders := 1 +---Muxes : 7 Input 7 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module CoreModule Detailed RTL Component Info : +---Adders : 5 Input 3 Bit Adders := 1 Module SegDisplayCtrl Detailed RTL Component Info : +---Muxes : 7 Input 7 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 90 (col length:60) BRAMs: 100 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met WARNING: [Synth 8-3917] design VotingMachine has port seg2[6] driven by constant 1 WARNING: [Synth 8-3917] design VotingMachine has port seg2[4] driven by constant 0 WARNING: [Synth 8-3917] design VotingMachine has port seg2[3] driven by constant 0 WARNING: [Synth 8-3917] design VotingMachine has port seg2[2] driven by constant 1 WARNING: [Synth 8-3917] design VotingMachine has port seg2[1] driven by constant 1 WARNING: [Synth 8-3917] design VotingMachine has port seg2[0] driven by constant 1 WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[3] driven by constant 0 WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[2] driven by constant 0 WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[1] driven by constant 0 WARNING: [Synth 8-3917] design VotingMachine has port seg_cs1[0] driven by constant 1 WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[3] driven by constant 0 WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[2] driven by constant 0 WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[1] driven by constant 0 WARNING: [Synth 8-3917] design VotingMachine has port seg_cs2[0] driven by constant 1 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 739.375 ; gain = 427.012 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 783.949 ; gain = 471.586 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 783.949 ; gain = 471.586 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 784.660 ; gain = 472.297 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.789 ; gain = 473.426 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.789 ; gain = 473.426 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.789 ; gain = 473.426 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.789 ; gain = 473.426 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.789 ; gain = 473.426 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.789 ; gain = 473.426 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |LUT5 | 7| |2 |IBUF | 5| |3 |OBUF | 22| +------+-----+------+ Report Instance Areas: +------+---------+---------------+------+ | |Instance |Module |Cells | +------+---------+---------------+------+ |1 |top | | 34| |2 | u1 |CoreModule | 1| |3 | u2 |SegDisplayCtrl | 6| +------+---------+---------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.789 ; gain = 473.426 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 14 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 785.824 ; gain = 199.328 Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 785.824 ; gain = 473.461 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 18 Infos, 22 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 803.844 ; gain = 504.035 INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp2/Exp2.runs/synth_1/VotingMachine.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file VotingMachine_utilization_synth.rpt -pb VotingMachine_utilization_synth.pb report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 803.844 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Wed Oct 30 22:07:51 2024...