#-----------------------------------------------------------
# Vivado v2018.1 (64-bit)
# SW Build 2188600 on Wed Apr  4 18:40:38 MDT 2018
# IP Build 2185939 on Wed Apr  4 20:55:05 MDT 2018
# Start of session at: Thu Dec 12 11:42:45 2024
# Process ID: 26148
# Current directory: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1
# Command line: vivado.exe -log counter_10.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source counter_10.tcl -notrace
# Log file: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10.vdi
# Journal file: F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source counter_10.tcl -notrace
Command: link_design -top counter_10 -part xc7a35tcsg324-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.1
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.srcs/constrs_1/new/counter_19.xdc]
Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.srcs/constrs_1/new/counter_19.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 608.109 ; gain = 302.410
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 621.867 ; gain = 13.758
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1a3a304eb

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1152.344 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1a3a304eb

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1152.344 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 1a3a304eb

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1152.344 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 1a3a304eb

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1152.344 ; gain = 0.000
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 1a3a304eb

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1152.344 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 1a3a304eb

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1152.344 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells

Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1152.344 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1a3a304eb

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1152.344 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1a3a304eb

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1152.344 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1152.344 ; gain = 544.234
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1152.344 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file counter_10_drc_opted.rpt -pb counter_10_drc_opted.pb -rpx counter_10_drc_opted.rpx
Command: report_drc -file counter_10_drc_opted.rpt -pb counter_10_drc_opted.pb -rpx counter_10_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1152.344 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 144551012

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1152.344 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1152.344 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 40a97d45

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.451 . Memory (MB): peak = 1175.508 ; gain = 23.164

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 6ec5449b

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.480 . Memory (MB): peak = 1175.508 ; gain = 23.164

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 6ec5449b

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.482 . Memory (MB): peak = 1175.508 ; gain = 23.164
Phase 1 Placer Initialization | Checksum: 6ec5449b

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.487 . Memory (MB): peak = 1175.508 ; gain = 23.164

Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 67ab0db0

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.669 . Memory (MB): peak = 1175.508 ; gain = 23.164

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 67ab0db0

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.672 . Memory (MB): peak = 1175.508 ; gain = 23.164

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: b44dab5c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.680 . Memory (MB): peak = 1175.508 ; gain = 23.164

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 654b6a0f

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.684 . Memory (MB): peak = 1175.508 ; gain = 23.164

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 654b6a0f

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.685 . Memory (MB): peak = 1175.508 ; gain = 23.164

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1600cb152

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.737 . Memory (MB): peak = 1175.508 ; gain = 23.164

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1600cb152

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.739 . Memory (MB): peak = 1175.508 ; gain = 23.164

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1600cb152

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.739 . Memory (MB): peak = 1175.508 ; gain = 23.164
Phase 3 Detail Placement | Checksum: 1600cb152

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.739 . Memory (MB): peak = 1175.508 ; gain = 23.164

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 1600cb152

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.741 . Memory (MB): peak = 1175.508 ; gain = 23.164

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1600cb152

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.748 . Memory (MB): peak = 1175.508 ; gain = 23.164

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 1600cb152

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.748 . Memory (MB): peak = 1175.508 ; gain = 23.164

Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 225cdd995

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.749 . Memory (MB): peak = 1175.508 ; gain = 23.164
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 225cdd995

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.749 . Memory (MB): peak = 1175.508 ; gain = 23.164
Ending Placer Task | Checksum: 1c5b8b459

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.752 . Memory (MB): peak = 1175.508 ; gain = 23.164
INFO: [Common 17-83] Releasing license: Implementation
41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1175.508 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file counter_10_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1183.660 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file counter_10_utilization_placed.rpt -pb counter_10_utilization_placed.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1183.660 ; gain = 0.000
INFO: [runtcl-4] Executing : report_control_sets -verbose -file counter_10_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1183.660 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: e83a1a30 ConstDB: 0 ShapeSum: dd7e9a29 RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 1294bf7db

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1299.867 ; gain = 116.207
Post Restoration Checksum: NetGraph: b4a6849b NumContArr: 74a57340 Constraints: 0 Timing: 0

Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 1294bf7db

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1305.926 ; gain = 122.266

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 1294bf7db

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1305.926 ; gain = 122.266
 Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: 65671432

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 12301e04d

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: 12c9b5e41

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043
Phase 4 Rip-up And Reroute | Checksum: 12c9b5e41

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043

Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: 12c9b5e41

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: 12c9b5e41

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043
Phase 6 Post Hold Fix | Checksum: 12c9b5e41

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.0168221 %
  Global Horizontal Routing Utilization  = 0.00429464 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Congestion Report
North Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 21.6216%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.

------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0

Phase 7 Route finalize | Checksum: 12c9b5e41

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.703 ; gain = 125.043

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 12c9b5e41

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.992 ; gain = 126.332

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 18b7847b5

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.992 ; gain = 126.332
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1309.992 ; gain = 126.332

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1309.992 ; gain = 126.332
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1309.992 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file counter_10_drc_routed.rpt -pb counter_10_drc_routed.pb -rpx counter_10_drc_routed.rpx
Command: report_drc -file counter_10_drc_routed.rpt -pb counter_10_drc_routed.pb -rpx counter_10_drc_routed.rpx
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file counter_10_methodology_drc_routed.rpt -pb counter_10_methodology_drc_routed.pb -rpx counter_10_methodology_drc_routed.rpx
Command: report_methodology -file counter_10_methodology_drc_routed.rpt -pb counter_10_methodology_drc_routed.pb -rpx counter_10_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp6-1/Exp6-1.runs/impl_1/counter_10_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file counter_10_power_routed.rpt -pb counter_10_power_summary_routed.pb -rpx counter_10_power_routed.rpx
Command: report_power -file counter_10_power_routed.rpt -pb counter_10_power_summary_routed.pb -rpx counter_10_power_routed.rpx
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file counter_10_route_status.rpt -pb counter_10_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file counter_10_timing_summary_routed.rpt -pb counter_10_timing_summary_routed.pb -rpx counter_10_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
INFO: [runtcl-4] Executing : report_incremental_reuse -file counter_10_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file counter_10_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Command: write_bitstream -force counter_10.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command write_bitstream
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./counter_10.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
84 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1760.434 ; gain = 417.121
INFO: [Common 17-206] Exiting Vivado at Thu Dec 12 11:43:50 2024...