#----------------------------------------------------------- # Vivado v2018.1 (64-bit) # SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 # Start of session at: Thu Dec 12 20:11:37 2024 # Process ID: 23000 # Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1 # Command line: vivado.exe -log slowClock.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source slowClock.tcl # Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1/slowClock.vds # Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1\vivado.jou #----------------------------------------------------------- source slowClock.tcl -notrace Command: synth_design -top slowClock -part xc7a35tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 21660 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 409.984 ; gain = 97.137 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'slowClock' [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/sources_1/new/slowClock.v:23] Parameter sys_clk bound to: 100000000 - type: integer Parameter clk_out1 bound to: 1 - type: integer Parameter clk_out12 bound to: 12 - type: integer Parameter clk_out48 bound to: 48 - type: integer Parameter clk_out190 bound to: 190 - type: integer Parameter max1 bound to: 49999999 - type: integer Parameter max12 bound to: 4166665 - type: integer Parameter max48 bound to: 1041665 - type: integer Parameter max190 bound to: 263156 - type: integer INFO: [Synth 8-6155] done synthesizing module 'slowClock' (1#1) [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/sources_1/new/slowClock.v:23] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 464.465 ; gain = 151.617 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 464.465 ; gain = 151.617 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 464.465 ; gain = 151.617 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7a35tcsg324-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc] Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/slowClock_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/slowClock_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 789.797 ; gain = 0.000 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949 --------------------------------------------------------------------------------- INFO: [Synth 8-5545] ROM "clk_1Hz" won't be mapped to RAM because address size (26) is larger than maximum supported(25) INFO: [Synth 8-5546] ROM "clk_12Hz" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clk_48Hz" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clk_190Hz" won't be mapped to RAM because it is too sparse --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 2 Input 23 Bit Adders := 1 2 Input 21 Bit Adders := 1 2 Input 19 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 23 Bit Registers := 1 21 Bit Registers := 1 19 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 26 Bit Muxes := 1 2 Input 23 Bit Muxes := 1 2 Input 21 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module slowClock Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 2 Input 23 Bit Adders := 1 2 Input 21 Bit Adders := 1 2 Input 19 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 23 Bit Registers := 1 21 Bit Registers := 1 19 Bit Registers := 1 1 Bit Registers := 4 +---Muxes : 2 Input 26 Bit Muxes := 1 2 Input 23 Bit Muxes := 1 2 Input 21 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 90 (col length:60) BRAMs: 100 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met INFO: [Synth 8-5545] ROM "clk_1Hz" won't be mapped to RAM because address size (26) is larger than maximum supported(25) INFO: [Synth 8-5546] ROM "clk_12Hz" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clk_48Hz" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "clk_190Hz" won't be mapped to RAM because it is too sparse --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 789.797 ; gain = 476.949 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 789.797 ; gain = 476.949 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 789.797 ; gain = 476.949 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 797.371 ; gain = 484.523 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 23| |3 |LUT1 | 3| |4 |LUT2 | 49| |5 |LUT3 | 1| |6 |LUT4 | 17| |7 |LUT5 | 2| |8 |LUT6 | 44| |9 |FDCE | 93| |10 |IBUF | 2| |11 |OBUF | 4| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 239| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 797.371 ; gain = 159.191 Synthesis Optimization Complete : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 25 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 805.500 ; gain = 505.727 INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1/slowClock.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file slowClock_utilization_synth.rpt -pb slowClock_utilization_synth.pb report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 805.500 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Thu Dec 12 20:12:13 2024...