#----------------------------------------------------------- # Vivado v2018.1 (64-bit) # SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 # Start of session at: Thu Dec 19 03:42:19 2024 # Process ID: 3132 # Current directory: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1 # Command line: vivado.exe -log t_date.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source t_date.tcl # Log file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1/t_date.vds # Journal file: Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1\vivado.jou #----------------------------------------------------------- source t_date.tcl -notrace Command: synth_design -top t_date -part xc7a35tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 692 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 407.832 ; gain = 96.258 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 't_date' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:23] Parameter y0 bound to: 4'b0000 Parameter y1 bound to: 4'b0001 Parameter y2 bound to: 4'b0010 Parameter y3 bound to: 4'b0011 Parameter y4 bound to: 4'b0100 Parameter y5 bound to: 4'b0101 Parameter y6 bound to: 4'b0110 Parameter y7 bound to: 4'b0111 INFO: [Synth 8-6157] synthesizing module 'clk' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/slow.v:23] Parameter sys_clk bound to: 100000000 - type: integer Parameter clk_out1 bound to: 1 - type: integer Parameter clk_out20k bound to: 20000 - type: integer Parameter max1 bound to: 49999999 - type: integer Parameter max20k bound to: 2499 - type: integer INFO: [Synth 8-6155] done synthesizing module 'clk' (1#1) [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/slow.v:23] INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:38] INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:57] INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:63] INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:70] INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:78] INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:87] INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:97] INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:108] INFO: [Synth 8-155] case statement is not full and has no default [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:52] INFO: [Synth 8-6155] done synthesizing module 't_date' (2#1) [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:23] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 463.461 ; gain = 151.887 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 463.461 ; gain = 151.887 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 463.461 ; gain = 151.887 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7a35tcsg324-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc] Finished Parsing XDC File [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/constrs_1/imports/Downloads/EX1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/t_date_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/t_date_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 788.133 ; gain = 0.000 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559 --------------------------------------------------------------------------------- INFO: [Synth 8-5545] ROM "clk_1HZ" won't be mapped to RAM because address size (26) is larger than maximum supported(25) INFO: [Synth 8-5546] ROM "clk_20kHZ" won't be mapped to RAM because it is too sparse INFO: [Synth 8-802] inferred FSM for state register 'state_c_reg' in module 't_date' INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5544] ROM "an" won't be mapped to Block RAM because address size (4) smaller than threshold (5) INFO: [Synth 8-5544] ROM "state_n" won't be mapped to Block RAM because address size (4) smaller than threshold (5) WARNING: [Synth 8-327] inferring latch for variable 'FSM_sequential_state_n_reg' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:39] WARNING: [Synth 8-327] inferring latch for variable 'FSM_onehot_state_n_reg' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:39] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 000 | 0000 iSTATE0 | 001 | 0001 iSTATE1 | 010 | 0010 iSTATE2 | 011 | 0011 iSTATE3 | 100 | 0100 iSTATE4 | 101 | 0101 iSTATE5 | 110 | 0110 iSTATE6 | 111 | 0111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_c_reg' using encoding 'sequential' in module 't_date' WARNING: [Synth 8-327] inferring latch for variable 'FSM_sequential_state_n_reg' [Z:/Storage/Schoolwork/DigitalLogic/test/test.srcs/sources_1/imports/Downloads/t_date.v:39] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 788.133 ; gain = 476.559 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 2 Input 12 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 12 Bit Registers := 1 8 Bit Registers := 3 1 Bit Registers := 2 +---Muxes : 2 Input 26 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 8 Bit Muxes := 6 7 Input 8 Bit Muxes := 2 8 Input 8 Bit Muxes := 6 9 Input 8 Bit Muxes := 2 3 Input 8 Bit Muxes := 1 4 Input 8 Bit Muxes := 1 5 Input 8 Bit Muxes := 1 6 Input 8 Bit Muxes := 1 8 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 11 6 Input 1 Bit Muxes := 2 7 Input 1 Bit Muxes := 2 8 Input 1 Bit Muxes := 4 9 Input 1 Bit Muxes := 2 3 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module t_date Detailed RTL Component Info : +---Registers : 8 Bit Registers := 3 +---Muxes : 2 Input 8 Bit Muxes := 6 7 Input 8 Bit Muxes := 2 8 Input 8 Bit Muxes := 6 9 Input 8 Bit Muxes := 2 3 Input 8 Bit Muxes := 1 4 Input 8 Bit Muxes := 1 5 Input 8 Bit Muxes := 1 6 Input 8 Bit Muxes := 1 8 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 9 6 Input 1 Bit Muxes := 2 7 Input 1 Bit Muxes := 2 8 Input 1 Bit Muxes := 4 9 Input 1 Bit Muxes := 2 3 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 1 5 Input 1 Bit Muxes := 1 Module clk Detailed RTL Component Info : +---Adders : 2 Input 26 Bit Adders := 1 2 Input 12 Bit Adders := 1 +---Registers : 26 Bit Registers := 1 12 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 26 Bit Muxes := 1 2 Input 12 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 90 (col length:60) BRAMs: 100 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met INFO: [Synth 8-5545] ROM "U1/clk_1HZ" won't be mapped to RAM because address size (26) is larger than maximum supported(25) INFO: [Synth 8-5546] ROM "U1/clk_20kHZ" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "a_h1" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "a_h2" won't be mapped to RAM because it is too sparse INFO: [Synth 8-3886] merging instance 'a_h2_reg[3]' (FDE) to 'a_h2_reg[7]' INFO: [Synth 8-3886] merging instance 'a_h2_reg[4]' (FDE) to 'a_h2_reg[7]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (\a_h1_reg[0] ) INFO: [Synth 8-3886] merging instance 'a_h1_reg[3]' (FDE) to 'a_h1_reg[7]' INFO: [Synth 8-3886] merging instance 'a_h1_reg[4]' (FDE) to 'a_h1_reg[7]' INFO: [Synth 8-3333] propagating constant 1 across sequential element (\a_h1_reg[6] ) WARNING: [Synth 8-3332] Sequential element (FSM_sequential_state_n_reg[2]) is unused and will be removed from module t_date. WARNING: [Synth 8-3332] Sequential element (FSM_sequential_state_n_reg[1]) is unused and will be removed from module t_date. WARNING: [Synth 8-3332] Sequential element (FSM_sequential_state_n_reg[0]) is unused and will be removed from module t_date. WARNING: [Synth 8-3332] Sequential element (a_h1_reg[6]) is unused and will be removed from module t_date. WARNING: [Synth 8-3332] Sequential element (a_h1_reg[0]) is unused and will be removed from module t_date. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 788.133 ; gain = 476.559 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 788.133 ; gain = 476.559 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 788.133 ; gain = 476.559 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 807.078 ; gain = 495.504 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 10| |3 |LUT1 | 3| |4 |LUT2 | 41| |5 |LUT3 | 5| |6 |LUT4 | 9| |7 |LUT5 | 7| |8 |LUT6 | 18| |9 |FDCE | 43| |10 |FDRE | 17| |11 |FDSE | 1| |12 |IBUF | 2| |13 |OBUF | 24| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 181| |2 | U1 |clk | 100| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 8 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:06 ; elapsed = 00:00:17 . Memory (MB): peak = 807.078 ; gain = 170.832 Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 807.078 ; gain = 495.504 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 54 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:25 . Memory (MB): peak = 807.078 ; gain = 508.328 INFO: [Common 17-1381] The checkpoint 'Z:/Storage/Schoolwork/DigitalLogic/test/test.runs/synth_1/t_date.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file t_date_utilization_synth.rpt -pb t_date_utilization_synth.pb report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 807.078 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Thu Dec 19 03:42:49 2024...