35 lines
662 B
Verilog
35 lines
662 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/09/23 23:58:54
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// Design Name:
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// Module Name: sim4First
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module sim4First( );
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reg a;
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reg b;
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wire [2:0] z;
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First uut( .a(a), .b(b), .z(z) );
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always begin
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a = 0; b = 0; #100;
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a = 0; b = 1; #100;
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a = 1; b = 0; #100;
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a = 1; b = 1; #100;
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end
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endmodule
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