39 lines
761 B
Verilog
39 lines
761 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/09/25 20:35:36
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// Design Name:
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// Module Name: sim4mux41
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module sim4mux41();
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reg [3:0] I;
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reg [1:0] S;
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wire Y;
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integer i, s;
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mux41 uut (.I(I), .S(S), .Y(Y));
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initial begin
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for (i = 0; i < 16; i = i + 1) begin
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for (s = 0; s < 4; s = s + 1) begin
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I = i;
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S = s;
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#10;
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end
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end
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end
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endmodule
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