63 lines
1.5 KiB
Verilog
63 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/10/24 10:37:58
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// Design Name:
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// Module Name: encoder
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module encoder(
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input en,
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input [7:0] i,
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output reg [7:0] i_sig,
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output wire [6:0] seg1,
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output wire [7:0] seg2,
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output reg [3:0] seg_cs1,
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output reg [3:0] seg_cs2
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);
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reg out;
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reg [2:0] Y;
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always @(*) begin
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out = 1;
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if (en == 0)
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out = 0;
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else begin
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case (i)
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8'b11111110: begin Y = 3'b000; i_sig = 8'b00000001; end
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8'b11111101: begin Y = 3'b001; i_sig = 8'b00000010; end
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8'b11111011: begin Y = 3'b010; i_sig = 8'b00000100; end
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8'b11110111: begin Y = 3'b011; i_sig = 8'b00001000; end
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8'b11101111: begin Y = 3'b100; i_sig = 8'b00010000; end
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8'b11011111: begin Y = 3'b101; i_sig = 8'b00100000; end
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8'b10111111: begin Y = 3'b110; i_sig = 8'b01000000; end
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8'b01111111: begin Y = 3'b111; i_sig = 8'b10000000; end
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default: out = 0;
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endcase
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end
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end
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SegDisplayCtrl unit (
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.Y(Y),
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.out(out),
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.seg1(seg1),
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.seg2(seg2)
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);
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always @(*) begin
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seg_cs1 = 4'b0001;
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seg_cs2 = 4'b0001;
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end
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endmodule
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