38 lines
860 B
Verilog
38 lines
860 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/10/31 11:26:14
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// Design Name:
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// Module Name: SegDisplayCtrl
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module SegDisplayCtrl(
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input wire [4:0] type,
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output reg [6:0] seg
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);
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always @(*) begin
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case (type)
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5'b10000: seg = 7'b1110111; // a
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5'b01000: seg = 7'b0011111; // b
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5'b00100: seg = 7'b1001110; // c
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5'b00010: seg = 7'b0111101; // d
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5'b00001: seg = 7'b1001111; // e
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default: seg = 7'b0000000;
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endcase
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end
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endmodule
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