34 lines
725 B
Verilog
34 lines
725 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/10/31 11:22:30
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// Design Name:
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// Module Name: judge
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module judge(
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input [3:0] data1,
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input [3:0] data2,
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output reg [4:0] result
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);
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always @(*) begin
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if (data1 > data2) result = 4'b1000;
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else if (data1 < data2) result = 4'b0100;
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else if (data1 == data2) result = 4'b0010;
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end
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endmodule
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