318 lines
19 KiB
Plaintext
318 lines
19 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2018.1 (64-bit)
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# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
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# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
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# Start of session at: Thu Dec 12 20:11:37 2024
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# Process ID: 23000
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# Current directory: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1
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# Command line: vivado.exe -log slowClock.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source slowClock.tcl
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# Log file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1/slowClock.vds
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# Journal file: F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1\vivado.jou
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#-----------------------------------------------------------
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source slowClock.tcl -notrace
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Command: synth_design -top slowClock -part xc7a35tcsg324-1
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 21660
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---------------------------------------------------------------------------------
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Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 409.984 ; gain = 97.137
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'slowClock' [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/sources_1/new/slowClock.v:23]
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Parameter sys_clk bound to: 100000000 - type: integer
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Parameter clk_out1 bound to: 1 - type: integer
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Parameter clk_out12 bound to: 12 - type: integer
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Parameter clk_out48 bound to: 48 - type: integer
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Parameter clk_out190 bound to: 190 - type: integer
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Parameter max1 bound to: 49999999 - type: integer
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Parameter max12 bound to: 4166665 - type: integer
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Parameter max48 bound to: 1041665 - type: integer
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Parameter max190 bound to: 263156 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'slowClock' (1#1) [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/sources_1/new/slowClock.v:23]
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---------------------------------------------------------------------------------
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Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 464.465 ; gain = 151.617
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---------------------------------------------------------------------------------
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Report Check Netlist:
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+------+------------------+-------+---------+-------+------------------+
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| |Item |Errors |Warnings |Status |Description |
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+------+------------------+-------+---------+-------+------------------+
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|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
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+------+------------------+-------+---------+-------+------------------+
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---------------------------------------------------------------------------------
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Start Handling Custom Attributes
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 464.465 ; gain = 151.617
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 464.465 ; gain = 151.617
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---------------------------------------------------------------------------------
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INFO: [Device 21-403] Loading part xc7a35tcsg324-1
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Processing XDC Constraints
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Initializing timing engine
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Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc]
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Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc]
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.srcs/constrs_1/new/slowClock.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/slowClock_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/slowClock_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Completed Processing XDC Constraints
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 789.797 ; gain = 0.000
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---------------------------------------------------------------------------------
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Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7a35tcsg324-1
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---------------------------------------------------------------------------------
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Applying 'set_property' XDC Constraints
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949
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---------------------------------------------------------------------------------
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INFO: [Synth 8-5545] ROM "clk_1Hz" won't be mapped to RAM because address size (26) is larger than maximum supported(25)
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INFO: [Synth 8-5546] ROM "clk_12Hz" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "clk_48Hz" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "clk_190Hz" won't be mapped to RAM because it is too sparse
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 789.797 ; gain = 476.949
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start RTL Component Statistics
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---------------------------------------------------------------------------------
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Detailed RTL Component Info :
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+---Adders :
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2 Input 26 Bit Adders := 1
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2 Input 23 Bit Adders := 1
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2 Input 21 Bit Adders := 1
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2 Input 19 Bit Adders := 1
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+---Registers :
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26 Bit Registers := 1
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23 Bit Registers := 1
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21 Bit Registers := 1
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19 Bit Registers := 1
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1 Bit Registers := 4
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+---Muxes :
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2 Input 26 Bit Muxes := 1
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2 Input 23 Bit Muxes := 1
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2 Input 21 Bit Muxes := 1
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2 Input 19 Bit Muxes := 1
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2 Input 1 Bit Muxes := 4
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---------------------------------------------------------------------------------
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Finished RTL Component Statistics
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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Hierarchical RTL Component report
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Module slowClock
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Detailed RTL Component Info :
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+---Adders :
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2 Input 26 Bit Adders := 1
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2 Input 23 Bit Adders := 1
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2 Input 21 Bit Adders := 1
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2 Input 19 Bit Adders := 1
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+---Registers :
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26 Bit Registers := 1
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23 Bit Registers := 1
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21 Bit Registers := 1
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19 Bit Registers := 1
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1 Bit Registers := 4
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+---Muxes :
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2 Input 26 Bit Muxes := 1
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2 Input 23 Bit Muxes := 1
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2 Input 21 Bit Muxes := 1
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2 Input 19 Bit Muxes := 1
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2 Input 1 Bit Muxes := 4
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---------------------------------------------------------------------------------
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Finished RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Part Resource Summary
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---------------------------------------------------------------------------------
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Part Resources:
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DSPs: 90 (col length:60)
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BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
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---------------------------------------------------------------------------------
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Finished Part Resource Summary
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Cross Boundary and Area Optimization
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---------------------------------------------------------------------------------
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Warning: Parallel synthesis criteria is not met
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INFO: [Synth 8-5545] ROM "clk_1Hz" won't be mapped to RAM because address size (26) is larger than maximum supported(25)
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INFO: [Synth 8-5546] ROM "clk_12Hz" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "clk_48Hz" won't be mapped to RAM because it is too sparse
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INFO: [Synth 8-5546] ROM "clk_190Hz" won't be mapped to RAM because it is too sparse
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---------------------------------------------------------------------------------
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 789.797 ; gain = 476.949
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start Applying XDC Timing Constraints
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 789.797 ; gain = 476.949
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Timing Optimization
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Timing Optimization : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 789.797 ; gain = 476.949
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start Technology Mapping
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Technology Mapping : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 797.371 ; gain = 484.523
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start IO Insertion
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Flattening Before IO Insertion
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Flattening Before IO Insertion
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Final Netlist Cleanup
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Final Netlist Cleanup
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished IO Insertion : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
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---------------------------------------------------------------------------------
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Report Check Netlist:
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+------+------------------+-------+---------+-------+------------------+
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| |Item |Errors |Warnings |Status |Description |
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+------+------------------+-------+---------+-------+------------------+
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|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
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+------+------------------+-------+---------+-------+------------------+
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---------------------------------------------------------------------------------
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Start Renaming Generated Instances
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start Rebuilding User Hierarchy
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Renaming Generated Ports
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Handling Custom Attributes
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Renaming Generated Nets
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Writing Synthesis Report
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---------------------------------------------------------------------------------
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Report BlackBoxes:
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+-+--------------+----------+
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| |BlackBox name |Instances |
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+-+--------------+----------+
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+-+--------------+----------+
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Report Cell Usage:
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+------+-------+------+
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| |Cell |Count |
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+------+-------+------+
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|1 |BUFG | 1|
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|2 |CARRY4 | 23|
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|3 |LUT1 | 3|
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|4 |LUT2 | 49|
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|5 |LUT3 | 1|
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|6 |LUT4 | 17|
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|7 |LUT5 | 2|
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|8 |LUT6 | 44|
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|9 |FDCE | 93|
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|10 |IBUF | 2|
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|11 |OBUF | 4|
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+------+-------+------+
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Report Instance Areas:
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+------+---------+-------+------+
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| |Instance |Module |Cells |
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+------+---------+-------+------+
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|1 |top | | 239|
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+------+---------+-------+------+
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---------------------------------------------------------------------------------
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Finished Writing Synthesis Report : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
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---------------------------------------------------------------------------------
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Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
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Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 797.371 ; gain = 159.191
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Synthesis Optimization Complete : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 797.371 ; gain = 484.523
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INFO: [Project 1-571] Translating synthesized netlist
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INFO: [Netlist 29-17] Analyzing 25 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-570] Preparing netlist for logic optimization
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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INFO: [Common 17-83] Releasing license: Synthesis
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22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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synth_design completed successfully
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synth_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 805.500 ; gain = 505.727
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INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp6-2/Exp6-2.runs/synth_1/slowClock.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_utilization -file slowClock_utilization_synth.rpt -pb slowClock_utilization_synth.pb
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report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 805.500 ; gain = 0.000
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INFO: [Common 17-206] Exiting Vivado at Thu Dec 12 20:12:13 2024...
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