95 lines
2.2 KiB
Verilog
95 lines
2.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/12/04 22:53:45
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// Design Name:
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// Module Name: slowClock
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module slowClock(
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input clk,
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input reset,
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output reg clk_1Hz,
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output reg clk_12Hz,
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output reg clk_48Hz,
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output reg clk_190Hz
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);
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parameter sys_clk = 100_000_000; // 100 MHz
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parameter clk_out1 = 1;
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parameter clk_out12 = 12;
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parameter clk_out48 = 48;
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parameter clk_out190 = 190;
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parameter max1 = sys_clk / (2 * clk_out1) - 1;
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parameter max12 = sys_clk / (2 * clk_out12) - 1;
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parameter max48 = sys_clk / (2 * clk_out48) - 1;
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parameter max190 = sys_clk / (2 * clk_out190) - 1;
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reg [25:0] counter1Hz;
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reg [22:0] counter12Hz;
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reg [20:0] counter48Hz;
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reg [18:0] counter190Hz;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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counter1Hz <= 0;
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clk_1Hz <= 0;
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counter12Hz <= 0;
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clk_12Hz <= 0;
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counter48Hz <= 0;
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clk_48Hz <= 0;
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counter190Hz <= 0;
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clk_190Hz <= 0;
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end
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else begin
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// 1 Hz
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if (counter1Hz == max1) begin
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counter1Hz <= 0;
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clk_1Hz <= ~clk_1Hz;
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end
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else begin
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counter1Hz <= counter1Hz + 1;
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end
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// 12 Hz
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if (counter12Hz == max12) begin
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counter12Hz <= 0;
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clk_12Hz <= ~clk_12Hz;
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end
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else begin
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counter12Hz <= counter12Hz + 1;
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end
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// 48 Hz
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if (counter48Hz == max48) begin
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counter48Hz <= 0;
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clk_48Hz <= ~clk_48Hz;
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end
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else begin
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counter48Hz <= counter48Hz + 1;
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end
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// 190 Hz
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if (counter190Hz == max190) begin
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counter190Hz <= 0;
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clk_190Hz <= ~clk_190Hz;
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end
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else begin
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counter190Hz <= counter190Hz + 1;
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end
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end
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end
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endmodule
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