38 lines
835 B
Verilog
38 lines
835 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/09/24 15:10:13
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// Design Name:
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// Module Name: sim4mux21
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module sim4mux21();
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reg a, b, c;
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wire y;
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mux21 uut(.a(a), .b(b), .c(c), .y(y));
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always begin
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a = 0; b = 0; c = 0; #100;
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a = 0; b = 0; c = 1; #100;
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a = 0; b = 1; c = 0; #100;
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a = 0; b = 1; c = 1; #100;
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a = 1; b = 0; c = 0; #100;
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a = 1; b = 0; c = 1; #100;
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a = 1; b = 1; c = 0; #100;
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a = 1; b = 1; c = 1; #100;
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end
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endmodule
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