28 lines
551 B
Verilog
28 lines
551 B
Verilog
`timescale 1ns / 1ps
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
// Company:
|
|
// Engineer:
|
|
//
|
|
// Create Date: 2024/09/24 15:07:05
|
|
// Design Name:
|
|
// Module Name: mux21
|
|
// Project Name:
|
|
// Target Devices:
|
|
// Tool Versions:
|
|
// Description:
|
|
//
|
|
// Dependencies:
|
|
//
|
|
// Revision:
|
|
// Revision 0.01 - File Created
|
|
// Additional Comments:
|
|
//
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
module mux21(a, b, c, y);
|
|
input a, b, c;
|
|
output y;
|
|
assign y = c ? b : a;
|
|
endmodule
|