416 lines
20 KiB
Plaintext
416 lines
20 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2018.1 (64-bit)
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# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
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# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
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# Start of session at: Thu Sep 26 11:15:35 2024
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# Process ID: 5212
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# Current directory: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1
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# Command line: vivado.exe -log mux41.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mux41.tcl -notrace
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# Log file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41.vdi
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# Journal file: F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1\vivado.jou
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#-----------------------------------------------------------
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source mux41.tcl -notrace
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Command: link_design -top mux41 -part xc7a35tcsg324-1
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2018.1
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INFO: [Device 21-403] Loading part xc7a35tcsg324-1
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc]
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Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.srcs/constrs_1/new/mux41.xdc]
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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link_design completed successfully
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link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 607.348 ; gain = 303.273
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Command: opt_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
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Running DRC as a precondition to command opt_design
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Starting DRC Task
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Project 1-461] DRC finished with 0 Errors
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INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 609.430 ; gain = 2.082
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Starting Logic Optimization Task
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Phase 1 Retarget
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Opt 31-49] Retargeted 0 cell(s).
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Phase 1 Retarget | Checksum: 1e3e1106b
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1130.844 ; gain = 0.000
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INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
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Phase 2 Constant propagation
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Phase 2 Constant propagation | Checksum: 1e3e1106b
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1130.844 ; gain = 0.000
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INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
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Phase 3 Sweep
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Phase 3 Sweep | Checksum: 1e3e1106b
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1130.844 ; gain = 0.000
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INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
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Phase 4 BUFG optimization
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Phase 4 BUFG optimization | Checksum: 1e3e1106b
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1130.844 ; gain = 0.000
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INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
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Phase 5 Shift Register Optimization
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Phase 5 Shift Register Optimization | Checksum: 1e3e1106b
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1130.844 ; gain = 0.000
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INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
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Phase 6 Post Processing Netlist
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Phase 6 Post Processing Netlist | Checksum: 1e3e1106b
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1130.844 ; gain = 0.000
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INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
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Starting Connectivity Check Task
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1130.844 ; gain = 0.000
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Ending Logic Optimization Task | Checksum: 1e3e1106b
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1130.844 ; gain = 0.000
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Starting Power Optimization Task
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INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
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Ending Power Optimization Task | Checksum: 1e3e1106b
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1130.844 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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opt_design completed successfully
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opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1130.844 ; gain = 523.496
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1130.844 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_opt.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file mux41_drc_opted.rpt -pb mux41_drc_opted.pb -rpx mux41_drc_opted.rpx
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Command: report_drc -file mux41_drc_opted.rpt -pb mux41_drc_opted.pb -rpx mux41_drc_opted.rpx
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_opted.rpt.
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report_drc completed successfully
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Command: place_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Running DRC as a precondition to command place_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Placer Task
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INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
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Phase 1 Placer Initialization
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Phase 1.1 Placer Initialization Netlist Sorting
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1133.133 ; gain = 0.000
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Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12f477d06
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1133.133 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1133.133 ; gain = 0.000
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12f477d06
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.362 . Memory (MB): peak = 1157.184 ; gain = 24.051
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Phase 1.3 Build Placer Netlist Model
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Phase 1.3 Build Placer Netlist Model | Checksum: 15695016a
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.370 . Memory (MB): peak = 1157.184 ; gain = 24.051
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Phase 1.4 Constrain Clocks/Macros
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Phase 1.4 Constrain Clocks/Macros | Checksum: 15695016a
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.371 . Memory (MB): peak = 1157.184 ; gain = 24.051
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Phase 1 Placer Initialization | Checksum: 15695016a
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.372 . Memory (MB): peak = 1157.184 ; gain = 24.051
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Phase 2 Global Placement
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Phase 2 Global Placement | Checksum: 224a517c0
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.529 . Memory (MB): peak = 1157.184 ; gain = 24.051
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Phase 3 Detail Placement
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Phase 3.1 Commit Multi Column Macros
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Phase 3.1 Commit Multi Column Macros | Checksum: 224a517c0
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.531 . Memory (MB): peak = 1157.184 ; gain = 24.051
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Phase 3.2 Commit Most Macros & LUTRAMs
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Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c91896ab
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.539 . Memory (MB): peak = 1157.184 ; gain = 24.051
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Phase 3.3 Area Swap Optimization
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Phase 3.3 Area Swap Optimization | Checksum: 15116b443
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.543 . Memory (MB): peak = 1157.184 ; gain = 24.051
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Phase 3.4 Pipeline Register Optimization
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Phase 3.4 Pipeline Register Optimization | Checksum: 15116b443
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.543 . Memory (MB): peak = 1157.184 ; gain = 24.051
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Phase 3.5 Small Shape Detail Placement
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Phase 3.5 Small Shape Detail Placement | Checksum: 1ac5be8b3
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.717 . Memory (MB): peak = 1157.637 ; gain = 24.504
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Phase 3.6 Re-assign LUT pins
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Phase 3.6 Re-assign LUT pins | Checksum: 1ac5be8b3
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.717 . Memory (MB): peak = 1157.637 ; gain = 24.504
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Phase 3.7 Pipeline Register Optimization
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Phase 3.7 Pipeline Register Optimization | Checksum: 1ac5be8b3
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.718 . Memory (MB): peak = 1157.637 ; gain = 24.504
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Phase 3 Detail Placement | Checksum: 1ac5be8b3
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.718 . Memory (MB): peak = 1157.637 ; gain = 24.504
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Phase 4 Post Placement Optimization and Clean-Up
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Phase 4.1 Post Commit Optimization
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Phase 4.1 Post Commit Optimization | Checksum: 1ac5be8b3
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.719 . Memory (MB): peak = 1157.637 ; gain = 24.504
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Phase 4.2 Post Placement Cleanup
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Phase 4.2 Post Placement Cleanup | Checksum: 1ac5be8b3
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1157.637 ; gain = 24.504
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Phase 4.3 Placer Reporting
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Phase 4.3 Placer Reporting | Checksum: 1ac5be8b3
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1157.637 ; gain = 24.504
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Phase 4.4 Final Placement Cleanup
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Phase 4.4 Final Placement Cleanup | Checksum: 1ac5be8b3
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.722 . Memory (MB): peak = 1157.637 ; gain = 24.504
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Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ac5be8b3
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.723 . Memory (MB): peak = 1157.637 ; gain = 24.504
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Ending Placer Task | Checksum: c54a07d5
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.724 . Memory (MB): peak = 1157.637 ; gain = 24.504
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INFO: [Common 17-83] Releasing license: Implementation
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41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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place_design completed successfully
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1159.215 ; gain = 1.578
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INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_placed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_io -file mux41_io_placed.rpt
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report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1170.410 ; gain = 0.000
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INFO: [runtcl-4] Executing : report_utilization -file mux41_utilization_placed.rpt -pb mux41_utilization_placed.pb
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report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1170.410 ; gain = 0.000
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INFO: [runtcl-4] Executing : report_control_sets -verbose -file mux41_control_sets_placed.rpt
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report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1170.410 ; gain = 0.000
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Command: route_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
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Running DRC as a precondition to command route_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Routing Task
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INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
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Checksum: PlaceDB: 153ecc1f ConstDB: 0 ShapeSum: b00b3bb6 RouteDB: 0
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Phase 1 Build RT Design
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Phase 1 Build RT Design | Checksum: c648ffa8
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1285.832 ; gain = 115.422
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Post Restoration Checksum: NetGraph: 2d5288c5 NumContArr: 98f676e3 Constraints: 0 Timing: 0
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Phase 2 Router Initialization
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INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
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Phase 2.1 Fix Topology Constraints
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Phase 2.1 Fix Topology Constraints | Checksum: c648ffa8
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.891 ; gain = 121.480
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Phase 2.2 Pre Route Cleanup
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Phase 2.2 Pre Route Cleanup | Checksum: c648ffa8
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1291.891 ; gain = 121.480
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Phase 2 Router Initialization | Checksum: c648ffa8
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1293.652 ; gain = 123.242
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Phase 3 Initial Routing
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Phase 3 Initial Routing | Checksum: 973162bc
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.652 ; gain = 123.242
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Phase 4 Rip-up And Reroute
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Phase 4.1 Global Iteration 0
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Number of Nodes with overlaps = 1
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Number of Nodes with overlaps = 0
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Phase 4.1 Global Iteration 0 | Checksum: d4df4150
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
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Phase 4 Rip-up And Reroute | Checksum: d4df4150
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
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Phase 5 Delay and Skew Optimization
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Phase 5 Delay and Skew Optimization | Checksum: d4df4150
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
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Phase 6 Post Hold Fix
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Phase 6.1 Hold Fix Iter
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Phase 6.1 Hold Fix Iter | Checksum: d4df4150
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
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Phase 6 Post Hold Fix | Checksum: d4df4150
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
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Phase 7 Route finalize
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Router Utilization Summary
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Global Vertical Routing Utilization = 0.00398629 %
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Global Horizontal Routing Utilization = 0.00221239 %
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Routable Net Status*
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*Does not include unroutable nets such as driverless and loadless.
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Run report_route_status for detailed report.
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Number of Failed Nets = 0
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Number of Unrouted Nets = 0
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Number of Partially Routed Nets = 0
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Number of Node Overlaps = 0
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Congestion Report
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North Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions.
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South Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions.
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East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
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West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
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------------------------------
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Reporting congestion hotspots
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------------------------------
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Direction: North
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: South
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: East
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: West
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Phase 7 Route finalize | Checksum: d4df4150
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1293.688 ; gain = 123.277
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Phase 8 Verifying routed nets
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Verification completed successfully
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Phase 8 Verifying routed nets | Checksum: d4df4150
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293
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Phase 9 Depositing Routes
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Phase 9 Depositing Routes | Checksum: d4df4150
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293
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INFO: [Route 35-16] Router Completed Successfully
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Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293
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Routing Is Done.
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INFO: [Common 17-83] Releasing license: Implementation
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54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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route_design completed successfully
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route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1295.703 ; gain = 125.293
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1295.703 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_routed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file mux41_drc_routed.rpt -pb mux41_drc_routed.pb -rpx mux41_drc_routed.rpx
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Command: report_drc -file mux41_drc_routed.rpt -pb mux41_drc_routed.pb -rpx mux41_drc_routed.rpx
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_drc_routed.rpt.
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report_drc completed successfully
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INFO: [runtcl-4] Executing : report_methodology -file mux41_methodology_drc_routed.rpt -pb mux41_methodology_drc_routed.pb -rpx mux41_methodology_drc_routed.rpx
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Command: report_methodology -file mux41_methodology_drc_routed.rpt -pb mux41_methodology_drc_routed.pb -rpx mux41_methodology_drc_routed.rpx
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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INFO: [DRC 23-133] Running Methodology with 2 threads
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INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp1-2-2/Exp1-2-2.runs/impl_1/mux41_methodology_drc_routed.rpt.
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report_methodology completed successfully
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INFO: [runtcl-4] Executing : report_power -file mux41_power_routed.rpt -pb mux41_power_summary_routed.pb -rpx mux41_power_routed.rpx
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Command: report_power -file mux41_power_routed.rpt -pb mux41_power_summary_routed.pb -rpx mux41_power_routed.rpx
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WARNING: [Power 33-232] No user defined clocks were found in the design!
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Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Running Vector-less Activity Propagation...
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Finished Running Vector-less Activity Propagation
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66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
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report_power completed successfully
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INFO: [runtcl-4] Executing : report_route_status -file mux41_route_status.rpt -pb mux41_route_status.pb
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INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file mux41_timing_summary_routed.rpt -pb mux41_timing_summary_routed.pb -rpx mux41_timing_summary_routed.rpx -warn_on_violation
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
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WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
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INFO: [runtcl-4] Executing : report_incremental_reuse -file mux41_incremental_reuse_routed.rpt
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INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
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INFO: [runtcl-4] Executing : report_clock_utilization -file mux41_clock_utilization_routed.rpt
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INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
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INFO: [Common 17-206] Exiting Vivado at Thu Sep 26 11:16:12 2024...
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