38 lines
713 B
Verilog
38 lines
713 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/09/25 20:04:39
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// Design Name:
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// Module Name: LU
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module LU(a, b, s, Y);
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input a, b;
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input [1:0] s;
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output Y;
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reg Y;
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always @(*) begin
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case (s)
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2'b00: Y = a & b;
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2'b01: Y = a | b;
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2'b10: Y = a ^ b;
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2'b11: Y = 0;
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default: Y = 0;
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endcase
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end
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endmodule
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