307 lines
19 KiB
Plaintext
307 lines
19 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2018.1 (64-bit)
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# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
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# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
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# Start of session at: Wed Nov 6 20:19:40 2024
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# Process ID: 27608
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# Current directory: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1
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# Command line: vivado.exe -log encoder.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source encoder.tcl
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# Log file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1/encoder.vds
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# Journal file: F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1\vivado.jou
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#-----------------------------------------------------------
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source encoder.tcl -notrace
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Command: synth_design -top encoder -part xc7a35tcsg324-1
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 26504
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---------------------------------------------------------------------------------
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Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 409.770 ; gain = 97.609
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'encoder' [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v:23]
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INFO: [Synth 8-6157] synthesizing module 'SegDisplayCtrl' [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/SegDisplayCtrl.v:22]
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INFO: [Synth 8-226] default block is never used [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/SegDisplayCtrl.v:29]
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INFO: [Synth 8-6155] done synthesizing module 'SegDisplayCtrl' (1#1) [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/SegDisplayCtrl.v:22]
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INFO: [Synth 8-6155] done synthesizing module 'encoder' (2#1) [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v:23]
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WARNING: [Synth 8-3917] design encoder has port seg_cs1[3] driven by constant 0
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WARNING: [Synth 8-3917] design encoder has port seg_cs1[2] driven by constant 0
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WARNING: [Synth 8-3917] design encoder has port seg_cs1[1] driven by constant 0
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WARNING: [Synth 8-3917] design encoder has port seg_cs1[0] driven by constant 1
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WARNING: [Synth 8-3917] design encoder has port seg_cs2[3] driven by constant 0
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WARNING: [Synth 8-3917] design encoder has port seg_cs2[2] driven by constant 0
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WARNING: [Synth 8-3917] design encoder has port seg_cs2[1] driven by constant 0
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WARNING: [Synth 8-3917] design encoder has port seg_cs2[0] driven by constant 1
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---------------------------------------------------------------------------------
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Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 464.227 ; gain = 152.066
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---------------------------------------------------------------------------------
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Report Check Netlist:
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+------+------------------+-------+---------+-------+------------------+
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| |Item |Errors |Warnings |Status |Description |
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+------+------------------+-------+---------+-------+------------------+
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|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
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+------+------------------+-------+---------+-------+------------------+
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---------------------------------------------------------------------------------
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Start Handling Custom Attributes
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 464.227 ; gain = 152.066
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 464.227 ; gain = 152.066
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---------------------------------------------------------------------------------
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INFO: [Device 21-403] Loading part xc7a35tcsg324-1
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Processing XDC Constraints
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Initializing timing engine
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Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc]
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Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc]
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/constrs_1/new/encoder.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/encoder_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/encoder_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Completed Processing XDC Constraints
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INFO: [Project 1-111] Unisim Transformation Summary:
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No Unisim elements were transformed.
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Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 745.281 ; gain = 0.000
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---------------------------------------------------------------------------------
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Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 745.281 ; gain = 433.121
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7a35tcsg324-1
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---------------------------------------------------------------------------------
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 745.281 ; gain = 433.121
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Applying 'set_property' XDC Constraints
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 745.281 ; gain = 433.121
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---------------------------------------------------------------------------------
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INFO: [Synth 8-5546] ROM "out" won't be mapped to RAM because it is too sparse
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WARNING: [Synth 8-327] inferring latch for variable 'i_sig_reg' [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v:40]
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WARNING: [Synth 8-327] inferring latch for variable 'Y_reg' [F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.srcs/sources_1/new/encoder.v:40]
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 745.281 ; gain = 433.121
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start RTL Component Statistics
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---------------------------------------------------------------------------------
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Detailed RTL Component Info :
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+---Muxes :
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2 Input 8 Bit Muxes := 1
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9 Input 8 Bit Muxes := 1
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8 Input 7 Bit Muxes := 1
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9 Input 3 Bit Muxes := 2
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9 Input 1 Bit Muxes := 1
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---------------------------------------------------------------------------------
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Finished RTL Component Statistics
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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Hierarchical RTL Component report
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Module encoder
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Detailed RTL Component Info :
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+---Muxes :
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9 Input 8 Bit Muxes := 1
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9 Input 3 Bit Muxes := 2
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9 Input 1 Bit Muxes := 1
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Module SegDisplayCtrl
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Detailed RTL Component Info :
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+---Muxes :
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2 Input 8 Bit Muxes := 1
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8 Input 7 Bit Muxes := 1
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---------------------------------------------------------------------------------
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Finished RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Part Resource Summary
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---------------------------------------------------------------------------------
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Part Resources:
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DSPs: 90 (col length:60)
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BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
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---------------------------------------------------------------------------------
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Finished Part Resource Summary
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Cross Boundary and Area Optimization
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---------------------------------------------------------------------------------
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Warning: Parallel synthesis criteria is not met
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INFO: [Synth 8-5546] ROM "out" won't be mapped to RAM because it is too sparse
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WARNING: [Synth 8-3917] design encoder has port seg2[6] driven by constant 0
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WARNING: [Synth 8-3917] design encoder has port seg2[5] driven by constant 0
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WARNING: [Synth 8-3917] design encoder has port seg_cs1[3] driven by constant 0
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WARNING: [Synth 8-3917] design encoder has port seg_cs1[2] driven by constant 0
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WARNING: [Synth 8-3917] design encoder has port seg_cs1[1] driven by constant 0
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WARNING: [Synth 8-3917] design encoder has port seg_cs1[0] driven by constant 1
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WARNING: [Synth 8-3917] design encoder has port seg_cs2[3] driven by constant 0
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WARNING: [Synth 8-3917] design encoder has port seg_cs2[2] driven by constant 0
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WARNING: [Synth 8-3917] design encoder has port seg_cs2[1] driven by constant 0
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WARNING: [Synth 8-3917] design encoder has port seg_cs2[0] driven by constant 1
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---------------------------------------------------------------------------------
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 745.281 ; gain = 433.121
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start Applying XDC Timing Constraints
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 784.875 ; gain = 472.715
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Timing Optimization
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 784.875 ; gain = 472.715
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start Technology Mapping
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 784.949 ; gain = 472.789
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start IO Insertion
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---------------------------------------------------------------------------------
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Start Flattening Before IO Insertion
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---------------------------------------------------------------------------------
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Finished Flattening Before IO Insertion
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Final Netlist Cleanup
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Final Netlist Cleanup
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918
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---------------------------------------------------------------------------------
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Report Check Netlist:
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+------+------------------+-------+---------+-------+------------------+
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| |Item |Errors |Warnings |Status |Description |
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+------+------------------+-------+---------+-------+------------------+
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|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
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+------+------------------+-------+---------+-------+------------------+
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---------------------------------------------------------------------------------
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Start Renaming Generated Instances
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start Rebuilding User Hierarchy
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Renaming Generated Ports
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Handling Custom Attributes
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Renaming Generated Nets
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Writing Synthesis Report
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---------------------------------------------------------------------------------
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Report BlackBoxes:
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+-+--------------+----------+
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| |BlackBox name |Instances |
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+-+--------------+----------+
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+-+--------------+----------+
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Report Cell Usage:
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+------+-----+------+
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| |Cell |Count |
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+------+-----+------+
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|1 |LUT1 | 7|
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|2 |LUT2 | 1|
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|3 |LUT3 | 7|
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|4 |LUT4 | 3|
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|5 |LUT5 | 2|
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|6 |LUT6 | 3|
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|7 |LD | 11|
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|8 |IBUF | 9|
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|9 |OBUF | 31|
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+------+-----+------+
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Report Instance Areas:
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+------+---------+---------------+------+
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| |Instance |Module |Cells |
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+------+---------+---------------+------+
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|1 |top | | 74|
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|2 | unit |SegDisplayCtrl | 5|
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+------+---------+---------------+------+
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---------------------------------------------------------------------------------
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Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.078 ; gain = 473.918
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---------------------------------------------------------------------------------
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Synthesis finished with 0 errors, 0 critical warnings and 12 warnings.
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Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 786.082 ; gain = 192.867
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Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 786.082 ; gain = 473.922
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INFO: [Project 1-571] Translating synthesized netlist
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INFO: [Netlist 29-17] Analyzing 20 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-570] Preparing netlist for logic optimization
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Project 1-111] Unisim Transformation Summary:
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A total of 11 instances were transformed.
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LD => LDCE: 11 instances
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INFO: [Common 17-83] Releasing license: Synthesis
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19 Infos, 20 Warnings, 0 Critical Warnings and 0 Errors encountered.
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synth_design completed successfully
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synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 807.133 ; gain = 507.688
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INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp3-1/Exp3-1.runs/synth_1/encoder.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_utilization -file encoder_utilization_synth.rpt -pb encoder_utilization_synth.pb
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report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 807.133 ; gain = 0.000
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INFO: [Common 17-206] Exiting Vivado at Wed Nov 6 20:20:03 2024...
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