47 lines
1.1 KiB
Verilog
47 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/10/30 23:15:29
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// Design Name:
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// Module Name: SegDisplayCtrl
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module SegDisplayCtrl(
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input wire [2:0] Y,
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input wire out,
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output reg [6:0] seg1,
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output reg [7:0] seg2
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);
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always @(*) begin
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case (Y)
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3'b000: seg1 = 7'b1111110; // 0
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3'b001: seg1 = 7'b0110000; // 1
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3'b010: seg1 = 7'b1101101; // 2
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3'b011: seg1 = 7'b1111001; // 3
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3'b100: seg1 = 7'b0110011; // 4
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3'b101: seg1 = 7'b1011011; // 5
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3'b110: seg1 = 7'b1011111; // 6
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3'b111: seg1 = 7'b1110000; // 7
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default: seg1 = 7'b0000000;
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endcase
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if (out)
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seg2 = 8'b00000001;
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else
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seg2 = 8'b10011110;
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end
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endmodule
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