451 lines
23 KiB
Plaintext
451 lines
23 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2018.1 (64-bit)
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# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
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# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
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# Start of session at: Thu Nov 7 02:28:43 2024
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# Process ID: 25584
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# Current directory: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1
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# Command line: vivado.exe -log calc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source calc.tcl -notrace
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# Log file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc.vdi
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# Journal file: F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1\vivado.jou
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#-----------------------------------------------------------
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source calc.tcl -notrace
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Command: link_design -top calc -part xc7a35tcsg324-1
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Design is defaulting to srcset: sources_1
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Design is defaulting to constrset: constrs_1
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INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-479] Netlist was created with Vivado 2018.1
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INFO: [Device 21-403] Loading part xc7a35tcsg324-1
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INFO: [Project 1-570] Preparing netlist for logic optimization
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Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc]
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Finished Parsing XDC File [F:/Schoolwork/DigitalLogic/Exp4/Exp4.srcs/constrs_1/new/calc.xdc]
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Project 1-111] Unisim Transformation Summary:
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A total of 2 instances were transformed.
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LDCP => LDCP (GND, LUT3, LUT3, LDCE, VCC): 2 instances
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7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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link_design completed successfully
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link_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 608.344 ; gain = 303.082
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Command: opt_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
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Running DRC as a precondition to command opt_design
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Starting DRC Task
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Project 1-461] DRC finished with 0 Errors
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INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.373 . Memory (MB): peak = 623.590 ; gain = 15.246
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Starting Logic Optimization Task
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Phase 1 Retarget
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Opt 31-49] Retargeted 0 cell(s).
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Phase 1 Retarget | Checksum: 276aac3f7
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1170.543 ; gain = 0.000
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INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
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Phase 2 Constant propagation
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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Phase 2 Constant propagation | Checksum: 276aac3f7
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1170.543 ; gain = 0.000
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INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
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Phase 3 Sweep
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Phase 3 Sweep | Checksum: 276aac3f7
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1170.543 ; gain = 0.000
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INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
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Phase 4 BUFG optimization
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Phase 4 BUFG optimization | Checksum: 276aac3f7
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1170.543 ; gain = 0.000
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INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
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Phase 5 Shift Register Optimization
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Phase 5 Shift Register Optimization | Checksum: 276aac3f7
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1170.543 ; gain = 0.000
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INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
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Phase 6 Post Processing Netlist
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Phase 6 Post Processing Netlist | Checksum: 276aac3f7
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1170.543 ; gain = 0.000
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INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
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Starting Connectivity Check Task
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1170.543 ; gain = 0.000
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Ending Logic Optimization Task | Checksum: 276aac3f7
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1170.543 ; gain = 0.000
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Starting Power Optimization Task
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INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
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Ending Power Optimization Task | Checksum: 276aac3f7
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1170.543 ; gain = 0.000
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INFO: [Common 17-83] Releasing license: Implementation
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23 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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opt_design completed successfully
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opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1170.543 ; gain = 562.199
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1170.543 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_opt.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file calc_drc_opted.rpt -pb calc_drc_opted.pb -rpx calc_drc_opted.rpx
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Command: report_drc -file calc_drc_opted.rpt -pb calc_drc_opted.pb -rpx calc_drc_opted.rpx
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2018.1/data/ip'.
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_drc_opted.rpt.
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report_drc completed successfully
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Command: place_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Running DRC as a precondition to command place_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Placer Task
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INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
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Phase 1 Placer Initialization
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Phase 1.1 Placer Initialization Netlist Sorting
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1170.543 ; gain = 0.000
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Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e2929c37
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1170.543 ; gain = 0.000
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1170.543 ; gain = 0.000
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 137b1e3de
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.322 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 1.3 Build Placer Netlist Model
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Phase 1.3 Build Placer Netlist Model | Checksum: 1dab45a3d
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.330 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 1.4 Constrain Clocks/Macros
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Phase 1.4 Constrain Clocks/Macros | Checksum: 1dab45a3d
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.330 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 1 Placer Initialization | Checksum: 1dab45a3d
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.331 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 2 Global Placement
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Phase 2 Global Placement | Checksum: 1e6d939ab
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.463 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 3 Detail Placement
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Phase 3.1 Commit Multi Column Macros
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Phase 3.1 Commit Multi Column Macros | Checksum: 1e6d939ab
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.464 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 3.2 Commit Most Macros & LUTRAMs
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Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 219db61c9
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.470 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 3.3 Area Swap Optimization
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Phase 3.3 Area Swap Optimization | Checksum: 151450402
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.474 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 3.4 Pipeline Register Optimization
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Phase 3.4 Pipeline Register Optimization | Checksum: 151450402
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.474 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 3.5 Small Shape Detail Placement
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Phase 3.5 Small Shape Detail Placement | Checksum: 14e2b920e
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.516 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 3.6 Re-assign LUT pins
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Phase 3.6 Re-assign LUT pins | Checksum: 14e2b920e
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.519 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 3.7 Pipeline Register Optimization
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Phase 3.7 Pipeline Register Optimization | Checksum: 14e2b920e
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.519 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 3 Detail Placement | Checksum: 14e2b920e
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.519 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 4 Post Placement Optimization and Clean-Up
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Phase 4.1 Post Commit Optimization
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Phase 4.1 Post Commit Optimization | Checksum: 14e2b920e
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.521 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 4.2 Post Placement Cleanup
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Phase 4.2 Post Placement Cleanup | Checksum: 14e2b920e
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.522 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 4.3 Placer Reporting
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Phase 4.3 Placer Reporting | Checksum: 14e2b920e
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.523 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 4.4 Final Placement Cleanup
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Phase 4.4 Final Placement Cleanup | Checksum: 14e2b920e
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.523 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Phase 4 Post Placement Optimization and Clean-Up | Checksum: 14e2b920e
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.523 . Memory (MB): peak = 1183.531 ; gain = 12.988
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Ending Placer Task | Checksum: 1015e41ce
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.525 . Memory (MB): peak = 1183.531 ; gain = 12.988
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INFO: [Common 17-83] Releasing license: Implementation
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41 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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place_design completed successfully
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1183.531 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_placed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_io -file calc_io_placed.rpt
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report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1188.391 ; gain = 0.000
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INFO: [runtcl-4] Executing : report_utilization -file calc_utilization_placed.rpt -pb calc_utilization_placed.pb
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report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1188.391 ; gain = 0.000
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INFO: [runtcl-4] Executing : report_control_sets -verbose -file calc_control_sets_placed.rpt
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report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1188.391 ; gain = 0.000
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Command: route_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
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Running DRC as a precondition to command route_design
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
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INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
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Starting Routing Task
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INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
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Checksum: PlaceDB: 37ead21 ConstDB: 0 ShapeSum: fddf94ad RouteDB: 0
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Phase 1 Build RT Design
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Phase 1 Build RT Design | Checksum: bf67df9b
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1302.117 ; gain = 113.727
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Post Restoration Checksum: NetGraph: 4572a9c8 NumContArr: 79f535d3 Constraints: 0 Timing: 0
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Phase 2 Router Initialization
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INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
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Phase 2.1 Fix Topology Constraints
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Phase 2.1 Fix Topology Constraints | Checksum: bf67df9b
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1308.117 ; gain = 119.727
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Phase 2.2 Pre Route Cleanup
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Phase 2.2 Pre Route Cleanup | Checksum: bf67df9b
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1308.117 ; gain = 119.727
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Number of Nodes with overlaps = 0
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Phase 2 Router Initialization | Checksum: 11937b63c
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
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Phase 3 Initial Routing
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Phase 3 Initial Routing | Checksum: 1a7a41aad
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
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Phase 4 Rip-up And Reroute
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Phase 4.1 Global Iteration 0
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Number of Nodes with overlaps = 6
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Number of Nodes with overlaps = 0
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Phase 4.1 Global Iteration 0 | Checksum: b875e9c3
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
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Phase 4 Rip-up And Reroute | Checksum: b875e9c3
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
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Phase 5 Delay and Skew Optimization
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Phase 5 Delay and Skew Optimization | Checksum: b875e9c3
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
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Phase 6 Post Hold Fix
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Phase 6.1 Hold Fix Iter
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Phase 6.1 Hold Fix Iter | Checksum: b875e9c3
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
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Phase 6 Post Hold Fix | Checksum: b875e9c3
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
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Phase 7 Route finalize
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Router Utilization Summary
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Global Vertical Routing Utilization = 0.0557283 %
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Global Horizontal Routing Utilization = 0.0265487 %
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Routable Net Status*
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*Does not include unroutable nets such as driverless and loadless.
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Run report_route_status for detailed report.
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Number of Failed Nets = 0
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Number of Unrouted Nets = 0
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Number of Partially Routed Nets = 0
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Number of Node Overlaps = 0
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Congestion Report
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North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions.
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South Dir 1x1 Area, Max Cong = 26.1261%, No Congested Regions.
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East Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions.
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West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions.
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------------------------------
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Reporting congestion hotspots
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------------------------------
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Direction: North
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: South
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: East
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Direction: West
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----------------
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Congested clusters found at Level 0
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Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
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Phase 7 Route finalize | Checksum: b875e9c3
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1310.898 ; gain = 122.508
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Phase 8 Verifying routed nets
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Verification completed successfully
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Phase 8 Verifying routed nets | Checksum: b875e9c3
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.164 ; gain = 123.773
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Phase 9 Depositing Routes
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Phase 9 Depositing Routes | Checksum: 144801a5b
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.164 ; gain = 123.773
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INFO: [Route 35-16] Router Completed Successfully
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Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.164 ; gain = 123.773
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Routing Is Done.
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INFO: [Common 17-83] Releasing license: Implementation
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54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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route_design completed successfully
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route_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1312.164 ; gain = 123.773
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Writing placer database...
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Writing XDEF routing special nets.
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Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1312.164 ; gain = 0.000
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INFO: [Common 17-1381] The checkpoint 'F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_routed.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_drc -file calc_drc_routed.rpt -pb calc_drc_routed.pb -rpx calc_drc_routed.rpx
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Command: report_drc -file calc_drc_routed.rpt -pb calc_drc_routed.pb -rpx calc_drc_routed.rpx
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INFO: [DRC 23-27] Running DRC with 2 threads
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INFO: [Coretcl 2-168] The results of DRC are in file F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_drc_routed.rpt.
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report_drc completed successfully
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INFO: [runtcl-4] Executing : report_methodology -file calc_methodology_drc_routed.rpt -pb calc_methodology_drc_routed.pb -rpx calc_methodology_drc_routed.rpx
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Command: report_methodology -file calc_methodology_drc_routed.rpt -pb calc_methodology_drc_routed.pb -rpx calc_methodology_drc_routed.rpx
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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INFO: [DRC 23-133] Running Methodology with 2 threads
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INFO: [Coretcl 2-1520] The results of Report Methodology are in file F:/Schoolwork/DigitalLogic/Exp4/Exp4.runs/impl_1/calc_methodology_drc_routed.rpt.
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report_methodology completed successfully
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INFO: [runtcl-4] Executing : report_power -file calc_power_routed.rpt -pb calc_power_summary_routed.pb -rpx calc_power_routed.rpx
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Command: report_power -file calc_power_routed.rpt -pb calc_power_summary_routed.pb -rpx calc_power_routed.rpx
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WARNING: [Power 33-232] No user defined clocks were found in the design!
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Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
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INFO: [Timing 38-35] Done setting XDC timing constraints.
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Running Vector-less Activity Propagation...
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Finished Running Vector-less Activity Propagation
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66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
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report_power completed successfully
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INFO: [runtcl-4] Executing : report_route_status -file calc_route_status.rpt -pb calc_route_status.pb
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INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file calc_timing_summary_routed.rpt -pb calc_timing_summary_routed.pb -rpx calc_timing_summary_routed.rpx -warn_on_violation
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
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WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
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INFO: [runtcl-4] Executing : report_incremental_reuse -file calc_incremental_reuse_routed.rpt
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INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
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INFO: [runtcl-4] Executing : report_clock_utilization -file calc_clock_utilization_routed.rpt
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INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file route_report_bus_skew_0.rpt -rpx route_report_bus_skew_0.rpx
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
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Command: write_bitstream -force calc.bit
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Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
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Running DRC as a precondition to command write_bitstream
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INFO: [DRC 23-27] Running DRC with 2 threads
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WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
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set_property CFGBVS value1 [current_design]
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|
#where value1 is either VCCO or GND
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|
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set_property CONFIG_VOLTAGE value2 [current_design]
|
|
#where value2 is the voltage provided to configuration bank 0
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|
Refer to the device configuration user guide for more information.
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WARNING: [DRC PDRC-153] Gated clock check: Net run/result_reg[2]/G0 is a gated clock net sourced by a combinational pin run/result_reg[2]/L3_2/O, cell run/result_reg[2]/L3_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
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WARNING: [DRC PDRC-153] Gated clock check: Net run/result_reg[3]/G0 is a gated clock net sourced by a combinational pin run/result_reg[3]/L3_2/O, cell run/result_reg[3]/L3_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
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WARNING: [DRC PDRC-153] Gated clock check: Net run/result_reg[3]_i_1_n_0 is a gated clock net sourced by a combinational pin run/result_reg[3]_i_1/O, cell run/result_reg[3]_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
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INFO: [Vivado 12-3199] DRC finished with 0 Errors, 4 Warnings
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INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
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INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
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Loading data files...
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Loading site data...
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Loading route data...
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Processing options...
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Creating bitmap...
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Creating bitstream...
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Writing bitstream ./calc.bit...
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INFO: [Vivado 12-1842] Bitgen Completed Successfully.
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INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
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INFO: [Common 17-83] Releasing license: Implementation
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84 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
write_bitstream completed successfully
|
|
write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1766.340 ; gain = 420.117
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INFO: [Common 17-206] Exiting Vivado at Thu Nov 7 02:29:25 2024...
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