31 lines
602 B
Verilog
31 lines
602 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2024/11/24 20:29:26
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// Design Name:
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// Module Name: DFlipFlop
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module DFlipFlop (
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input wire D,
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input wire clk,
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output reg Q
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);
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always @(posedge clk) begin
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Q <= D;
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end
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endmodule |