40 lines
816 B
Verilog
40 lines
816 B
Verilog
`timescale 1ns / 1ps
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
// Company:
|
|
// Engineer:
|
|
//
|
|
// Create Date: 2024/11/24 23:42:48
|
|
// Design Name:
|
|
// Module Name: Register32
|
|
// Project Name:
|
|
// Target Devices:
|
|
// Tool Versions:
|
|
// Description:
|
|
//
|
|
// Dependencies:
|
|
//
|
|
// Revision:
|
|
// Revision 0.01 - File Created
|
|
// Additional Comments:
|
|
//
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
module Register32 (
|
|
input wire [31:0] D,
|
|
input wire clk,
|
|
input wire rst,
|
|
input wire set,
|
|
output reg [31:0] Q
|
|
);
|
|
always @(posedge clk or posedge rst or posedge set) begin
|
|
if (rst)
|
|
Q <= 32'h00000000; // Reset clear
|
|
else if (set)
|
|
Q <= 32'hFFFFFFFF; // Set all 1
|
|
else
|
|
Q <= D;
|
|
end
|
|
endmodule
|
|
|