diff --git a/CourseDesignReport.docx b/CourseDesignReport.docx new file mode 100644 index 0000000..404b499 Binary files /dev/null and b/CourseDesignReport.docx differ diff --git a/Hardware/LA32R.cache/wt/webtalk_pa.xml b/Hardware/LA32R.cache/wt/webtalk_pa.xml index a009afc..91f5897 100644 --- a/Hardware/LA32R.cache/wt/webtalk_pa.xml +++ b/Hardware/LA32R.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,81 +17,93 @@ This means code written to parse this file will need to be revisited each subseq - + + - - - - + + + + - - - - + + + + - - + + - + + - - + + - - + + - + + - - + + + + - - - - - - + + + + + + - - + + + + - - - - + + + + + + + + + - + - - + + - + - +
diff --git a/Hardware/LA32R.sim/sim_1/behav/xsim/webtalk.jou b/Hardware/LA32R.sim/sim_1/behav/xsim/webtalk.jou index 9a83fb7..a506aee 100644 --- a/Hardware/LA32R.sim/sim_1/behav/xsim/webtalk.jou +++ b/Hardware/LA32R.sim/sim_1/behav/xsim/webtalk.jou @@ -2,8 +2,8 @@ # Webtalk v2018.1 (64-bit) # SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 -# Start of session at: Wed Jun 18 20:13:54 2025 -# Process ID: 21412 +# Start of session at: Fri Jun 20 18:50:01 2025 +# Process ID: 32760 # Current directory: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim # Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim/xsim.dir/cpu_tb_snapshot/webtalk/xsim_webtalk.tcl -notrace # Log file: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim/webtalk.log diff --git a/Hardware/LA32R.sim/sim_1/behav/xsim/webtalk_30320.backup.jou b/Hardware/LA32R.sim/sim_1/behav/xsim/webtalk_28472.backup.jou similarity index 92% rename from Hardware/LA32R.sim/sim_1/behav/xsim/webtalk_30320.backup.jou rename to Hardware/LA32R.sim/sim_1/behav/xsim/webtalk_28472.backup.jou index fb4f4b4..c290914 100644 --- a/Hardware/LA32R.sim/sim_1/behav/xsim/webtalk_30320.backup.jou +++ b/Hardware/LA32R.sim/sim_1/behav/xsim/webtalk_28472.backup.jou @@ -2,8 +2,8 @@ # Webtalk v2018.1 (64-bit) # SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 -# Start of session at: Wed Jun 18 20:13:51 2025 -# Process ID: 30320 +# Start of session at: Fri Jun 20 18:49:58 2025 +# Process ID: 28472 # Current directory: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim # Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim/xsim.dir/cpu_tb_snapshot/webtalk/xsim_webtalk.tcl -notrace # Log file: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim/webtalk.log diff --git a/Hardware/LA32R.sim/sim_1/behav/xsim/xsim.dir/cpu_tb_snapshot/xsim.mem b/Hardware/LA32R.sim/sim_1/behav/xsim/xsim.dir/cpu_tb_snapshot/xsim.mem index 519660a..d754a16 100644 Binary files a/Hardware/LA32R.sim/sim_1/behav/xsim/xsim.dir/cpu_tb_snapshot/xsim.mem and b/Hardware/LA32R.sim/sim_1/behav/xsim/xsim.dir/cpu_tb_snapshot/xsim.mem differ diff --git a/Hardware/LA32R.sim/sim_1/behav/xsim/xsim.jou b/Hardware/LA32R.sim/sim_1/behav/xsim/xsim.jou index be642bc..c84647d 100644 --- a/Hardware/LA32R.sim/sim_1/behav/xsim/xsim.jou +++ b/Hardware/LA32R.sim/sim_1/behav/xsim/xsim.jou @@ -2,8 +2,8 @@ # xsim v2018.1 (64-bit) # SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018 # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 -# Start of session at: Wed Jun 18 20:13:51 2025 -# Process ID: 20256 +# Start of session at: Fri Jun 20 18:49:58 2025 +# Process ID: 27168 # Current directory: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim # Command line: xsim.exe -log ..\..\..\..\..\simulation.log -mode tcl -source {xsim.dir/cpu_tb_snapshot/xsim_script.tcl} # Log file: D:/Schoolwork/ComputerComposition/LA32R/Hardware/LA32R.sim/sim_1/behav/xsim/../../../../../simulation.log diff --git a/Hardware/LA32R.srcs/sim_1/new/cpu_tb.v b/Hardware/LA32R.srcs/sim_1/new/cpu_tb.v index 5ee2fae..a1c20f8 100644 --- a/Hardware/LA32R.srcs/sim_1/new/cpu_tb.v +++ b/Hardware/LA32R.srcs/sim_1/new/cpu_tb.v @@ -31,8 +31,6 @@ ** - "program.hex" 的路径在 `instruction_memory.v` 模块中指定。 *******************************************************************************/ -`timescale 1ns / 1ps - module cpu_tb; // --- 信号声明 --- @@ -66,7 +64,7 @@ module cpu_tb; // 2. 设定仿真运行时间后停止 // 由于测试程序末尾通常是无限循环，因此需要手动设置仿真停止时间。 - #500; // 仿真运行500纳秒 + #5000; // 仿真运行5000纳秒 // 3. 仿真结束前，打印寄存器堆的最终状态 $display("\n------------------------------------------------------------"); @@ -89,13 +87,10 @@ module cpu_tb; // 在每个时钟周期的下降沿采样并显示信息，以确保在该时刻所有待显示的信号值均已稳定。 always @(negedge clk) begin if (!rst) begin //仅在非复位状态下显示 - $display("时间: %0t ns | PC: 0x%08h | 指令: 0x%08h | R4=0x%h R5=0x%h R6=0x%h", + $display("时间: %0t ns | PC: 0x%08h | 指令: 0x%08h", $time, // 当前仿真时间 uut.pc_out, // PC的当前值 - uut.instr, // 当前PC指向的指令 - uut.u_reg_file.registers[4], // R4寄存器的值 - uut.u_reg_file.registers[5], // R5寄存器的值 - uut.u_reg_file.registers[6] // R6寄存器的值 + uut.instr // 当前PC指向的指令 ); end end diff --git a/Hardware/LA32R.xpr b/Hardware/LA32R.xpr index fd224b2..cab3917 100644 --- a/Hardware/LA32R.xpr +++ b/Hardware/LA32R.xpr @@ -31,7 +31,7 @@