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This commit updates all comments in Verilog source files, the Python assembler, and the batch run script to Chinese. Key changes include: - Verilog files (.v): - Header comments (Description, Features, Revision, Additional Comments) translated and updated. - Inline comments translated to Chinese. - Removed [FIX], [NEW] tags, incorporating relevant information into the comments. - assembler.py: - Main docstring and inline comments translated to Chinese. - Removed [FIX] style tags, with details moved to a revision history in the docstring. - Ensured no functional code changes were made. - run.bat: - All user-facing `echo` prompts translated to Chinese. - Comments (::) reviewed and standardized in Chinese. The codebase's logic and functionality remain unchanged. This effort improves readability and maintainability for Chinese-speaking developers by providing comprehensive and standardized documentation directly within the code. Co-authored-by: google-labs-jules[bot] <161369871+google-labs-jules[bot]@users.noreply.github.com>
68 lines
3.0 KiB
Verilog
68 lines
3.0 KiB
Verilog
`timescale 1ns / 1ps
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/*******************************************************************************
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** Company: Nantong University
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** Engineer: あやせももこ
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**
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** Create Date: 2025-06-16
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** Design Name: LA32R Single Cycle CPU
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** Module Name: pc
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** Project Name: Computer Architecture Course Design
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** Target Devices: Any FPGA
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** Tool Versions: Vivado 2018.1
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** Description:
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** This module implements the Program Counter (PC) and its update logic.
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** The PC is a 32-bit register that holds the address of the instruction
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** to be fetched. It updates on every clock cycle.
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**
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** Update Logic:
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** - 若无分支或跳转 (pcsource=0): PC_next = PC_current + 4
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** - 若发生分支或跳转 (pcsource=1): PC_next = PC_current + imm_ext (分支/跳转目标地址)
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** (其中 imm_ext 是已经过符号扩展和适当左移的偏移量)
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** Features:
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** - 32位程序计数器。
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** - 同步复位功能，复位时PC置为0x00000000。
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** - 在每个时钟上升沿更新PC值。
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** - 支持顺序执行 (PC + 4)。
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** - 支持基于立即数偏移量的分支和跳转。
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** Revision:
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** Revision 0.01 - 文件创建及基本功能实现。
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** Additional Comments:
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** - `imm_ext` 输入假定已经由立即数扩展单元处理过（例如，对于分支指令，已经左移两位）。
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*******************************************************************************/
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module pc (
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input wire clk, // 时钟信号输入
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input wire rst, // 复位信号输入 (高有效)
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input wire pcsource, // PC下一地址来源选择信号 (0: PC+4; 1: 分支/跳转目标)
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input wire [31:0] imm_ext, // 来自立即数扩展单元的32位扩展后立即数 (用作偏移量)
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output reg [31:0] pc_out // 输出当前的PC值 (即当前指令地址)
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);
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wire [31:0] pc_plus_4; // 存储PC + 4的结果
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wire [31:0] pc_branch; // 存储分支或跳转目标地址
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wire [31:0] pc_next; // 存储下一个PC的值
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// PC寄存器逻辑：在时钟上升沿或复位信号有效时更新
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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pc_out <= 32'h00000000; // 系统复位时，PC清零
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end else begin
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pc_out <= pc_next; // 否则，PC更新为pc_next的值
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end
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end
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// PC下一状态逻辑 (组合逻辑)
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// 计算PC顺序递增4的值 (指向下一条指令)
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assign pc_plus_4 = pc_out + 32'd4;
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// 计算分支/跳转目标地址。imm_ext是带符号的偏移量，
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// 对于分支指令，imm_extender模块已经将其处理为乘以4之后的值（即左移两位）。
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assign pc_branch = pc_out + imm_ext;
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// 根据pcsource信号选择下一个PC值：
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// 如果pcsource为1 (表示发生分支或跳转)，则pc_next为计算出的目标地址pc_branch。
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// 如果pcsource为0 (表示顺序执行)，则pc_next为pc_plus_4。
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assign pc_next = pcsource ? pc_branch : pc_plus_4;
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endmodule
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