80 lines
3.2 KiB
Verilog
80 lines
3.2 KiB
Verilog
`timescale 1ns / 1ps
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/*******************************************************************************
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** Company: Nantong University
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** Engineer: あやせももこ
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**
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** Create Date: 2025-06-16
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** Design Name: LA32R Single Cycle CPU
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** Module Name: alu
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** Project Name: Computer Architecture Course Design
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** Target Devices: Any FPGA
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** Tool Versions: Vivado 2018.1
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** Description:
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** This module implements the Arithmetic Logic Unit (ALU) for the LA32R CPU.
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**
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** [FIXED] The implementation of SLT now uses the $signed() system function
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** to correctly handle comparisons that could cause overflow, such as
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** comparing a positive and a negative number.
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**
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** Revision:
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** Revision 0.02 - Corrected SLT implementation using $signed().
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** Revision 0.01 - File Created
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**
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*******************************************************************************/
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module alu (
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input wire [31:0] a, // 操作数 A (Operand A)
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input wire [31:0] b, // 操作数 B (Operand B)
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input wire [3:0] alu_op, // ALU 操作控制码 (ALU Operation Control Code)
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output reg [31:0] result, // 运算结果 (Result)
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output wire zero, // 零标志位 (Zero Flag)
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output wire lt // 小于标志位 (Less Than Flag for BLT)
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);
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// 定义ALU操作码的参数，增强可读性
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// Define parameters for ALU operations to enhance readability
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localparam ALU_ADD = 4'b0000;
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localparam ALU_SUB = 4'b0001;
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localparam ALU_AND = 4'b0010;
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localparam ALU_OR = 4'b0011;
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localparam ALU_NOR = 4'b0100;
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localparam ALU_SLT = 4'b0101;
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localparam ALU_SLTU = 4'b0110;
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// 减法结果的临时线网
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// Temporary wire for subtraction result
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wire [31:0] sub_result = a - b;
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// [FIX] 使用$signed()进行稳健的有符号比较
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// [FIX] Use $signed() for robust signed comparison
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wire slt_res = ($signed(a) < $signed(b));
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// 无符号比较
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// Unsigned comparison
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wire sltu_res = (a < b);
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// 主组合逻辑: 根据alu_op计算结果
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// Main combinational logic: calculate result based on alu_op
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always @(*) begin
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case (alu_op)
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ALU_ADD: result = a + b; // 加法 (Addition)
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ALU_SUB: result = sub_result; // 减法 (Subtraction)
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ALU_AND: result = a & b; // 与 (AND)
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ALU_OR: result = a | b; // 或 (OR)
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ALU_NOR: result = ~(a | b); // 或非 (NOR)
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ALU_SLT: result = {31'b0, slt_res}; // 有符号小于比较 (Set on Less Than, Signed)
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ALU_SLTU: result = {31'b0, sltu_res}; // 无符号小于比较 (Set on Less Than, Unsigned)
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default: result = 32'hxxxxxxxx; // 默认情况，输出不定态 (Default case, output undefined)
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endcase
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end
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// 零标志位输出: 当减法结果为0时置1，用于BEQ指令
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// Zero flag output: set to 1 when the subtraction result is zero, for BEQ instruction
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assign zero = (sub_result == 32'h00000000);
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// 小于标志位输出: 用于BLT指令
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// Less Than flag output: for BLT instruction
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assign lt = slt_res;
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endmodule |