57 lines
1.8 KiB
Verilog
57 lines
1.8 KiB
Verilog
`timescale 1ns / 1ps
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/*******************************************************************************
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** Company: Nantong University
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** Engineer: あやせももこ
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**
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** Create Date: 2025-06-16
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** Design Name: LA32R Single Cycle CPU
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** Module Name: pc
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** Project Name: Computer Architecture Course Design
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** Target Devices: Any FPGA
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** Tool Versions: Vivado 2018.1
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** Description:
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** This module implements the Program Counter (PC) and its update logic.
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** The PC is a 32-bit register that holds the address of the instruction
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** to be fetched. It updates on every clock cycle.
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**
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** Update Logic:
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** - If no branch/jump: PC_next = PC_current + 4
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** - If branch/jump taken: PC_next = Branch/Jump Target Address
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**
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** Revision:
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** Revision 0.01 - File Created
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**
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*******************************************************************************/
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module pc (
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input wire clk, // 时钟 (Clock)
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input wire rst, // 复位 (Reset)
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input wire pcsource, // PC下一个地址来源选择 (PC next address source selection)
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input wire [31:0] imm_ext, // 来自立即数扩展单元的偏移量 (Offset from immediate extender)
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output reg [31:0] pc_out // 当前PC值 (Current PC value)
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);
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wire [31:0] pc_plus_4;
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wire [31:0] pc_branch;
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wire [31:0] pc_next;
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// PC寄存器
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// PC register
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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pc_out <= 32'h00000000; // 复位到0地址
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end else begin
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pc_out <= pc_next;
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end
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end
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// PC更新逻辑
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// PC update logic
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assign pc_plus_4 = pc_out + 32'd4;
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assign pc_branch = pc_out + imm_ext; // 偏移量已经左移两位
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assign pc_next = pcsource ? pc_branch : pc_plus_4;
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endmodule
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