Initial commit
This commit is contained in:
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@OrCAD Simulation Server Version: 1.0
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@Settings: 0 1
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@General:
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ProfileName= "ACExpSim1(2)"
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ProfileFile= "ACExpSim1(2).sim"
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Connectivity= "SCHEMATIC1.net"
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NetlistFile= "ACExpSim1(2).cir"
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DataFile= "ACExpSim1(2).dat"
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OutFile= "ACExpSim1(2).out"
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Notes=
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@#$BEGINNOTES
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@#$ENDNOTES
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@End General
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@Analysis: 0 1
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+0 0 0 0
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+0 "1000ns"
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@End Analysis
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@End Analysis
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+7 ""
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LoadFile 0 ""
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SaveFile 0 ""
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@End Analysis
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@Analysis: 5 0
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@End Analysis
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@Analysis: 11 1
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+2236960 0
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@Analysis: 13 1
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@Analysis: 14 1
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+1 1 1 "*"
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@End Analysis
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@End Analysis
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@Analysis: 16 0
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+0 "0"
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+2 "chkpt_default, , ,"
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@End Analysis
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@Analysis: 17 0
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+0 "-1"
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+1 ""
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+2 "-1"
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+3 "-1"
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+4 "1"
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@End Analysis
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Binary file not shown.
@@ -0,0 +1,18 @@
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** Profile: "SCHEMATIC1-ACExpSim1(2)" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\1-2\AnalogCircuitExp1(2)-PSpiceFiles\SCHEMATIC1\ACExpSim1(2).sim ]
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** Creating circuit file "ACExpSim1(2).cir"
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** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
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*Libraries:
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* Profile Libraries :
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* Local Libraries :
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* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file:
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.lib "nomd.lib"
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*Analysis directives:
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.TRAN 0 1000ns 0
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.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
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.INC "..\SCHEMATIC1.net"
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.END
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@@ -0,0 +1 @@
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lib=D:\OrCAD\OrCAD_16.5_Lite\tools\PSpice\Library\eval.lib, offset=27170, size=1127
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Binary file not shown.
@@ -0,0 +1,169 @@
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**** 11/29/24 11:49:30 ******* PSpice Lite (April 2011) ******* ID# 10813 ****
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** Profile: "SCHEMATIC1-ACExpSim1(2)" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\1-2\AnalogCircuitExp1(2)-PSpiceFiles\SCHEMATI
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**** CIRCUIT DESCRIPTION
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******************************************************************************
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** Creating circuit file "ACExpSim1(2).cir"
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** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
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*Libraries:
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* Profile Libraries :
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* Local Libraries :
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* From [PSPICE NETLIST] section of D:\OrCAD\OrCAD_16.5_Lite\tools\pspice\PSpice.ini file:
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.lib "nomd.lib"
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*Analysis directives:
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.TRAN 0 1000ns 0
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.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
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.INC "..\SCHEMATIC1.net"
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**** INCLUDING SCHEMATIC1.net ****
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* source ANALOGCIRCUITEXP1(2)
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R_Rf N00912 OUT 100k TC=0,0
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R_R1 VI1 N00912 10k TC=0,0
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X_U1 N00902 N00912 N00892 N00886 OUT uA741
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R_R3 0 N00902 100k TC=0,0
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V_+V N00892 0 15Vdc
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V_-V 0 N00886 15Vdc
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V_V1 VI1 0 -5Vdc
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V_V2 VI2 0 -15Vdc
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R_R2 VI2 N00902 10k TC=0,0
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**** RESUMING ACExpSim1(2).cir ****
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.END
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**** 11/29/24 11:49:30 ******* PSpice Lite (April 2011) ******* ID# 10813 ****
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** Profile: "SCHEMATIC1-ACExpSim1(2)" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\1-2\AnalogCircuitExp1(2)-PSpiceFiles\SCHEMATI
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**** Diode MODEL PARAMETERS
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******************************************************************************
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X_U1.dx
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IS 800.000000E-18
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RS 1
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**** 11/29/24 11:49:30 ******* PSpice Lite (April 2011) ******* ID# 10813 ****
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** Profile: "SCHEMATIC1-ACExpSim1(2)" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\1-2\AnalogCircuitExp1(2)-PSpiceFiles\SCHEMATI
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**** BJT MODEL PARAMETERS
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******************************************************************************
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X_U1.qx
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NPN
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LEVEL 1
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IS 800.000000E-18
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BF 93.75
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NF 1
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BR 1
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NR 1
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ISS 0
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RE 0
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RC 0
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CJE 0
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VJE .75
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CJC 0
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VJC .75
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MJC .33
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XCJC 1
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CJS 0
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VJS .75
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KF 0
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AF 1
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CN 2.42
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D .87
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**** 11/29/24 11:49:30 ******* PSpice Lite (April 2011) ******* ID# 10813 ****
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** Profile: "SCHEMATIC1-ACExpSim1(2)" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\1-2\AnalogCircuitExp1(2)-PSpiceFiles\SCHEMATI
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**** INITIAL TRANSIENT SOLUTION TEMPERATURE = 27.000 DEG C
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******************************************************************************
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NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
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( OUT) -14.6120 ( VI1) -5.0000 ( VI2) -15.0000 (N00886) -15.0000
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(N00892) 15.0000 (N00902) -13.6360 (N00912) -5.8753 (X_U1.6) 1.4472
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(X_U1.7) -14.6180 (X_U1.8) -14.6180 (X_U1.9) 0.0000 (X_U1.10) -6.5131
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(X_U1.11) 14.9230 (X_U1.12) 15.0000
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(X_U1.13) -6.4862 (X_U1.14) -6.5131
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(X_U1.53) 14.0000 (X_U1.54) -14.0000
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(X_U1.90) -.1027 (X_U1.91) 40.0000
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(X_U1.92) -40.0000 (X_U1.99) 0.0000
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VOLTAGE SOURCE CURRENTS
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NAME CURRENT
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V_+V -1.667E-03
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V_-V -1.652E-03
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V_V1 -8.753E-05
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V_V2 1.364E-04
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X_U1.vb 1.447E-05
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X_U1.vc 2.861E-11
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X_U1.ve -1.534E-05
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X_U1.vlim -1.027E-04
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X_U1.vlp -4.010E-11
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X_U1.vln -3.990E-11
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TOTAL POWER DISSIPATION 5.14E-02 WATTS
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JOB CONCLUDED
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**** 11/29/24 11:49:30 ******* PSpice Lite (April 2011) ******* ID# 10813 ****
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** Profile: "SCHEMATIC1-ACExpSim1(2)" [ F:\Schoolwork\AnalogCircuit\AnalogCircuitExp1\1-2\AnalogCircuitExp1(2)-PSpiceFiles\SCHEMATI
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**** JOB STATISTICS SUMMARY
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******************************************************************************
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Total job time (using Solver 1) = .02
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@@ -0,0 +1,15 @@
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.ALIASES
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R_Rf Rf(1=N00912 2=OUT ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS818@ANALOG.R.Normal(chips)
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R_R1 R1(1=VI1 2=N00912 ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS776@ANALOG.R.Normal(chips)
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X_U1 U1(+=N00902 -=N00912 V+=N00892 V-=N00886 OUT=OUT ) CN
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+@ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS698@EVAL.uA741.Normal(chips)
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R_R3 R3(1=0 2=N00902 ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS798@ANALOG.R.Normal(chips)
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V_+V +V(+=N00892 -=0 ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS756@SOURCE.VDC.Normal(chips)
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V_-V -V(+=0 -=N00886 ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS736@SOURCE.VDC.Normal(chips)
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V_V1 V1(+=VI1 -=0 ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS1192@SOURCE.VDC.Normal(chips)
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V_V2 V2(+=VI2 -=0 ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS1223@SOURCE.VDC.Normal(chips)
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R_R2 R2(1=VI2 2=N00902 ) CN @ANALOGCIRCUITEXP1(2).SCHEMATIC1(sch_1):INS1270@ANALOG.R.Normal(chips)
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_ _(OUT=OUT)
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_ _(vi1=VI1)
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_ _(vi2=VI2)
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.ENDALIASES
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@@ -0,0 +1,10 @@
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* source ANALOGCIRCUITEXP1(2)
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R_Rf N00912 OUT 100k TC=0,0
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R_R1 VI1 N00912 10k TC=0,0
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X_U1 N00902 N00912 N00892 N00886 OUT uA741
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R_R3 0 N00902 100k TC=0,0
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V_+V N00892 0 15Vdc
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V_-V 0 N00886 15Vdc
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V_V1 VI1 0 -5Vdc
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V_V2 VI2 0 -15Vdc
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R_R2 VI2 N00902 10k TC=0,0
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@@ -0,0 +1,96 @@
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("FILE_TYPE" "PMAP File"
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("devices"
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("R")
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("VDC")
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)
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("instances"
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||||
("Rf"
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||||
("device_name" "R")
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||||
("pspice_path" "R_Rf")
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("level" "0")
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||||
("model_params"
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||||
("VALUE"
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||||
("value" "100k")
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("pspice_param" "VALUE")
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)
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)
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||||
)
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||||
("R1"
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||||
("device_name" "R")
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||||
("pspice_path" "R_R1")
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||||
("level" "0")
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||||
("model_params"
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||||
("VALUE"
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||||
("value" "10k")
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||||
("pspice_param" "VALUE")
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||||
)
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||||
)
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||||
)
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||||
("R3"
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||||
("device_name" "R")
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||||
("pspice_path" "R_R3")
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||||
("level" "0")
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||||
("model_params"
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||||
("VALUE"
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||||
("value" "100k")
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||||
("pspice_param" "VALUE")
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)
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||||
)
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||||
)
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("+V"
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||||
("device_name" "VDC")
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||||
("pspice_path" "V_+V")
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||||
("level" "0")
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||||
("model_params"
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||||
("DC"
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||||
("value" "15Vdc")
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||||
("pspice_param" "DC")
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||||
)
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||||
)
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||||
)
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||||
("-V"
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||||
("device_name" "VDC")
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||||
("pspice_path" "V_-V")
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||||
("level" "0")
|
||||
("model_params"
|
||||
("DC"
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||||
("value" "15Vdc")
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||||
("pspice_param" "DC")
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||||
)
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||||
)
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||||
)
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||||
("V1"
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||||
("device_name" "VDC")
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||||
("pspice_path" "V_V1")
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||||
("level" "0")
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||||
("model_params"
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||||
("DC"
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||||
("value" "-5Vdc")
|
||||
("pspice_param" "DC")
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||||
)
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||||
)
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||||
)
|
||||
("V2"
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||||
("device_name" "VDC")
|
||||
("pspice_path" "V_V2")
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||||
("level" "0")
|
||||
("model_params"
|
||||
("DC"
|
||||
("value" "-15Vdc")
|
||||
("pspice_param" "DC")
|
||||
)
|
||||
)
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||||
)
|
||||
("R2"
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||||
("device_name" "R")
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||||
("pspice_path" "R_R2")
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||||
("level" "0")
|
||||
("model_params"
|
||||
("VALUE"
|
||||
("value" "10k")
|
||||
("pspice_param" "VALUE")
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
Reference in New Issue
Block a user