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2025-11-06 09:35:54 +08:00
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<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Tue Jul 1 23:58:17 2025">
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Exp1/Exp1.xpr Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="ConstrsType" Val="XDC"/>
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</Simulators>
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<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
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<Step Id="write_bitstream"/>
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<Board/>
</Project>