Initial commit

Exp2/Exp2.srcs/sources_1/new/RAM.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2025/05/30 20:50:37
+// Design Name: 
+// Module Name: RAM
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module RAM (
+    input  wire        clk,
+    input  wire        MemWrEn,
+    input  wire [31:0] addr,
+    input  wire [31:0] data_in,
+    output wire [31:0] data_out
+);
+    reg [31:0] memory_array [2^32-1:0];
+    always @(posedge clk) begin
+        if (MemWrEn) begin
+            memory_array[addr] <= data_in;
+        end
+    end
+    assign data_out = memory_array[addr];
+endmodule