Initial commit
This commit is contained in:
1
Experiments/Exp1/Exp1.ip_user_files/README.txt
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1
Experiments/Exp1/Exp1.ip_user_files/README.txt
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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
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71
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/glbl.v
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71
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/glbl.v
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
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`ifndef GLBL
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`define GLBL
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`timescale 1 ps / 1 ps
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module glbl ();
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parameter ROC_WIDTH = 100000;
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parameter TOC_WIDTH = 0;
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//-------- STARTUP Globals --------------
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wire GSR;
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wire GTS;
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wire GWE;
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wire PRLD;
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tri1 p_up_tmp;
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tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
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wire PROGB_GLBL;
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wire CCLKO_GLBL;
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wire FCSBO_GLBL;
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wire [3:0] DO_GLBL;
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wire [3:0] DI_GLBL;
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reg GSR_int;
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reg GTS_int;
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reg PRLD_int;
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//-------- JTAG Globals --------------
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wire JTAG_TDO_GLBL;
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wire JTAG_TCK_GLBL;
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wire JTAG_TDI_GLBL;
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wire JTAG_TMS_GLBL;
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wire JTAG_TRST_GLBL;
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reg JTAG_CAPTURE_GLBL;
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reg JTAG_RESET_GLBL;
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reg JTAG_SHIFT_GLBL;
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reg JTAG_UPDATE_GLBL;
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reg JTAG_RUNTEST_GLBL;
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reg JTAG_SEL1_GLBL = 0;
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reg JTAG_SEL2_GLBL = 0 ;
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reg JTAG_SEL3_GLBL = 0;
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reg JTAG_SEL4_GLBL = 0;
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reg JTAG_USER_TDO1_GLBL = 1'bz;
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reg JTAG_USER_TDO2_GLBL = 1'bz;
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reg JTAG_USER_TDO3_GLBL = 1'bz;
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reg JTAG_USER_TDO4_GLBL = 1'bz;
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assign (strong1, weak0) GSR = GSR_int;
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assign (strong1, weak0) GTS = GTS_int;
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assign (weak1, weak0) PRLD = PRLD_int;
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initial begin
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GSR_int = 1'b1;
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PRLD_int = 1'b1;
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#(ROC_WIDTH)
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GSR_int = 1'b0;
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PRLD_int = 1'b0;
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end
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initial begin
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GTS_int = 1'b1;
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#(TOC_WIDTH)
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GTS_int = 1'b0;
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end
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endmodule
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`endif
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11
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/tb_exp1.tcl
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11
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/tb_exp1.tcl
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set curr_wave [current_wave_config]
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if { [string length $curr_wave] == 0 } {
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if { [llength [get_objects]] > 0} {
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add_wave /
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set_property needs_save false [current_wave_config]
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} else {
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send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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}
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}
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run 1000ns
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11
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/tb_exp1_vlog.prj
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11
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/tb_exp1_vlog.prj
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# compile verilog/system verilog design source files
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verilog xil_defaultlib \
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"../../../../../Shared/ALU.v" \
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"../../../../../Shared/Ext.v" \
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"../../../../Exp1.srcs/sim_1/new/tb_exp1.v" \
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# compile glbl module
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verilog xil_defaultlib "glbl.v"
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# Do not sort compile order
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nosort
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12
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/webtalk.jou
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12
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/webtalk.jou
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#-----------------------------------------------------------
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# Webtalk v2018.1 (64-bit)
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# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
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# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
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# Start of session at: Wed Jul 2 00:04:46 2025
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# Process ID: 16772
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# Current directory: D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim
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# Command line: wbtcv.exe -mode batch -source D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/webtalk/xsim_webtalk.tcl -notrace
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# Log file: D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/webtalk.log
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# Journal file: D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim\webtalk.jou
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#-----------------------------------------------------------
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source D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xsim.dir/tb_exp1_behav/webtalk/xsim_webtalk.tcl -notrace
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BIN
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xelab.pb
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BIN
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xelab.pb
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-wto "37682ab63326475c8c4702befd41712b" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_exp1_behav" "xil_defaultlib.tb_exp1" "xil_defaultlib.glbl" -log "elaborate.log"
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@@ -0,0 +1 @@
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Breakpoint File Version 1.0
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@@ -0,0 +1,118 @@
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/**********************************************************************/
|
||||
/* ____ ____ */
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||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
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||||
/* / / All Right Reserved. */
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||||
/* /---/ /\ */
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||||
/* \ \ / \ */
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||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
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||||
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#include "iki.h"
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#include <string.h>
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#include <math.h>
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#ifdef __GNUC__
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#include <stdlib.h>
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#else
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#include <malloc.h>
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||||
#define alloca _alloca
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#endif
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||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/**********************************************************************/
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||||
|
||||
|
||||
#include "iki.h"
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#include <string.h>
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#include <math.h>
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#ifdef __GNUC__
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#include <stdlib.h>
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#else
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#include <malloc.h>
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#define alloca _alloca
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#endif
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typedef void (*funcp)(char *, char *);
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extern int main(int, char**);
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extern void execute_6(char*, char *);
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extern void execute_16(char*, char *);
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extern void execute_17(char*, char *);
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extern void execute_18(char*, char *);
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extern void execute_19(char*, char *);
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extern void execute_20(char*, char *);
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extern void execute_21(char*, char *);
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extern void execute_22(char*, char *);
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extern void execute_3(char*, char *);
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extern void execute_5(char*, char *);
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extern void execute_11(char*, char *);
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extern void execute_12(char*, char *);
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extern void execute_13(char*, char *);
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extern void execute_14(char*, char *);
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extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
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extern void execute_8(char*, char *);
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extern void execute_9(char*, char *);
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extern void execute_10(char*, char *);
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extern void execute_23(char*, char *);
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extern void execute_24(char*, char *);
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extern void execute_25(char*, char *);
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extern void execute_26(char*, char *);
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extern void execute_27(char*, char *);
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extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
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funcp funcTab[24] = {(funcp)execute_6, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_3, (funcp)execute_5, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_23, (funcp)execute_24, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)vlog_transfunc_eventcallback};
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const int NumRelocateId= 24;
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void relocate(char *dp)
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{
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iki_relocate(dp, "xsim.dir/tb_exp1_behav/xsim.reloc", (void **)funcTab, 24);
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/*Populate the transaction function pointer field in the whole net structure */
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}
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void sensitize(char *dp)
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{
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iki_sensitize(dp, "xsim.dir/tb_exp1_behav/xsim.reloc");
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}
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void simulate(char *dp)
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{
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iki_schedule_processes_at_time_zero(dp, "xsim.dir/tb_exp1_behav/xsim.reloc");
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// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
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iki_execute_processes();
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// Schedule resolution functions for the multiply driven Verilog nets that have strength
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||||
// Schedule transaction functions for the singly driven Verilog nets that have strength
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||||
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||||
}
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#include "iki_bridge.h"
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void relocate(char *);
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void sensitize(char *);
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void simulate(char *);
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extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
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extern void implicit_HDL_SCinstatiate();
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extern int xsim_argc_copy ;
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extern char** xsim_argv_copy ;
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int main(int argc, char **argv)
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||||
{
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iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
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iki_set_sv_type_file_path_name("xsim.dir/tb_exp1_behav/xsim.svtype");
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iki_set_crvs_dump_file_path_name("xsim.dir/tb_exp1_behav/xsim.crvsdump");
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||||
void* design_handle = iki_create_design("xsim.dir/tb_exp1_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
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||||
iki_set_rc_trial_count(100);
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||||
(void) design_handle;
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||||
return iki_simulate_design();
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||||
}
|
||||
Binary file not shown.
BIN
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xvlog.pb
Normal file
BIN
Experiments/Exp1/Exp1.sim/sim_1/behav/xsim/xvlog.pb
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Binary file not shown.
48
Experiments/Exp1/Exp1.srcs/sim_1/new/tb_exp1.v
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48
Experiments/Exp1/Exp1.srcs/sim_1/new/tb_exp1.v
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`timescale 1ns / 1ps
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module tb_exp1;
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reg [31:0] alu_a, alu_b;
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reg [2:0] AluCtrl;
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wire [31:0] AddResult;
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||||
wire Zero;
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reg [31:0] Ext_DataIn;
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reg [1:0] ExtOp;
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wire [31:0] Ext_DataOut;
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|
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ALU u_ALU (
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.a(alu_a), .b(alu_b), .AluCtrl(AluCtrl),
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.AddResult(AddResult), .Zero(Zero)
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||||
);
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||||
|
||||
Ext u_Ext (
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.DataIn(Ext_DataIn), .ExtOp(ExtOp), .DataOut(Ext_DataOut)
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||||
);
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||||
|
||||
initial begin
|
||||
$display("----------------- 开始实验一仿真 -----------------");
|
||||
$display("=========== 测试 ALU 模块 ===========");
|
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alu_a = 32'd10; alu_b = 32'd5; AluCtrl = 3'b000; #10;
|
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$display("ALU ADD: %d + %d = %d", alu_a, alu_b, AddResult);
|
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alu_a = 32'd10; alu_b = 32'd10; AluCtrl = 3'b001; #10;
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$display("ALU SUB: %d - %d = %d, Zero = %b", alu_a, alu_b, AddResult, Zero);
|
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alu_a = 32'hFFFFFFFF;
|
||||
alu_b = 32'd1;
|
||||
AluCtrl = 3'b101; #10;
|
||||
$display("ALU SLT: $signed(%h) < $signed(%h) is %d", alu_a, alu_b, AddResult);
|
||||
AluCtrl = 3'b110; #10;
|
||||
$display("ALU SLTU: %h < %h is %d", alu_a, alu_b, AddResult);
|
||||
|
||||
$display("\n=========== 测试 Ext 模块 ===========");
|
||||
Ext_DataIn = 32'h02A4C503;
|
||||
ExtOp = 2'b00; #10;
|
||||
$display("ExtOp=00, DataIn=%h, DataOut=%h (符号扩展[21:10])", Ext_DataIn, Ext_DataOut);
|
||||
ExtOp = 2'b01; #10;
|
||||
$display("ExtOp=01, DataIn=%h, DataOut=%h (符号扩展[25:10] << 2)", Ext_DataIn, Ext_DataOut);
|
||||
ExtOp = 2'b10; #10;
|
||||
$display("ExtOp=10, DataIn=%h, DataOut=%h ([24:5] << 12)", Ext_DataIn, Ext_DataOut);
|
||||
|
||||
$display("\n----------------- 实验一仿真结束 -----------------");
|
||||
$stop;
|
||||
end
|
||||
endmodule
|
||||
153
Experiments/Exp1/Exp1.xpr
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153
Experiments/Exp1/Exp1.xpr
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|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.1 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="36" Path="D:/Schoolwork/ComputerComposition/Experiments/Exp1/Exp1.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="37682ab63326475c8c4702befd41712b"/>
|
||||
<Option Name="Part" Val="xc7a35tcsg324-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="2"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../Shared/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Shared/Ext.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="ALU"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_exp1.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="tb_exp1"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
</Project>
|
||||
Reference in New Issue
Block a user